drm/i915/display/xelpd: Implement Wa_14013475917

This workaround requires that VIDEO_DIP_ENABLE_VSC_HSW is never set
with PSR.

BSpec: 54369
BSpec: 54077
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210418002126.87882-5-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 299a94e78d0376ad892ae72ac54eae1b3f39a800..c03a4603e213c5e163bd79504e95472d5ef074db 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -532,6 +532,11 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
                               hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
                               0);
 
+       /* Wa_14013475917 */
+       if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
+           type == DP_SDP_VSC)
+               return;
+
        val |= hsw_infoframe_enable(type);
        intel_de_write(dev_priv, ctl_reg, val);
        intel_de_posting_read(dev_priv, ctl_reg);