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(parent: 13a7ebb) | patch
net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
authorJisheng Zhang <jszhang@marvell.com>
Wed, 30 Mar 2016 11:53:41 +0000 (19:53 +0800)
committerDavid S. Miller <davem@davemloft.net>
Thu, 31 Mar 2016 19:15:01 +0000 (15:15 -0400)
commitb7854efce20be7c7bcd43424dee027124e9af27f
tree575b50e44f64c2bb478199db773e15b7d376df20tree
parent13a7ebb38a659254e71a4a95cf39429a9287912bcommit | diff
net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES

The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline
size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/mvpp2.c diff | blob | history
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