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(parent: 996defd) | patch
net: axienet: fix number of TX ring slots for available check
authorRobert Hancock <robert.hancock@calian.com>
Tue, 18 Jan 2022 21:41:30 +0000 (15:41 -0600)
committerDavid S. Miller <davem@davemloft.net>
Wed, 19 Jan 2022 11:29:14 +0000 (11:29 +0000)
commitaba57a823d2985a2cc8c74a2535f3a88e68d9424
treece2128ed41cdccbea07a53d5608ae4993edce4e4tree
parent996defd7f8b5dafc1d480b7585c7c62437f80c3ccommit | diff
net: axienet: fix number of TX ring slots for available check

The check for the number of available TX ring slots was off by 1 since a
slot is required for the skb header as well as each fragment. This could
result in overwriting a TX ring slot that was still in use.

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/xilinx/xilinx_axienet_main.c diff | blob | history
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