clk: renesas: rcar-gen3: Add dummy SDnH clock
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Wed, 10 Nov 2021 19:15:50 +0000 (20:15 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 19 Nov 2021 10:27:58 +0000 (11:27 +0100)
commita31cf51bf6b4bf78ccb1c9fb40ea6231cf3df433
treeda1a89c9140b848144267d16ff88524f6d7db4f3
parent161450134ae9bab3778c5f5732941162626d0eaa
clk: renesas: rcar-gen3: Add dummy SDnH clock

Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rcar-cpg-lib.c
drivers/clk/renesas/rcar-cpg-lib.h
drivers/clk/renesas/rcar-gen3-cpg.c
drivers/clk/renesas/rcar-gen3-cpg.h