drm/i915/xelpmp: Consider GSI offset when doing MCR lookups
authorMatt Roper <matthew.d.roper@intel.com>
Tue, 14 Feb 2023 00:19:06 +0000 (16:19 -0800)
committerJani Nikula <jani.nikula@intel.com>
Thu, 23 Feb 2023 11:52:33 +0000 (13:52 +0200)
commit33c25354939099b76ecb6c82d1c7c50400fbcca6
tree974543d5f65ac2fd73e99cc350ad325be5d8a910
parent8038510b1fe443ffbc0e356db5f47cbb8678a594
drm/i915/xelpmp: Consider GSI offset when doing MCR lookups

MCR range tables use the final MMIO offset of a register (including the
0x380000 GSI offset when applicable).  Since the i915_mcr_reg_t passed
as a parameter during steering lookup does not include the GSI offset,
we need to add it back in for GSI registers before searching the tables.

Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230214001906.1477370-1-matthew.d.roper@intel.com
(cherry picked from commit d6683bbe70d4cdbf3da6acecf7d569cc6f0b4382)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/gt/intel_gt_mcr.c