spi: fsl_spi: Don't change speed while chipselect is active
[sfrench/cifs-2.6.git] / drivers / spi / spi-fsl-spi.c
index 731624f157fc0fa2122065b44bffa0b751d3451d..93152144fd2ec7ea4f456c1c14b79d4e9965501f 100644 (file)
@@ -333,13 +333,26 @@ static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 {
        struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
        struct spi_transfer *t;
+       struct spi_transfer *first;
+
+       first = list_first_entry(&m->transfers, struct spi_transfer,
+                                transfer_list);
 
        /*
         * In CPU mode, optimize large byte transfers to use larger
         * bits_per_word values to reduce number of interrupts taken.
+        *
+        * Some glitches can appear on the SPI clock when the mode changes.
+        * Check that there is no speed change during the transfer and set it up
+        * now to change the mode without having a chip-select asserted.
         */
-       if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
-               list_for_each_entry(t, &m->transfers, transfer_list) {
+       list_for_each_entry(t, &m->transfers, transfer_list) {
+               if (t->speed_hz != first->speed_hz) {
+                       dev_err(&m->spi->dev,
+                               "speed_hz cannot change during message.\n");
+                       return -EINVAL;
+               }
+               if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
                        if (t->len < 256 || t->bits_per_word != 8)
                                continue;
                        if ((t->len & 3) == 0)
@@ -348,7 +361,7 @@ static int fsl_spi_prepare_message(struct spi_controller *ctlr,
                                t->bits_per_word = 16;
                }
        }
-       return 0;
+       return fsl_spi_setup_transfer(m->spi, first);
 }
 
 static int fsl_spi_transfer_one(struct spi_controller *controller,