Merge drm/drm-next into drm-misc-next-fixes
[sfrench/cifs-2.6.git] / drivers / gpu / drm / msm / adreno / a6xx_gpu_state.h
index 9560fc1b858a90da2169a853834ac536cfe1d4d7..5ddd32063bcc15695abb5b9e25688a0f8a4e6208 100644 (file)
@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
+/*
+ * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
 
 #ifndef _A6XX_CRASH_DUMP_H_
 #define _A6XX_CRASH_DUMP_H_
@@ -51,6 +54,7 @@ static const u32 a6xx_pc_vs_cluster[] = {
 #define CLUSTER_SP_PS  4
 #define CLUSTER_PS     5
 #define CLUSTER_VPC_PS 6
+#define CLUSTER_NONE    7
 
 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
        { .id = _id, .name = #_id,\
@@ -337,27 +341,6 @@ static const struct a6xx_registers a6xx_vbif_reglist =
 static const struct a6xx_registers a6xx_gbif_reglist =
                        REGS(a6xx_gbif_registers, 0, 0);
 
-static const u32 a7xx_ahb_registers[] = {
-       /* RBBM_STATUS */
-       0x210, 0x210,
-       /* RBBM_STATUS2-3 */
-       0x212, 0x213,
-};
-
-static const u32 a7xx_gbif_registers[] = {
-       0x3c00, 0x3c0b,
-       0x3c40, 0x3c42,
-       0x3c45, 0x3c47,
-       0x3c49, 0x3c4a,
-       0x3cc0, 0x3cd1,
-};
-
-static const struct a6xx_registers a7xx_ahb_reglist=
-       REGS(a7xx_ahb_registers, 0, 0);
-
-static const struct a6xx_registers a7xx_gbif_reglist =
-       REGS(a7xx_gbif_registers, 0, 0);
-
 static const u32 a6xx_gmu_gx_registers[] = {
        /* GMU GX */
        0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
@@ -534,4 +517,288 @@ static const struct a6xx_debugbus_block a650_debugbus_blocks[] = {
        DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100),
 };
 
+static const struct a6xx_debugbus_block a7xx_gbif_debugbus_blocks[] = {
+       DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
+       DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100),
+};
+
+static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = {
+       DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100),
+       DEBUGBUS(A7XX_DBGBUS_CX, 0x100),
+       DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
+};
+
+#define STATE_NON_CONTEXT 0
+#define STATE_TOGGLE_CTXT 1
+#define STATE_FORCE_CTXT_0 2
+#define STATE_FORCE_CTXT_1 3
+
+struct gen7_sel_reg {
+       unsigned int host_reg;
+       unsigned int cd_reg;
+       unsigned int val;
+};
+
+struct gen7_cluster_registers {
+       /* cluster_id: Cluster identifier */
+       int cluster_id;
+       /* pipe_id: Pipe Identifier */
+       int pipe_id;
+       /* context_id: one of STATE_ that identifies the context to dump */
+       int context_id;
+       /* regs: Pointer to an array of register pairs */
+       const u32 *regs;
+       /* sel: Pointer to a selector register to write before reading */
+       const struct gen7_sel_reg *sel;
+};
+
+struct gen7_sptp_cluster_registers {
+       /* cluster_id: Cluster identifier */
+       enum a7xx_cluster cluster_id;
+       /* statetype: SP block state type for the cluster */
+       enum a7xx_statetype_id statetype;
+       /* pipe_id: Pipe identifier */
+       enum a7xx_pipe pipe_id;
+       /* context_id: Context identifier */
+       int context_id;
+       /* location_id: Location identifier */
+       enum a7xx_state_location location_id;
+       /* regs: Pointer to the list of register pairs to read */
+       const u32 *regs;
+       /* regbase: Dword offset of the register block in the GPu register space */
+       unsigned int regbase;
+};
+
+struct gen7_shader_block {
+       /* statetype: Type identifer for the block */
+       u32 statetype;
+       /* size: Size of the block (in dwords) */
+       u32 size;
+       /* num_sps: The SP id to dump */
+       u32 num_sps;
+       /* num_usptps: The number of USPTPs to dump */;
+       u32 num_usptps;
+       /* pipe_id: Pipe identifier for the block data  */
+       u32 pipeid;
+       /* location: Location identifer for the block data */
+       u32 location;
+};
+
+struct gen7_reg_list {
+       const u32 *regs;
+       const struct gen7_sel_reg *sel;
+};
+
+/* adreno_gen7_x_y_snapshot.h defines which debugbus blocks a given family has, but the
+ * list of debugbus blocks is global on a7xx.
+ */
+
+#define A7XX_DEBUGBUS(_id, _count) [_id] = { .id = _id, .name = #_id, .count = _count },
+static const struct a6xx_debugbus_block a7xx_debugbus_blocks[] = {
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RBBM, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VSC, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_COM_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_GX, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_DBGC, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CX, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BR, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BV, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_LARC, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_SPTP, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RB_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RB_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RB_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RB_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RB_4, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_RB_5, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_WRAPPER, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_4, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_5, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_4, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_5, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_6, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_7, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USP_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USP_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USP_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USP_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USP_4, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USP_5, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_4, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_5, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_6, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_7, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_8, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_9, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_10, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_TP_11, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_4, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_5, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_6, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_7, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_8, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_9, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_10, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_11, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_3, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_4, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_5, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_0, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_1, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_2, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_SUBCORE, 0x100)
+       A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_CORE, 0x100)
+};
+
+#define A7XX_NAME(enumval) [enumval] = #enumval
+static const char *a7xx_statetype_names[] = {
+       A7XX_NAME(A7XX_TP0_NCTX_REG),
+       A7XX_NAME(A7XX_TP0_CTX0_3D_CVS_REG),
+       A7XX_NAME(A7XX_TP0_CTX0_3D_CPS_REG),
+       A7XX_NAME(A7XX_TP0_CTX1_3D_CVS_REG),
+       A7XX_NAME(A7XX_TP0_CTX1_3D_CPS_REG),
+       A7XX_NAME(A7XX_TP0_CTX2_3D_CPS_REG),
+       A7XX_NAME(A7XX_TP0_CTX3_3D_CPS_REG),
+       A7XX_NAME(A7XX_TP0_TMO_DATA),
+       A7XX_NAME(A7XX_TP0_SMO_DATA),
+       A7XX_NAME(A7XX_TP0_MIPMAP_BASE_DATA),
+       A7XX_NAME(A7XX_SP_NCTX_REG),
+       A7XX_NAME(A7XX_SP_CTX0_3D_CVS_REG),
+       A7XX_NAME(A7XX_SP_CTX0_3D_CPS_REG),
+       A7XX_NAME(A7XX_SP_CTX1_3D_CVS_REG),
+       A7XX_NAME(A7XX_SP_CTX1_3D_CPS_REG),
+       A7XX_NAME(A7XX_SP_CTX2_3D_CPS_REG),
+       A7XX_NAME(A7XX_SP_CTX3_3D_CPS_REG),
+       A7XX_NAME(A7XX_SP_INST_DATA),
+       A7XX_NAME(A7XX_SP_INST_DATA_1),
+       A7XX_NAME(A7XX_SP_LB_0_DATA),
+       A7XX_NAME(A7XX_SP_LB_1_DATA),
+       A7XX_NAME(A7XX_SP_LB_2_DATA),
+       A7XX_NAME(A7XX_SP_LB_3_DATA),
+       A7XX_NAME(A7XX_SP_LB_4_DATA),
+       A7XX_NAME(A7XX_SP_LB_5_DATA),
+       A7XX_NAME(A7XX_SP_LB_6_DATA),
+       A7XX_NAME(A7XX_SP_LB_7_DATA),
+       A7XX_NAME(A7XX_SP_CB_RAM),
+       A7XX_NAME(A7XX_SP_LB_13_DATA),
+       A7XX_NAME(A7XX_SP_LB_14_DATA),
+       A7XX_NAME(A7XX_SP_INST_TAG),
+       A7XX_NAME(A7XX_SP_INST_DATA_2),
+       A7XX_NAME(A7XX_SP_TMO_TAG),
+       A7XX_NAME(A7XX_SP_SMO_TAG),
+       A7XX_NAME(A7XX_SP_STATE_DATA),
+       A7XX_NAME(A7XX_SP_HWAVE_RAM),
+       A7XX_NAME(A7XX_SP_L0_INST_BUF),
+       A7XX_NAME(A7XX_SP_LB_8_DATA),
+       A7XX_NAME(A7XX_SP_LB_9_DATA),
+       A7XX_NAME(A7XX_SP_LB_10_DATA),
+       A7XX_NAME(A7XX_SP_LB_11_DATA),
+       A7XX_NAME(A7XX_SP_LB_12_DATA),
+       A7XX_NAME(A7XX_HLSQ_DATAPATH_DSTR_META),
+       A7XX_NAME(A7XX_HLSQ_L2STC_TAG_RAM),
+       A7XX_NAME(A7XX_HLSQ_L2STC_INFO_CMD),
+       A7XX_NAME(A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM),
+       A7XX_NAME(A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM),
+       A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM),
+       A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM),
+       A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_ICB_CVS_CB_BASE_TAG),
+       A7XX_NAME(A7XX_HLSQ_ICB_CPS_CB_BASE_TAG),
+       A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM),
+       A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM),
+       A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_1),
+       A7XX_NAME(A7XX_HLSQ_INST_RAM),
+       A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM),
+       A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM),
+       A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_INST_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM),
+       A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG),
+       A7XX_NAME(A7XX_HLSQ_INST_RAM_1),
+       A7XX_NAME(A7XX_HLSQ_STPROC_META),
+       A7XX_NAME(A7XX_HLSQ_BV_BE_META),
+       A7XX_NAME(A7XX_HLSQ_INST_RAM_2),
+       A7XX_NAME(A7XX_HLSQ_DATAPATH_META),
+       A7XX_NAME(A7XX_HLSQ_FRONTEND_META),
+       A7XX_NAME(A7XX_HLSQ_INDIRECT_META),
+       A7XX_NAME(A7XX_HLSQ_BACKEND_META),
+};
+
+static const char *a7xx_pipe_names[] = {
+       A7XX_NAME(A7XX_PIPE_NONE),
+       A7XX_NAME(A7XX_PIPE_BR),
+       A7XX_NAME(A7XX_PIPE_BV),
+       A7XX_NAME(A7XX_PIPE_LPAC),
+};
+
+static const char *a7xx_cluster_names[] = {
+       A7XX_NAME(A7XX_CLUSTER_NONE),
+       A7XX_NAME(A7XX_CLUSTER_FE),
+       A7XX_NAME(A7XX_CLUSTER_SP_VS),
+       A7XX_NAME(A7XX_CLUSTER_PC_VS),
+       A7XX_NAME(A7XX_CLUSTER_GRAS),
+       A7XX_NAME(A7XX_CLUSTER_SP_PS),
+       A7XX_NAME(A7XX_CLUSTER_VPC_PS),
+       A7XX_NAME(A7XX_CLUSTER_PS),
+};
+
 #endif