Merge tag 'drm-intel-next-2022-05-20' of git://anongit.freedesktop.org/drm/drm-intel...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_pm.c

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b3a5c3f5ce14139249ea19e92dcf1a735088f01e..42db41c8e3b3301094787e53816d6307c0ac8619 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2874,7 +2874,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 
                /* read the first set of memory latencies[0:3] */
                val = 0; /* data0 to be programmed to 0 for first set */
-               ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+               ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
                                     &val, NULL);
 
                if (ret) {
@@ -2893,7 +2893,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 
                /* read the second set of memory latencies[4:7] */
                val = 1; /* data0 to be programmed to 1 for second set */
-               ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+               ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
                                     &val, NULL);
                if (ret) {
                        drm_err(&dev_priv->drm,
@@ -3679,7 +3679,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
                u32 val = 0;
                int ret;
 
-               ret = snb_pcode_read(dev_priv,
+               ret = snb_pcode_read(&dev_priv->uncore,
                                     GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
                                     &val, NULL);
                if (ret) {
@@ -3748,7 +3748,7 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
                return;
 
        drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
-       ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+       ret = snb_pcode_write(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
                              GEN9_SAGV_ENABLE);
 
        /* We don't need to wait for SAGV when enabling */
@@ -3781,7 +3781,7 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
 
        drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
        /* bspec says to keep retrying for at least 1 ms */
-       ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+       ret = skl_pcode_request(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
                                GEN9_SAGV_DISABLE,
                                GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
                                1);
@@ -5475,6 +5475,25 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
        }
 
        blocks = fixed16_to_u32_round_up(selected_result) + 1;
+       /*
+        * Lets have blocks at minimum equivalent to plane_blocks_per_line
+        * as there will be at minimum one line for lines configuration. This
+        * is a work around for FIFO underruns observed with resolutions like
+        * 4k 60 Hz in single channel DRAM configurations.
+        *
+        * As per the Bspec 49325, if the ddb allocation can hold at least
+        * one plane_blocks_per_line, we should have selected method2 in
+        * the above logic. Assuming that modern versions have enough dbuf
+        * and method2 guarantees blocks equivalent to at least 1 line,
+        * select the blocks as plane_blocks_per_line.
+        *
+        * TODO: Revisit the logic when we have better understanding on DRAM
+        * channels' impact on the level 0 memory latency and the relevant
+        * wm calculations.
+        */
+       if (skl_wm_has_lines(dev_priv, level))
+               blocks = max(blocks,
+                            fixed16_to_u32_round_up(wp->plane_blocks_per_line));
        lines = div_round_up_fixed16(selected_result,
                                     wp->plane_blocks_per_line);