Merge tag 'drm-intel-gt-next-2023-08-04' of git://anongit.freedesktop.org/drm/drm...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4f94a0367cb968fdd1b06f799b49f5d86c8be664..aefad14ab27a42da906cfea782057e1452327c1d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -941,8 +941,30 @@
 #define HECI_H_GS1(base)       _MMIO((base) + 0xc4c)
 #define   HECI_H_GS1_ER_PREP   REG_BIT(0)
 
-#define HECI_FWSTS5(base)              _MMIO((base) + 0xc68)
-#define   HECI_FWSTS5_HUC_AUTH_DONE    (1 << 19)
+/*
+ * The FWSTS register values are FW defined and can be different between
+ * HECI1 and HECI2
+ */
+#define HECI_FWSTS1                            0xc40
+#define   HECI1_FWSTS1_CURRENT_STATE                   REG_GENMASK(3, 0)
+#define   HECI1_FWSTS1_CURRENT_STATE_RESET             0
+#define   HECI1_FWSTS1_PROXY_STATE_NORMAL              5
+#define   HECI1_FWSTS1_INIT_COMPLETE                   REG_BIT(9)
+#define HECI_FWSTS2                            0xc48
+#define HECI_FWSTS3                            0xc60
+#define HECI_FWSTS4                            0xc64
+#define HECI_FWSTS5                            0xc68
+#define   HECI1_FWSTS5_HUC_AUTH_DONE   (1 << 19)
+#define HECI_FWSTS6                            0xc6c
+
+/* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
+#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
+                                                   HECI_FWSTS1, \
+                                                   HECI_FWSTS2, \
+                                                   HECI_FWSTS3, \
+                                                   HECI_FWSTS4, \
+                                                   HECI_FWSTS5, \
+                                                   HECI_FWSTS6))
 
 #define HSW_GTT_CACHE_EN       _MMIO(0x4024)
 #define   GTT_CACHE_EN_ALL     0xF0007FFF