Merge drm/drm-next into drm-intel-gt-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_perf.c

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e27f3b7cf094e73ab51657f97481241751670c12..2e8028e826b5c1877decb79da6fe5bfa178c06c2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,8 +1630,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
        struct drm_i915_gem_object *bo;
        struct i915_vma *vma;
        const u64 delay_ticks = 0xffffffffffffffff -
-               intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt,
-                                             atomic64_read(&stream->perf->noa_programming_delay));
+               intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
+               atomic64_read(&stream->perf->noa_programming_delay));
        const u32 base = stream->engine->mmio_base;
 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
        u32 *batch, *ts0, *cs, *jump;
@@ -2114,7 +2114,7 @@ gen8_update_reg_state_unlocked(const struct intel_context *ce,
        u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
        u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
        /* The MMIO offsets for Flex EU registers aren't contiguous */
-       i915_reg_t flex_regs[] = {
+       static const i915_reg_t flex_regs[] = {
                EU_PERF_CNTL0,
                EU_PERF_CNTL1,
                EU_PERF_CNTL2,
@@ -3542,7 +3542,7 @@ err:
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-       return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt,
+       return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
                                             2ULL << exponent);
 }