Merge tag 'drm-intel-next-2022-07-06' of git://anongit.freedesktop.org/drm/drm-intel...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_pci.c

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 04346929d009d30ef077857d2643eb1e6bce8ad7..5edc8fbf1dff7c5ede694317b89f26134a378f2d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -174,6 +174,7 @@
        .display.overlay_needs_physical = 1, \
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
+       .has_3d_pipeline = 1, \
        .hws_needs_physical = 1, \
        .unfenced_needs_alignment = 1, \
        .platform_engine_mask = BIT(RCS0), \
@@ -193,6 +194,7 @@
        .display.has_overlay = 1, \
        .display.overlay_needs_physical = 1, \
        .display.has_gmch = 1, \
+       .has_3d_pipeline = 1, \
        .gpu_reset_clobbers_display = true, \
        .hws_needs_physical = 1, \
        .unfenced_needs_alignment = 1, \
@@ -235,6 +237,7 @@ static const struct intel_device_info i865g_info = {
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
        .platform_engine_mask = BIT(RCS0), \
+       .has_3d_pipeline = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        .dma_mask_size = 32, \
@@ -326,6 +329,7 @@ static const struct intel_device_info pnv_m_info = {
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
        .platform_engine_mask = BIT(RCS0), \
+       .has_3d_pipeline = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        .dma_mask_size = 36, \
@@ -377,6 +381,7 @@ static const struct intel_device_info gm45_info = {
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
        .display.has_hotplug = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
+       .has_3d_pipeline = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = true, \
        /* ilk does support rc6, but we do not implement [power] contexts */ \
@@ -408,6 +413,7 @@ static const struct intel_device_info ilk_m_info = {
        .display.has_hotplug = 1, \
        .display.fbc_mask = BIT(INTEL_FBC_A), \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+       .has_3d_pipeline = 1, \
        .has_coherent_ggtt = true, \
        .has_llc = 1, \
        .has_rc6 = 1, \
@@ -459,6 +465,7 @@ static const struct intel_device_info snb_m_gt2_info = {
        .display.has_hotplug = 1, \
        .display.fbc_mask = BIT(INTEL_FBC_A), \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
+       .has_3d_pipeline = 1, \
        .has_coherent_ggtt = true, \
        .has_llc = 1, \
        .has_rc6 = 1, \
@@ -695,6 +702,7 @@ static const struct intel_device_info skl_gt4_info = {
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
                BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
+       .has_3d_pipeline = 1, \
        .has_64bit_reloc = 1, \
        .display.has_ddi = 1, \
        .display.has_fpga_dbg = 1, \
@@ -904,7 +912,8 @@ static const struct intel_device_info rkl_info = {
        .has_llc = 0, \
        .has_pxp = 0, \
        .has_snoop = 1, \
-       .is_dgfx = 1
+       .is_dgfx = 1, \
+       .has_heci_gscfi = 1
 
 static const struct intel_device_info dg1_info = {
        GEN12_FEATURES,
@@ -1000,6 +1009,7 @@ static const struct intel_device_info adl_p_info = {
        .graphics.rel = 50, \
        XE_HP_PAGE_SIZES, \
        .dma_mask_size = 46, \
+       .has_3d_pipeline = 1, \
        .has_64bit_reloc = 1, \
        .has_flat_ccs = 1, \
        .has_global_mocs = 1, \
@@ -1007,7 +1017,7 @@ static const struct intel_device_info adl_p_info = {
        .has_llc = 1, \
        .has_logical_ring_contexts = 1, \
        .has_logical_ring_elsq = 1, \
-       .has_mslices = 1, \
+       .has_mslice_steering = 1, \
        .has_rc6 = 1, \
        .has_reset_engine = 1, \
        .has_rps = 1, \
@@ -1033,7 +1043,8 @@ static const struct intel_device_info xehpsdv_info = {
                BIT(RCS0) | BIT(BCS0) |
                BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
                BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
-               BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+               BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+               BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
        .require_force_probe = 1,
 };
 
@@ -1047,12 +1058,14 @@ static const struct intel_device_info xehpsdv_info = {
        .has_4tile = 1, \
        .has_64k_pages = 1, \
        .has_guc_deprivilege = 1, \
+       .has_heci_pxp = 1, \
        .needs_compact_pt = 1, \
        .has_media_ratio_mode = 1, \
        .platform_engine_mask = \
                BIT(RCS0) | BIT(BCS0) | \
                BIT(VECS0) | BIT(VECS1) | \
-               BIT(VCS0) | BIT(VCS2)
+               BIT(VCS0) | BIT(VCS2) | \
+               BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
 
 static const struct intel_device_info dg2_info = {
        DG2_FEATURES,
@@ -1069,6 +1082,32 @@ static const struct intel_device_info ats_m_info = {
        .require_force_probe = 1,
 };
 
+#define XE_HPC_FEATURES \
+       XE_HP_FEATURES, \
+       .dma_mask_size = 52, \
+       .has_3d_pipeline = 0, \
+       .has_guc_deprivilege = 1, \
+       .has_l3_ccs_read = 1, \
+       .has_mslice_steering = 0, \
+       .has_one_eu_per_fuse_bit = 1
+
+__maybe_unused
+static const struct intel_device_info pvc_info = {
+       XE_HPC_FEATURES,
+       XE_HPM_FEATURES,
+       DGFX_FEATURES,
+       .graphics.rel = 60,
+       .media.rel = 60,
+       PLATFORM(INTEL_PONTEVECCHIO),
+       .display = { 0 },
+       .has_flat_ccs = 0,
+       .platform_engine_mask =
+               BIT(BCS0) |
+               BIT(VCS0) |
+               BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
+       .require_force_probe = 1,
+};
+
 #undef PLATFORM
 
 /*