Merge tag 'drm-intel-next-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b63893eeca73ddf78070bbecf055f6560f8636b7..2fe92d2e0f6293cbcbf02df52d98d47b97bad6e3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -336,7 +336,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
        __gen6_mask_pm_irq(dev_priv, mask);
 }
 
-void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
+static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 {
        i915_reg_t reg = gen6_pm_iir(dev_priv);
 
@@ -347,7 +347,7 @@ void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
        POSTING_READ(reg);
 }
 
-void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
+static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 {
        lockdep_assert_held(&dev_priv->irq_lock);
 
@@ -357,7 +357,7 @@ void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
        /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 }
 
-void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
+static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 {
        lockdep_assert_held(&dev_priv->irq_lock);
 
@@ -405,7 +405,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
        synchronize_irq(dev_priv->drm.irq);
 
        /* Now that we will not be generating any more work, flush any
-        * outsanding tasks. As we are called on the RPS idle path,
+        * outstanding tasks. As we are called on the RPS idle path,
         * we will reset the GPU to minimum frequencies, so the current
         * state of the worker can be discarded.
         */