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Merge tag 'drm-intel-gt-next-2023-10-19' of git://anongit.freedesktop.org/drm/drm...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.h
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3737307bb12ad5823b2ebcf13d54e8e23c1c7d85..6a2a78c61f212c7c8178012ab6676015903e271a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -332,12 +332,6 @@ struct drm_i915_private {
 
        struct i915_hwmon *hwmon;
 
-       /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
-       struct intel_gt gt0;
-
-       /*
-        * i915->gt[0] == &i915->gt0
-        */
        struct intel_gt *gt[I915_MAX_GT];
 
        struct kobject *sysfs_gt;
@@ -397,9 +391,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
        return pci_get_drvdata(pdev);
 }
 
-static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
+static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
 {
-       return &i915->gt0;
+       return i915->gt[0];
 }
 
 /* Simple iterator over all initialised engines */
@@ -431,8 +425,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 
 #define INTEL_INFO(i915)       ((i915)->__info)
 #define RUNTIME_INFO(i915)     (&(i915)->__runtime)
-#define DISPLAY_INFO(i915)     ((i915)->display.info.__device_info)
-#define DISPLAY_RUNTIME_INFO(i915)     (&(i915)->display.info.__runtime_info)
 #define DRIVER_CAPS(i915)      (&(i915)->caps)
 
 #define INTEL_DEVID(i915)      (RUNTIME_INFO(i915)->device_id)
@@ -451,10 +443,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 #define IS_MEDIA_VER(i915, from, until) \
        (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 
-#define DISPLAY_VER(i915)      (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
-#define IS_DISPLAY_VER(i915, from, until) \
-       (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
-
 #define INTEL_REVID(i915)      (to_pci_dev((i915)->drm.dev)->revision)
 
 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
@@ -576,8 +564,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COFFEELAKE(i915)    IS_PLATFORM(i915, INTEL_COFFEELAKE)
 #define IS_COMETLAKE(i915)     IS_PLATFORM(i915, INTEL_COMETLAKE)
 #define IS_ICELAKE(i915)       IS_PLATFORM(i915, INTEL_ICELAKE)
-#define IS_JSL_EHL(i915)       (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
-                               IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
+#define IS_JASPERLAKE(i915)    IS_PLATFORM(i915, INTEL_JASPERLAKE)
+#define IS_ELKHARTLAKE(i915)   IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
 #define IS_TIGERLAKE(i915)     IS_PLATFORM(i915, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(i915)    IS_PLATFORM(i915, INTEL_ROCKETLAKE)
 #define IS_DG1(i915)        IS_PLATFORM(i915, INTEL_DG1)
@@ -594,117 +582,74 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
        IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(i915) \
        IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(i915) \
+#define IS_RAPTORLAKE_S(i915) \
        IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(i915) \
+#define IS_ALDERLAKE_P_N(i915) \
        IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_RAPTORLAKE_P(i915) \
        IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_RAPTORLAKE_U(i915) \
        IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
-#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
+#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
                                    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(i915) \
+#define IS_BROADWELL_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
-#define IS_BDW_ULX(i915) \
+#define IS_BROADWELL_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_BDW_GT3(i915)       (IS_BROADWELL(i915) && \
+#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
                                 INTEL_INFO(i915)->gt == 3)
-#define IS_HSW_ULT(i915) \
+#define IS_HASWELL_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
-#define IS_HSW_GT3(i915)       (IS_HASWELL(i915) && \
+#define IS_HASWELL_GT3(i915)   (IS_HASWELL(i915) && \
                                 INTEL_INFO(i915)->gt == 3)
-#define IS_HSW_GT1(i915)       (IS_HASWELL(i915) && \
+#define IS_HASWELL_GT1(i915)   (IS_HASWELL(i915) && \
                                 INTEL_INFO(i915)->gt == 1)
 /* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(i915) \
+#define IS_HASWELL_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(i915) \
+#define IS_KABYLAKE_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(i915) \
+#define IS_KABYLAKE_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915)       (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915)   (IS_SKYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915)       (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915)   (IS_SKYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915)       (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915)   (IS_SKYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 4)
-#define IS_KBL_GT2(i915)       (IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT2(i915)  (IS_KABYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 2)
-#define IS_KBL_GT3(i915)       (IS_KABYLAKE(i915) && \
+#define IS_KABYLAKE_GT3(i915)  (IS_KABYLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 3)
-#define IS_CFL_ULT(i915) \
+#define IS_COFFEELAKE_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CFL_ULX(i915) \
+#define IS_COFFEELAKE_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CFL_GT2(i915)       (IS_COFFEELAKE(i915) && \
+#define IS_COFFEELAKE_GT2(i915)        (IS_COFFEELAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 2)
-#define IS_CFL_GT3(i915)       (IS_COFFEELAKE(i915) && \
+#define IS_COFFEELAKE_GT3(i915)        (IS_COFFEELAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 3)
 
-#define IS_CML_ULT(i915) \
+#define IS_COMETLAKE_ULT(i915) \
        IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CML_ULX(i915) \
+#define IS_COMETLAKE_ULX(i915) \
        IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CML_GT2(i915)       (IS_COMETLAKE(i915) && \
+#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
                                 INTEL_INFO(i915)->gt == 2)
 
 #define IS_ICL_WITH_PORT_F(i915) \
        IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
        IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
-
-#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
-       (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
-#define IS_KBL_DISPLAY_STEP(i915, since, until) \
-       (IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
-
-#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
-       (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
-#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
-       (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
-
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
-       (IS_TIGERLAKE(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
-
-#define IS_RKL_DISPLAY_STEP(p, since, until) \
-       (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
-
-#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
-       (IS_ALDERLAKE_S(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
-
-#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
-       (IS_ALDERLAKE_S(__i915) && \
-        IS_GRAPHICS_STEP(__i915, since, until))
-
-#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
-       (IS_ALDERLAKE_P(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
-
-#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
-       (IS_ALDERLAKE_P(__i915) && \
-        IS_GRAPHICS_STEP(__i915, since, until))
-
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
        (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
-       (IS_METEORLAKE(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
-
-#define IS_DG2_DISPLAY_STEP(__i915, since, until) \
-       (IS_DG2(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
-
 #define IS_PVC_BD_STEP(__i915, since, until) \
        (IS_PONTEVECCHIO(__i915) && \
         IS_BASEDIE_STEP(__i915, since, until))
@@ -749,7 +694,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
 
 #define HAS_LLC(i915)  (INTEL_INFO(i915)->has_llc)
-#define HAS_4TILE(i915)        (INTEL_INFO(i915)->has_4tile)
 #define HAS_SNOOP(i915)        (INTEL_INFO(i915)->has_snoop)
 #define HAS_EDRAM(i915)        ((i915)->edram_size_mb)
 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
@@ -783,7 +727,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(i915)                       \
-       (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+       (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
@@ -844,15 +788,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
-#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
+#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
                                 2 : HAS_L3_DPF(i915))
 
-/* Only valid when HAS_DISPLAY() is true */
-#define INTEL_DISPLAY_ENABLED(i915) \
-       (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)),         \
-        !(i915)->params.disable_display &&                             \
-        !intel_opregion_headless_sku(i915))
-
 #define HAS_GUC_DEPRIVILEGE(i915) \
        (INTEL_INFO(i915)->has_guc_deprivilege)
 
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