Merge tag 'gvt-next-2017-06-08' of https://github.com/01org/gvt-linux into drm-intel...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / handlers.c

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6ec47598d758713b645a3c4e9ef8309955b36824..35a9bff6b0cff91fab12d448544192cc26c36286 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -47,21 +47,6 @@
 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
 #define PCH_PP_DIVISOR _MMIO(0xc7210)
 
-/* Register contains RO bits */
-#define F_RO           (1 << 0)
-/* Register contains graphics address */
-#define F_GMADR                (1 << 1)
-/* Mode mask registers with high 16 bits as the mask bits */
-#define F_MODE_MASK    (1 << 2)
-/* This reg can be accessed by GPU commands */
-#define F_CMD_ACCESS   (1 << 3)
-/* This reg has been accessed by a VM */
-#define F_ACCESSED     (1 << 4)
-/* This reg has been accessed through GPU commands */
-#define F_CMD_ACCESSED (1 << 5)
-/* This reg could be accessed by unaligned address */
-#define F_UNALIGN      (1 << 6)
-
 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
 {
        if (IS_BROADWELL(gvt->dev_priv))
@@ -139,6 +124,7 @@ static int new_mmio_info(struct intel_gvt *gvt,
                gvt->mmio.mmio_attribute[info->offset / 4] = flags;
                INIT_HLIST_NODE(&info->node);
                hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
+               gvt->mmio.num_tracked_mmio++;
        }
        return 0;
 }
@@ -312,6 +298,9 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 
        intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
 
+       /* sw will wait for the device to ack the reset request */
+        vgpu_vreg(vgpu, offset) = 0;
+
        return 0;
 }
 
@@ -1256,7 +1245,7 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
        mode = vgpu_vreg(vgpu, offset);
 
        if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
-               WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n",
+               WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
                                vgpu->id);
                return 0;
        }
@@ -2946,77 +2935,15 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
                if (ret)
                        goto err;
        }
+
+       gvt_dbg_mmio("traced %u virtual mmio registers\n",
+                    gvt->mmio.num_tracked_mmio);
        return 0;
 err:
        intel_gvt_clean_mmio_info(gvt);
        return ret;
 }
 
-/**
- * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
- * @gvt: a GVT device
- * @offset: register offset
- *
- */
-void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset)
-{
-       gvt->mmio.mmio_attribute[offset >> 2] |=
-               F_ACCESSED;
-}
-
-/**
- * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
- * @gvt: a GVT device
- * @offset: register offset
- *
- */
-bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt,
-               unsigned int offset)
-{
-       return gvt->mmio.mmio_attribute[offset >> 2] &
-               F_CMD_ACCESS;
-}
-
-/**
- * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
- * @gvt: a GVT device
- * @offset: register offset
- *
- */
-bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt,
-               unsigned int offset)
-{
-       return gvt->mmio.mmio_attribute[offset >> 2] &
-               F_UNALIGN;
-}
-
-/**
- * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
- * @gvt: a GVT device
- * @offset: register offset
- *
- */
-void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt,
-               unsigned int offset)
-{
-       gvt->mmio.mmio_attribute[offset >> 2] |=
-               F_CMD_ACCESSED;
-}
-
-/**
- * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
- * @gvt: a GVT device
- * @offset: register offset
- *
- * Returns:
- * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
- *
- */
-bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset)
-{
-       return gvt->mmio.mmio_attribute[offset >> 2] &
-               F_MODE_MASK;
-}
 
 /**
  * intel_vgpu_default_mmio_read - default MMIO read handler