Merge tag 'drm-intel-next-2019-04-04' into gvt-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 35b4ec3f7618b887e5661d0d652cca99b6ed02c6..57a92a86c63e2c8c20255cac9137b0d892cc1458 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -391,12 +391,12 @@ struct cmd_info {
 #define F_POST_HANDLE  (1<<2)
        u32 flag;
 
-#define R_RCS  (1 << RCS)
-#define R_VCS1  (1 << VCS)
-#define R_VCS2  (1 << VCS2)
+#define R_RCS  BIT(RCS0)
+#define R_VCS1  BIT(VCS0)
+#define R_VCS2  BIT(VCS1)
 #define R_VCS  (R_VCS1 | R_VCS2)
-#define R_BCS  (1 << BCS)
-#define R_VECS (1 << VECS)
+#define R_BCS  BIT(BCS0)
+#define R_VECS BIT(VECS0)
 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
        /* rings that support this cmd: BLT/RCS/VCS/VECS */
        u16 rings;
@@ -558,7 +558,7 @@ static const struct decode_info decode_info_vebox = {
 };
 
 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
-       [RCS] = {
+       [RCS0] = {
                &decode_info_mi,
                NULL,
                NULL,
@@ -569,7 +569,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
                NULL,
        },
 
-       [VCS] = {
+       [VCS0] = {
                &decode_info_mi,
                NULL,
                NULL,
@@ -580,7 +580,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
                NULL,
        },
 
-       [BCS] = {
+       [BCS0] = {
                &decode_info_mi,
                NULL,
                &decode_info_2d,
@@ -591,7 +591,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
                NULL,
        },
 
-       [VECS] = {
+       [VECS0] = {
                &decode_info_mi,
                NULL,
                NULL,
@@ -602,7 +602,7 @@ static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
                NULL,
        },
 
-       [VCS2] = {
+       [VCS1] = {
                &decode_info_mi,
                NULL,
                NULL,
@@ -631,8 +631,7 @@ static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
        struct cmd_entry *e;
 
        hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
-               if ((opcode == e->info->opcode) &&
-                               (e->info->rings & (1 << ring_id)))
+               if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))
                        return e->info;
        }
        return NULL;
@@ -943,15 +942,12 @@ static int cmd_handler_lri(struct parser_exec_state *s)
        struct intel_gvt *gvt = s->vgpu->gvt;
 
        for (i = 1; i < cmd_len; i += 2) {
-               if (IS_BROADWELL(gvt->dev_priv) &&
-                               (s->ring_id != RCS)) {
-                       if (s->ring_id == BCS &&
-                                       cmd_reg(s, i) ==
-                                       i915_mmio_reg_offset(DERRMR))
+               if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {
+                       if (s->ring_id == BCS0 &&
+                           cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
                                ret |= 0;
                        else
-                               ret |= (cmd_reg_inhibit(s, i)) ?
-                                       -EBADRQC : 0;
+                               ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
                }
                if (ret)
                        break;
@@ -1047,27 +1043,27 @@ struct cmd_interrupt_event {
 };
 
 static struct cmd_interrupt_event cmd_interrupt_events[] = {
-       [RCS] = {
+       [RCS0] = {
                .pipe_control_notify = RCS_PIPE_CONTROL,
                .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
                .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
        },
-       [BCS] = {
+       [BCS0] = {
                .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
                .mi_flush_dw = BCS_MI_FLUSH_DW,
                .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
        },
-       [VCS] = {
+       [VCS0] = {
                .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
                .mi_flush_dw = VCS_MI_FLUSH_DW,
                .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
        },
-       [VCS2] = {
+       [VCS1] = {
                .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
                .mi_flush_dw = VCS2_MI_FLUSH_DW,
                .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
        },
-       [VECS] = {
+       [VECS0] = {
                .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
                .mi_flush_dw = VECS_MI_FLUSH_DW,
                .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
@@ -1321,8 +1317,14 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
                              info->tile_val << 10);
        }
 
-       vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
-       intel_vgpu_trigger_virtual_event(vgpu, info->event);
+       if (info->plane == PLANE_PRIMARY)
+               vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
+
+       if (info->async_flip)
+               intel_vgpu_trigger_virtual_event(vgpu, info->event);
+       else
+               set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
+
        return 0;
 }