/* Preliminary initialization of Tile 0 */
int intel_root_gt_init_early(struct drm_i915_private *i915)
{
- struct intel_gt *gt = to_gt(i915);
+ struct intel_gt *gt;
+
+ gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt)
+ return -ENOMEM;
+
+ i915->gt[0] = gt;
gt->i915 = i915;
gt->uncore = &i915->uncore;
if (IS_HASWELL(i915))
intel_uncore_write(uncore,
HSW_MI_PREDICATE_RESULT_2,
- IS_HSW_GT3(i915) ?
+ IS_HASWELL_GT3(i915) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
/* Apply the GT workarounds... */
if (ret)
return ret;
- i915->gt[0] = gt;
-
if (!HAS_EXTRA_GT_LIST(i915))
return 0;