Merge drm/drm-next into drm-intel-gt-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gt / intel_gt.c

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 767e329e1cc5fd4eed40fd8cc6b969d5c4978cce..7eeee5a7cb33cb9527cd98ac46e8611180b878aa 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -8,7 +8,6 @@
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_lmem.h"
-#include "pxp/intel_pxp.h"
 
 #include "i915_drv.h"
 #include "i915_perf_oa_regs.h"
@@ -110,9 +109,18 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
 
 int intel_gt_assign_ggtt(struct intel_gt *gt)
 {
-       gt->ggtt = drmm_kzalloc(&gt->i915->drm, sizeof(*gt->ggtt), GFP_KERNEL);
+       /* Media GT shares primary GT's GGTT */
+       if (gt->type == GT_MEDIA) {
+               gt->ggtt = to_gt(gt->i915)->ggtt;
+       } else {
+               gt->ggtt = i915_ggtt_create(gt->i915);
+               if (IS_ERR(gt->ggtt))
+                       return PTR_ERR(gt->ggtt);
+       }
+
+       list_add_tail(&gt->ggtt_link, &gt->ggtt->gt_list);
 
-       return gt->ggtt ? 0 : -ENOMEM;
+       return 0;
 }
 
 int intel_gt_init_mmio(struct intel_gt *gt)
@@ -210,21 +218,6 @@ out:
        return ret;
 }
 
-static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
-{
-       intel_uncore_rmw(uncore, reg, 0, set);
-}
-
-static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
-{
-       intel_uncore_rmw(uncore, reg, clr, 0);
-}
-
-static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
-{
-       intel_uncore_rmw(uncore, reg, 0, 0);
-}
-
 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 {
        GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
@@ -250,14 +243,14 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
        u32 eir;
 
        if (GRAPHICS_VER(i915) != 2)
-               clear_register(uncore, PGTBL_ER);
+               intel_uncore_write(uncore, PGTBL_ER, 0);
 
        if (GRAPHICS_VER(i915) < 4)
-               clear_register(uncore, IPEIR(RENDER_RING_BASE));
+               intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0);
        else
-               clear_register(uncore, IPEIR_I965);
+               intel_uncore_write(uncore, IPEIR_I965, 0);
 
-       clear_register(uncore, EIR);
+       intel_uncore_write(uncore, EIR, 0);
        eir = intel_uncore_read(uncore, EIR);
        if (eir) {
                /*
@@ -265,7 +258,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
                 * mask them.
                 */
                drm_dbg(&gt->i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
-               rmw_set(uncore, EMR, eir);
+               intel_uncore_rmw(uncore, EMR, 0, eir);
                intel_uncore_write(uncore, GEN2_IIR,
                                   I915_MASTER_ERROR_INTERRUPT);
        }
@@ -275,10 +268,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
                                           RING_FAULT_VALID, 0);
                intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
        } else if (GRAPHICS_VER(i915) >= 12) {
-               rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
+               intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID, 0);
                intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
        } else if (GRAPHICS_VER(i915) >= 8) {
-               rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
+               intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID, 0);
                intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
        } else if (GRAPHICS_VER(i915) >= 6) {
                struct intel_engine_cs *engine;
@@ -753,8 +746,6 @@ int intel_gt_init(struct intel_gt *gt)
 
        intel_migrate_init(&gt->migrate, gt);
 
-       intel_pxp_init(&gt->pxp);
-
        goto out_fw;
 err_gt:
        __intel_gt_disable(gt);
@@ -794,8 +785,6 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
        intel_rps_driver_unregister(&gt->rps);
        intel_gsc_fini(&gt->gsc);
 
-       intel_pxp_fini(&gt->pxp);
-
        /*
         * Upon unregistering the device to prevent any new users, cancel
         * all in-flight requests so that we can quickly unbind the active
@@ -1079,6 +1068,7 @@ static void mmio_invalidate_full(struct intel_gt *gt)
        enum intel_engine_id id;
        const i915_reg_t *regs;
        unsigned int num = 0;
+       unsigned long flags;
 
        if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
                regs = NULL;
@@ -1099,7 +1089,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
 
        intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 
-       spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */
+       intel_gt_mcr_lock(gt, &flags);
+       spin_lock(&uncore->lock); /* serialise invalidate with GT reset */
 
        awake = 0;
        for_each_engine(engine, gt, id) {
@@ -1109,9 +1100,15 @@ static void mmio_invalidate_full(struct intel_gt *gt)
                        continue;
 
                if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+                       u32 val = BIT(engine->instance);
+
+                       if (engine->class == VIDEO_DECODE_CLASS ||
+                           engine->class == VIDEO_ENHANCEMENT_CLASS ||
+                           engine->class == COMPUTE_CLASS)
+                               val = _MASKED_BIT_ENABLE(val);
                        intel_gt_mcr_multicast_write_fw(gt,
                                                        xehp_regs[engine->class],
-                                                       BIT(engine->instance));
+                                                       val);
                } else {
                        rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
                        if (!i915_mmio_reg_offset(rb.reg))
@@ -1138,7 +1135,8 @@ static void mmio_invalidate_full(struct intel_gt *gt)
             IS_ALDERLAKE_P(i915)))
                intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
 
-       spin_unlock_irq(&uncore->lock);
+       spin_unlock(&uncore->lock);
+       intel_gt_mcr_unlock(gt, flags);
 
        for_each_engine_masked(engine, gt, awake, tmp) {
                struct reg_and_bit rb;