Merge drm/drm-next into drm-misc-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / bridge / synopsys / dw-hdmi.c

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 521d689413c8c4b979794b11a7a0a6e2468037d6..d77fb8af61b8a82f78e7d2602b10300c2591ddef 100644 (file)
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -26,6 +26,7 @@
 
 #include <drm/bridge/dw_hdmi.h>
 #include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
 #include <drm/drm_edid.h>
 #include <drm/drm_of.h>
 #include <drm/drm_print.h>
@@ -580,6 +581,26 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
        return n;
 }
 
+/*
+ * When transmitting IEC60958 linear PCM audio, these registers allow to
+ * configure the channel status information of all the channel status
+ * bits in the IEC60958 frame. For the moment this configuration is only
+ * used when the I2S audio interface, General Purpose Audio (GPA),
+ * or AHB audio DMA (AHBAUDDMA) interface is active
+ * (for S/PDIF interface this information comes from the stream).
+ */
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
+                               u8 *channel_status)
+{
+       /*
+        * Set channel status register for frequency and word length.
+        * Use default values for other registers.
+        */
+       hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
+       hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
+
 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
        unsigned long pixel_clk, unsigned int sample_rate)
 {