Merge tag 'amd-drm-next-5.20-2022-07-14' of https://gitlab.freedesktop.org/agd5f...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / smu_v11_0.c

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 5f8809f6990dd12a323fbedc3f810848f5ea9bb9..dccbd9f707238922da482404622241aa09926f4a 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1228,6 +1228,8 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
        uint32_t crystal_clock_freq = 2500;
        uint32_t tach_period;
 
+       if (speed == 0)
+               return -EINVAL;
        /*
         * To prevent from possible overheat, some ASICs may have requirement
         * for minimum fan speed:
@@ -2197,3 +2199,12 @@ int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
 
        return ret;
 }
+
+void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+
+       smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+       smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+       smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}