Merge drm/drm-next into drm-misc-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / dce_v6_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 86e95b1c9d0e79aa8617890695e2d5b73a602a50..7f85ba5b726f6860e2ae80506b231145b196e5c0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2716,7 +2716,7 @@ static int dce_v6_0_sw_init(void *handle)
                return r;
 
        /* Pre-DCE11 */
-       INIT_WORK(&adev->hotplug_work,
+       INIT_DELAYED_WORK(&adev->hotplug_work,
                  amdgpu_display_hotplug_work_func);
 
        drm_kms_helper_poll_init(adev_to_drm(adev));
@@ -2777,7 +2777,7 @@ static int dce_v6_0_hw_fini(void *handle)
 
        dce_v6_0_pageflip_interrupt_fini(adev);
 
-       flush_work(&adev->hotplug_work);
+       flush_delayed_work(&adev->hotplug_work);
 
        return 0;
 }
@@ -3104,7 +3104,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
                tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
                tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
                WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
-               schedule_work(&adev->hotplug_work);
+               schedule_delayed_work(&adev->hotplug_work, 0);
                DRM_DEBUG("IH: HPD%d\n", hpd + 1);
        }