Merge branch 'x86/cpu' into perf/core, to pick up revert

[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / common.c

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 0948fc25446ab3fa3ae02684bfb4d5d31a2da81e..482f74859fb7760266813b5ba7fc260be12a8a96 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -366,22 +366,6 @@ out:
        cr4_clear_bits(X86_CR4_UMIP);
 }
 
-static __init int x86_nofsgsbase_setup(char *arg)
-{
-       /* Require an exact match without trailing characters. */
-       if (strlen(arg))
-               return 0;
-
-       /* Do not emit a message if the feature is not present. */
-       if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
-               return 1;
-
-       setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
-       pr_info("FSGSBASE disabled via kernel command line\n");
-       return 1;
-}
-__setup("nofsgsbase", x86_nofsgsbase_setup);
-
 /*
  * Protection Keys are not available in 32-bit mode.
  */
@@ -1387,12 +1371,6 @@ static void identify_cpu(struct cpuinfo_x86 *c)
        setup_smap(c);
        setup_umip(c);
 
-       /* Enable FSGSBASE instructions if available. */
-       if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
-               cr4_set_bits(X86_CR4_FSGSBASE);
-               elf_hwcap2 |= HWCAP2_FSGSBASE;
-       }
-
        /*
         * The vendor-specific functions might have changed features.
         * Now we do "generic changes."