Merge tag 'v5.3-rc6' into x86/cpu, to pick up fixes

[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / amd.c

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 68c363c341bf2a3794ec26f29df4dd28281d4dc5..29f0cdfbdca5d5036a6ed1c9c9019e9408efe306 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -945,12 +945,8 @@ static void init_amd(struct cpuinfo_x86 *c)
        init_amd_cacheinfo(c);
 
        if (cpu_has(c, X86_FEATURE_XMM2)) {
-               unsigned long long val;
-               int ret;
-
                /*
-                * A serializing LFENCE has less overhead than MFENCE, so
-                * use it for execution serialization.  On families which
+                * Use LFENCE for execution serialization.  On families which
                 * don't have that MSR, LFENCE is already serializing.
                 * msr_set_bit() uses the safe accessors, too, even if the MSR
                 * is not present.
@@ -958,19 +954,8 @@ static void init_amd(struct cpuinfo_x86 *c)
                msr_set_bit(MSR_F10H_DECFG,
                            MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
 
-               /*
-                * Verify that the MSR write was successful (could be running
-                * under a hypervisor) and only then assume that LFENCE is
-                * serializing.
-                */
-               ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
-               if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
-                       /* A serializing LFENCE stops RDTSC speculation */
-                       set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
-               } else {
-                       /* MFENCE stops RDTSC speculation */
-                       set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
-               }
+               /* A serializing LFENCE stops RDTSC speculation */
+               set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
        }
 
        /*