Merge patch "RISC-V: Add ptrace support for vectors"

[sfrench/cifs-2.6.git] / arch / riscv / include / uapi / asm / ptrace.h

diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h
index 283800130614ba4bc98900231641869b376ab059..a38268b19c3d3d5b3e837634e05a7774fc4287d4 100644 (file)
--- a/arch/riscv/include/uapi/asm/ptrace.h
+++ b/arch/riscv/include/uapi/asm/ptrace.h
@@ -10,6 +10,11 @@
 
 #include <linux/types.h>
 
+#define PTRACE_GETFDPIC                33
+
+#define PTRACE_GETFDPIC_EXEC   0
+#define PTRACE_GETFDPIC_INTERP 1
+
 /*
  * User-mode register state for core dumps, ptrace, sigcontext
  *
@@ -103,13 +108,18 @@ struct __riscv_v_ext_state {
         * In signal handler, datap will be set a correct user stack offset
         * and vector registers will be copied to the address of datap
         * pointer.
-        *
-        * In ptrace syscall, datap will be set to zero and the vector
-        * registers will be copied to the address right after this
-        * structure.
         */
 };
 
+struct __riscv_v_regset_state {
+       unsigned long vstart;
+       unsigned long vl;
+       unsigned long vtype;
+       unsigned long vcsr;
+       unsigned long vlenb;
+       char vreg[];
+};
+
 /*
  * According to spec: The number of bits in a single vector register,
  * VLEN >= ELEN, which must be a power of 2, and must be no greater than