Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[sfrench/cifs-2.6.git] / arch / riscv / include / uapi / asm / kvm.h

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 855c047e86d49664e6518842188fa17986213807..930fdc4101cdab8eddbd31e2ff33fb27f17bc998 100644 (file)
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -15,6 +15,7 @@
 #include <asm/bitsperlong.h>
 #include <asm/ptrace.h>
 
+#define __KVM_HAVE_IRQ_LINE
 #define __KVM_HAVE_READONLY_MEM
 
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
@@ -122,6 +123,7 @@ enum KVM_RISCV_ISA_EXT_ID {
        KVM_RISCV_ISA_EXT_ZBB,
        KVM_RISCV_ISA_EXT_SSAIA,
        KVM_RISCV_ISA_EXT_V,
+       KVM_RISCV_ISA_EXT_SVNAPOT,
        KVM_RISCV_ISA_EXT_MAX,
 };
 
@@ -211,6 +213,77 @@ enum KVM_RISCV_SBI_EXT_ID {
 #define KVM_REG_RISCV_VECTOR_REG(n)    \
                ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
 
+/* Device Control API: RISC-V AIA */
+#define KVM_DEV_RISCV_APLIC_ALIGN              0x1000
+#define KVM_DEV_RISCV_APLIC_SIZE               0x4000
+#define KVM_DEV_RISCV_APLIC_MAX_HARTS          0x4000
+#define KVM_DEV_RISCV_IMSIC_ALIGN              0x1000
+#define KVM_DEV_RISCV_IMSIC_SIZE               0x1000
+
+#define KVM_DEV_RISCV_AIA_GRP_CONFIG           0
+#define KVM_DEV_RISCV_AIA_CONFIG_MODE          0
+#define KVM_DEV_RISCV_AIA_CONFIG_IDS           1
+#define KVM_DEV_RISCV_AIA_CONFIG_SRCS          2
+#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS    3
+#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT   4
+#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS     5
+#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS    6
+
+/*
+ * Modes of RISC-V AIA device:
+ * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
+ * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
+ * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
+ *    available otherwise fallback to trap-n-emulation
+ */
+#define KVM_DEV_RISCV_AIA_MODE_EMUL            0
+#define KVM_DEV_RISCV_AIA_MODE_HWACCEL         1
+#define KVM_DEV_RISCV_AIA_MODE_AUTO            2
+
+#define KVM_DEV_RISCV_AIA_IDS_MIN              63
+#define KVM_DEV_RISCV_AIA_IDS_MAX              2048
+#define KVM_DEV_RISCV_AIA_SRCS_MAX             1024
+#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX       8
+#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN      24
+#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX      56
+#define KVM_DEV_RISCV_AIA_HART_BITS_MAX                16
+#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX       8
+
+#define KVM_DEV_RISCV_AIA_GRP_ADDR             1
+#define KVM_DEV_RISCV_AIA_ADDR_APLIC           0
+#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu)   (1 + (__vcpu))
+#define KVM_DEV_RISCV_AIA_ADDR_MAX             \
+               (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
+
+#define KVM_DEV_RISCV_AIA_GRP_CTRL             2
+#define KVM_DEV_RISCV_AIA_CTRL_INIT            0
+
+/*
+ * The device attribute type contains the memory mapped offset of the
+ * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
+ */
+#define KVM_DEV_RISCV_AIA_GRP_APLIC            3
+
+/*
+ * The lower 12-bits of the device attribute type contains the iselect
+ * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
+ * bits contains the VCPU id.
+ */
+#define KVM_DEV_RISCV_AIA_GRP_IMSIC            4
+#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS      12
+#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK      \
+               ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
+#define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \
+               (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
+                ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
+#define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr)       \
+               ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
+#define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr)       \
+               ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
+
+/* One single KVM irqchip, ie. the AIA */
+#define KVM_NR_IRQCHIPS                        1
+
 #endif
 
 #endif /* __LINUX_KVM_RISCV_H */