powerpc/64s: avoid reloading (H)SRR registers if they are still valid

[sfrench/cifs-2.6.git] / arch / powerpc / kernel / vector.S

diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index 54dbefcb4cde5e1e9028fddceaf249cf38f1f6d8..fc120fac19104a78d0ba2a6238946cc3612dc957 100644 (file)
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -73,6 +73,10 @@ _GLOBAL(load_up_altivec)
        addi    r5,r4,THREAD            /* Get THREAD */
        oris    r12,r12,MSR_VEC@h
        std     r12,_MSR(r1)
+#ifdef CONFIG_PPC_BOOK3S_64
+       li      r4,0
+       stb     r4,PACASRR_VALID(r13)
+#endif
 #endif
        li      r4,1
        stb     r4,THREAD_LOAD_VEC(r5)
@@ -131,6 +135,8 @@ _GLOBAL(load_up_vsx)
        /* enable use of VSX after return */
        oris    r12,r12,MSR_VSX@h
        std     r12,_MSR(r1)
+       li      r4,0
+       stb     r4,PACASRR_VALID(r13)
        b       fast_interrupt_return_srr
 
 #endif /* CONFIG_VSX */