Merge tag 'mips_6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

[sfrench/cifs-2.6.git] / arch / mips / mm / c-r4k.c

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index b45bf026ee55e662f328ca4dc162b1365afd3563..10413b6f6662bcf99433725cf4c037a91308b155 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1650,7 +1650,7 @@ static void coherency_setup(void)
 
        /*
         * c0_status.cu=0 specifies that updates by the sc instruction use
-        * the coherency mode specified by the TLB; 1 means cachable
+        * the coherency mode specified by the TLB; 1 means cacheable
         * coherent update on write will be used.  Not all processors have
         * this bit and; some wire it to zero, others like Toshiba had the
         * silly idea of putting something else there ...