#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
CPU0: cpu@0 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
CPU1: cpu@100 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
CPU2: cpu@200 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
CPU3: cpu@300 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
CPU4: cpu@400 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a78";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
CPU5: cpu@500 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a78";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
CPU6: cpu@600 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a78";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
CPU7: cpu@700 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-x1";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 2>;
enable-method = "psci";
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
- entry-latency-us = <355>;
- exit-latency-us = <909>;
+ entry-latency-us = <360>;
+ exit-latency-us = <531>;
min-residency-us = <3934>;
local-timer-stop;
};
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
- entry-latency-us = <241>;
- exit-latency-us = <1461>;
+ entry-latency-us = <702>;
+ exit-latency-us = <1061>;
min-residency-us = <4488>;
local-timer-stop;
};
};
domain-idle-states {
- CLUSTER_SLEEP_0: cluster-sleep-0 {
+ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <2752>;
+ exit-latency-us = <3048>;
+ min-residency-us = <6118>;
+ };
+
+ CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <3263>;
CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
- domain-idle-states = <&CLUSTER_SLEEP_0>;
+ domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
};
};
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart18_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default_state>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
#hwlock-cells = <1>;
};
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm8350-lpass-lpi-pinctrl";
+ reg = <0 0x033c0000 0 0x20000>,
+ <0 0x03550000 0 0x10000>;
+
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+ };
+
gpu: gpu@3d00000 {
compatible = "qcom,adreno-660.1", "qcom,adreno";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8350_CX>,
- <&rpmhpd SM8350_MSS>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MSS>;
power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8350_LCX>,
- <&rpmhpd SM8350_LMX>;
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
iommus = <&apps_smmu 0x4a0 0x0>;
- power-domains = <&rpmhpd SM8350_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
dma-coherent;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&dpu_opp_table>;
- power-domains = <&rpmhpd SM8350_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
#sound-dai-cells = <0>;
operating-points-v2 = <&dp_opp_table>;
- power-domains = <&rpmhpd SM8350_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
status = "disabled";
<&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi0_opp_table>;
- power-domains = <&rpmhpd SM8350_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi0_phy>;
<&mdss_dsi1_phy 1>;
operating-points-v2 = <&dsi1_opp_table>;
- power-domains = <&rpmhpd SM8350_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi1_phy>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- power-domains = <&rpmhpd SM8350_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
};
pdc: interrupt-controller@b220000 {
reg = <0 0x15000000 0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
};
adsp: remoteproc@17300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8350_LCX>,
- <&rpmhpd SM8350_LMX>;
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
label = "lpass";
qcom,remote-pid = <2>;
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ service@3 {
+ reg = <APR_SVC_ADSP_CORE>;
+ compatible = "qcom,q6core";
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ q6afecc: clock-controller {
+ compatible = "qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu 0x1801 0x0>;
+
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
<0 0x18593000 0 0x1000>;
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1",
+ "dcvsh-irq-2";
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8350_CX>,
- <&rpmhpd SM8350_MXC>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>;
power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
git.samba.org / sfrench / cifs-2.6.git / blobdiff