ARM: vexpress: Add config bus components and clocks to DTs

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / vexpress-v2p-ca5s.dts

diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 18917a0f86047a3a444919badb09fb47da244bc4..f3c1f2a440727f631deae98111bbf86c6a545221 100644 (file)
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -12,6 +12,7 @@
 / {
        model = "V2P-CA5s";
        arm,hbi = <0x225>;
+       arm,vexpress,site = <0xf>;
        compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
        interrupt-parent = <&gic>;
        #address-cells = <1>;
@@ -56,11 +57,15 @@
                compatible = "arm,hdlcd";
                reg = <0x2a110000 0x1000>;
                interrupts = <0 85 4>;
+               clocks = <&oscclk3>;
+               clock-names = "pxlclk";
        };
 
        memory-controller@2a150000 {
                compatible = "arm,pl341", "arm,primecell";
                reg = <0x2a150000 0x1000>;
+               clocks = <&oscclk1>;
+               clock-names = "apb_pclk";
        };
 
        memory-controller@2a190000 {
@@ -68,6 +73,8 @@
                reg = <0x2a190000 0x1000>;
                interrupts = <0 86 4>,
                             <0 87 4>;
+               clocks = <&oscclk1>;
+               clock-names = "apb_pclk";
        };
 
        scu@2c000000 {
@@ -109,6 +116,72 @@
                             <0 69 4>;
        };
 
+       dcc {
+               compatible = "arm,vexpress,config-bus";
+               arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+               osc@0 {
+                       /* CPU and internal AXI reference clock */
+                       compatible = "arm,vexpress-osc";
+                       arm,vexpress-sysreg,func = <1 0>;
+                       freq-range = <50000000 100000000>;
+                       #clock-cells = <0>;
+                       clock-output-names = "oscclk0";
+               };
+
+               oscclk1: osc@1 {
+                       /* Multiplexed AXI master clock */
+                       compatible = "arm,vexpress-osc";
+                       arm,vexpress-sysreg,func = <1 1>;
+                       freq-range = <5000000 50000000>;
+                       #clock-cells = <0>;
+                       clock-output-names = "oscclk1";
+               };
+
+               osc@2 {
+                       /* DDR2 */
+                       compatible = "arm,vexpress-osc";
+                       arm,vexpress-sysreg,func = <1 2>;
+                       freq-range = <80000000 120000000>;
+                       #clock-cells = <0>;
+                       clock-output-names = "oscclk2";
+               };
+
+               oscclk3: osc@3 {
+                       /* HDLCD */
+                       compatible = "arm,vexpress-osc";
+                       arm,vexpress-sysreg,func = <1 3>;
+                       freq-range = <23750000 165000000>;
+                       #clock-cells = <0>;
+                       clock-output-names = "oscclk3";
+               };
+
+               osc@4 {
+                       /* Test chip gate configuration */
+                       compatible = "arm,vexpress-osc";
+                       arm,vexpress-sysreg,func = <1 4>;
+                       freq-range = <80000000 80000000>;
+                       #clock-cells = <0>;
+                       clock-output-names = "oscclk4";
+               };
+
+               smbclk: osc@5 {
+                       /* SMB clock */
+                       compatible = "arm,vexpress-osc";
+                       arm,vexpress-sysreg,func = <1 5>;
+                       freq-range = <25000000 60000000>;
+                       #clock-cells = <0>;
+                       clock-output-names = "oscclk5";
+               };
+
+               temp@0 {
+                       /* DCC internal operating temperature */
+                       compatible = "arm,vexpress-temp";
+                       arm,vexpress-sysreg,func = <4 0>;
+                       label = "DCC";
+               };
+       };
+
        motherboard {
                ranges = <0 0 0x08000000 0x04000000>,
                         <1 0 0x14000000 0x04000000>,