sound/soc/mediatek/mt8173/mt8173-afe-pcm.c

   1 /*
   2  * Mediatek 8173 ALSA SoC AFE platform driver
   3  *
   4  * Copyright (c) 2015 MediaTek Inc.
   5  * Author: Koro Chen <koro.chen@mediatek.com>
   6  *             Sascha Hauer <s.hauer@pengutronix.de>
   7  *             Hidalgo Huang <hidalgo.huang@mediatek.com>
   8  *             Ir Lian <ir.lian@mediatek.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 and
  12  * only version 2 as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/pm_runtime.h>
  26 #include <sound/soc.h>
  27 #include "mt8173-afe-common.h"
  28 #include "../common/mtk-base-afe.h"
  29 #include "../common/mtk-afe-platform-driver.h"
  30 #include "../common/mtk-afe-fe-dai.h"
  31
  32 /*****************************************************************************
  33  *                  R E G I S T E R       D E F I N I T I O N
  34  *****************************************************************************/
  35 #define AUDIO_TOP_CON0          0x0000
  36 #define AUDIO_TOP_CON1          0x0004
  37 #define AFE_DAC_CON0            0x0010
  38 #define AFE_DAC_CON1            0x0014
  39 #define AFE_I2S_CON1            0x0034
  40 #define AFE_I2S_CON2            0x0038
  41 #define AFE_CONN_24BIT          0x006c
  42 #define AFE_MEMIF_MSB           0x00cc
  43
  44 #define AFE_CONN1               0x0024
  45 #define AFE_CONN2               0x0028
  46 #define AFE_CONN3               0x002c
  47 #define AFE_CONN7               0x0460
  48 #define AFE_CONN8               0x0464
  49 #define AFE_HDMI_CONN0          0x0390
  50
  51 /* Memory interface */
  52 #define AFE_DL1_BASE            0x0040
  53 #define AFE_DL1_CUR             0x0044
  54 #define AFE_DL1_END             0x0048
  55 #define AFE_DL2_BASE            0x0050
  56 #define AFE_DL2_CUR             0x0054
  57 #define AFE_AWB_BASE            0x0070
  58 #define AFE_AWB_CUR             0x007c
  59 #define AFE_VUL_BASE            0x0080
  60 #define AFE_VUL_CUR             0x008c
  61 #define AFE_VUL_END             0x0088
  62 #define AFE_DAI_BASE            0x0090
  63 #define AFE_DAI_CUR             0x009c
  64 #define AFE_MOD_PCM_BASE        0x0330
  65 #define AFE_MOD_PCM_CUR         0x033c
  66 #define AFE_HDMI_OUT_BASE       0x0374
  67 #define AFE_HDMI_OUT_CUR        0x0378
  68 #define AFE_HDMI_OUT_END        0x037c
  69
  70 #define AFE_ADDA_TOP_CON0       0x0120
  71 #define AFE_ADDA2_TOP_CON0      0x0600
  72
  73 #define AFE_HDMI_OUT_CON0       0x0370
  74
  75 #define AFE_IRQ_MCU_CON         0x03a0
  76 #define AFE_IRQ_STATUS          0x03a4
  77 #define AFE_IRQ_CLR             0x03a8
  78 #define AFE_IRQ_CNT1            0x03ac
  79 #define AFE_IRQ_CNT2            0x03b0
  80 #define AFE_IRQ_MCU_EN          0x03b4
  81 #define AFE_IRQ_CNT5            0x03bc
  82 #define AFE_IRQ_CNT7            0x03dc
  83
  84 #define AFE_TDM_CON1            0x0548
  85 #define AFE_TDM_CON2            0x054c
  86
  87 #define AFE_IRQ_STATUS_BITS     0xff
  88
  89 /* AUDIO_TOP_CON0 (0x0000) */
  90 #define AUD_TCON0_PDN_SPDF              (0x1 << 21)
  91 #define AUD_TCON0_PDN_HDMI              (0x1 << 20)
  92 #define AUD_TCON0_PDN_24M               (0x1 << 9)
  93 #define AUD_TCON0_PDN_22M               (0x1 << 8)
  94 #define AUD_TCON0_PDN_AFE               (0x1 << 2)
  95
  96 /* AFE_I2S_CON1 (0x0034) */
  97 #define AFE_I2S_CON1_LOW_JITTER_CLK     (0x1 << 12)
  98 #define AFE_I2S_CON1_RATE(x)            (((x) & 0xf) << 8)
  99 #define AFE_I2S_CON1_FORMAT_I2S         (0x1 << 3)
 100 #define AFE_I2S_CON1_EN                 (0x1 << 0)
 101
 102 /* AFE_I2S_CON2 (0x0038) */
 103 #define AFE_I2S_CON2_LOW_JITTER_CLK     (0x1 << 12)
 104 #define AFE_I2S_CON2_RATE(x)            (((x) & 0xf) << 8)
 105 #define AFE_I2S_CON2_FORMAT_I2S         (0x1 << 3)
 106 #define AFE_I2S_CON2_EN                 (0x1 << 0)
 107
 108 /* AFE_CONN_24BIT (0x006c) */
 109 #define AFE_CONN_24BIT_O04              (0x1 << 4)
 110 #define AFE_CONN_24BIT_O03              (0x1 << 3)
 111
 112 /* AFE_HDMI_CONN0 (0x0390) */
 113 #define AFE_HDMI_CONN0_O37_I37          (0x7 << 21)
 114 #define AFE_HDMI_CONN0_O36_I36          (0x6 << 18)
 115 #define AFE_HDMI_CONN0_O35_I33          (0x3 << 15)
 116 #define AFE_HDMI_CONN0_O34_I32          (0x2 << 12)
 117 #define AFE_HDMI_CONN0_O33_I35          (0x5 << 9)
 118 #define AFE_HDMI_CONN0_O32_I34          (0x4 << 6)
 119 #define AFE_HDMI_CONN0_O31_I31          (0x1 << 3)
 120 #define AFE_HDMI_CONN0_O30_I30          (0x0 << 0)
 121
 122 /* AFE_TDM_CON1 (0x0548) */
 123 #define AFE_TDM_CON1_LRCK_WIDTH(x)      (((x) - 1) << 24)
 124 #define AFE_TDM_CON1_32_BCK_CYCLES      (0x2 << 12)
 125 #define AFE_TDM_CON1_WLEN_32BIT         (0x2 << 8)
 126 #define AFE_TDM_CON1_MSB_ALIGNED        (0x1 << 4)
 127 #define AFE_TDM_CON1_1_BCK_DELAY        (0x1 << 3)
 128 #define AFE_TDM_CON1_LRCK_INV           (0x1 << 2)
 129 #define AFE_TDM_CON1_BCK_INV            (0x1 << 1)
 130 #define AFE_TDM_CON1_EN                 (0x1 << 0)
 131
 132 enum afe_tdm_ch_start {
 133         AFE_TDM_CH_START_O30_O31 = 0,
 134         AFE_TDM_CH_START_O32_O33,
 135         AFE_TDM_CH_START_O34_O35,
 136         AFE_TDM_CH_START_O36_O37,
 137         AFE_TDM_CH_ZERO,
 138 };
 139
 140 static const unsigned int mt8173_afe_backup_list[] = {
 141         AUDIO_TOP_CON0,
 142         AFE_CONN1,
 143         AFE_CONN2,
 144         AFE_CONN7,
 145         AFE_CONN8,
 146         AFE_DAC_CON1,
 147         AFE_DL1_BASE,
 148         AFE_DL1_END,
 149         AFE_VUL_BASE,
 150         AFE_VUL_END,
 151         AFE_HDMI_OUT_BASE,
 152         AFE_HDMI_OUT_END,
 153         AFE_HDMI_CONN0,
 154         AFE_DAC_CON0,
 155 };
 156
 157 struct mt8173_afe_private {
 158         struct clk *clocks[MT8173_CLK_NUM];
 159 };
 160
 161 static const struct snd_pcm_hardware mt8173_afe_hardware = {
 162         .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 163                  SNDRV_PCM_INFO_MMAP_VALID),
 164         .buffer_bytes_max = 256 * 1024,
 165         .period_bytes_min = 512,
 166         .period_bytes_max = 128 * 1024,
 167         .periods_min = 2,
 168         .periods_max = 256,
 169         .fifo_size = 0,
 170 };
 171
 172 struct mt8173_afe_rate {
 173         unsigned int rate;
 174         unsigned int regvalue;
 175 };
 176
 177 static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = {
 178         { .rate = 8000, .regvalue = 0 },
 179         { .rate = 11025, .regvalue = 1 },
 180         { .rate = 12000, .regvalue = 2 },
 181         { .rate = 16000, .regvalue = 4 },
 182         { .rate = 22050, .regvalue = 5 },
 183         { .rate = 24000, .regvalue = 6 },
 184         { .rate = 32000, .regvalue = 8 },
 185         { .rate = 44100, .regvalue = 9 },
 186         { .rate = 48000, .regvalue = 10 },
 187         { .rate = 88000, .regvalue = 11 },
 188         { .rate = 96000, .regvalue = 12 },
 189         { .rate = 174000, .regvalue = 13 },
 190         { .rate = 192000, .regvalue = 14 },
 191 };
 192
 193 static int mt8173_afe_i2s_fs(unsigned int sample_rate)
 194 {
 195         int i;
 196
 197         for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++)
 198                 if (mt8173_afe_i2s_rates[i].rate == sample_rate)
 199                         return mt8173_afe_i2s_rates[i].regvalue;
 200
 201         return -EINVAL;
 202 }
 203
 204 static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate)
 205 {
 206         unsigned int val;
 207         int fs = mt8173_afe_i2s_fs(rate);
 208
 209         if (fs < 0)
 210                 return -EINVAL;
 211
 212         /* from external ADC */
 213         regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
 214         regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
 215
 216         /* set input */
 217         val = AFE_I2S_CON2_LOW_JITTER_CLK |
 218               AFE_I2S_CON2_RATE(fs) |
 219               AFE_I2S_CON2_FORMAT_I2S;
 220
 221         regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
 222
 223         /* set output */
 224         val = AFE_I2S_CON1_LOW_JITTER_CLK |
 225               AFE_I2S_CON1_RATE(fs) |
 226               AFE_I2S_CON1_FORMAT_I2S;
 227
 228         regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
 229         return 0;
 230 }
 231
 232 static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable)
 233 {
 234         unsigned int val;
 235
 236         regmap_read(afe->regmap, AFE_I2S_CON2, &val);
 237         if (!!(val & AFE_I2S_CON2_EN) == enable)
 238                 return;
 239
 240         /* input */
 241         regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
 242
 243         /* output */
 244         regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
 245 }
 246
 247 static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe,
 248                                        struct clk *m_ck, struct clk *b_ck)
 249 {
 250         int ret;
 251
 252         if (m_ck) {
 253                 ret = clk_prepare_enable(m_ck);
 254                 if (ret) {
 255                         dev_err(afe->dev, "Failed to enable m_ck\n");
 256                         return ret;
 257                 }
 258         }
 259
 260         if (b_ck) {
 261                 ret = clk_prepare_enable(b_ck);
 262                 if (ret) {
 263                         dev_err(afe->dev, "Failed to enable b_ck\n");
 264                         return ret;
 265                 }
 266         }
 267         return 0;
 268 }
 269
 270 static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe,
 271                                     struct clk *m_ck, unsigned int mck_rate,
 272                                     struct clk *b_ck, unsigned int bck_rate)
 273 {
 274         int ret;
 275
 276         if (m_ck) {
 277                 ret = clk_set_rate(m_ck, mck_rate);
 278                 if (ret) {
 279                         dev_err(afe->dev, "Failed to set m_ck rate\n");
 280                         return ret;
 281                 }
 282         }
 283
 284         if (b_ck) {
 285                 ret = clk_set_rate(b_ck, bck_rate);
 286                 if (ret) {
 287                         dev_err(afe->dev, "Failed to set b_ck rate\n");
 288                         return ret;
 289                 }
 290         }
 291         return 0;
 292 }
 293
 294 static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe,
 295                                          struct clk *m_ck, struct clk *b_ck)
 296 {
 297         if (m_ck)
 298                 clk_disable_unprepare(m_ck);
 299         if (b_ck)
 300                 clk_disable_unprepare(b_ck);
 301 }
 302
 303 static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream,
 304                                   struct snd_soc_dai *dai)
 305 {
 306         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 307         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 308
 309         if (dai->active)
 310                 return 0;
 311
 312         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 313                            AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
 314         return 0;
 315 }
 316
 317 static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream,
 318                                     struct snd_soc_dai *dai)
 319 {
 320         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 321         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 322
 323         if (dai->active)
 324                 return;
 325
 326         mt8173_afe_set_i2s_enable(afe, false);
 327         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 328                            AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
 329                            AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
 330 }
 331
 332 static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream,
 333                                   struct snd_soc_dai *dai)
 334 {
 335         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 336         struct snd_pcm_runtime * const runtime = substream->runtime;
 337         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 338         struct mt8173_afe_private *afe_priv = afe->platform_priv;
 339         int ret;
 340
 341         mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
 342                                  runtime->rate * 256, NULL, 0);
 343         mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
 344                                  runtime->rate * 256, NULL, 0);
 345         /* config I2S */
 346         ret = mt8173_afe_set_i2s(afe, substream->runtime->rate);
 347         if (ret)
 348                 return ret;
 349
 350         mt8173_afe_set_i2s_enable(afe, true);
 351
 352         return 0;
 353 }
 354
 355 static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream,
 356                                    struct snd_soc_dai *dai)
 357 {
 358         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 359         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 360         struct mt8173_afe_private *afe_priv = afe->platform_priv;
 361
 362         if (dai->active)
 363                 return 0;
 364
 365         mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
 366                                     afe_priv->clocks[MT8173_CLK_I2S3_B]);
 367         return 0;
 368 }
 369
 370 static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
 371                                      struct snd_soc_dai *dai)
 372 {
 373         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 374         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 375         struct mt8173_afe_private *afe_priv = afe->platform_priv;
 376
 377         if (dai->active)
 378                 return;
 379
 380         mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
 381                                      afe_priv->clocks[MT8173_CLK_I2S3_B]);
 382 }
 383
 384 static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream,
 385                                    struct snd_soc_dai *dai)
 386 {
 387         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 388         struct snd_pcm_runtime * const runtime = substream->runtime;
 389         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 390         struct mt8173_afe_private *afe_priv = afe->platform_priv;
 391
 392         unsigned int val;
 393
 394         mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
 395                                  runtime->rate * 128,
 396                                  afe_priv->clocks[MT8173_CLK_I2S3_B],
 397                                  runtime->rate * runtime->channels * 32);
 398
 399         val = AFE_TDM_CON1_BCK_INV |
 400               AFE_TDM_CON1_LRCK_INV |
 401               AFE_TDM_CON1_1_BCK_DELAY |
 402               AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
 403               AFE_TDM_CON1_WLEN_32BIT |
 404               AFE_TDM_CON1_32_BCK_CYCLES |
 405               AFE_TDM_CON1_LRCK_WIDTH(32);
 406         regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
 407
 408         /* set tdm2 config */
 409         switch (runtime->channels) {
 410         case 1:
 411         case 2:
 412                 val = AFE_TDM_CH_START_O30_O31;
 413                 val |= (AFE_TDM_CH_ZERO << 4);
 414                 val |= (AFE_TDM_CH_ZERO << 8);
 415                 val |= (AFE_TDM_CH_ZERO << 12);
 416                 break;
 417         case 3:
 418         case 4:
 419                 val = AFE_TDM_CH_START_O30_O31;
 420                 val |= (AFE_TDM_CH_START_O32_O33 << 4);
 421                 val |= (AFE_TDM_CH_ZERO << 8);
 422                 val |= (AFE_TDM_CH_ZERO << 12);
 423                 break;
 424         case 5:
 425         case 6:
 426                 val = AFE_TDM_CH_START_O30_O31;
 427                 val |= (AFE_TDM_CH_START_O32_O33 << 4);
 428                 val |= (AFE_TDM_CH_START_O34_O35 << 8);
 429                 val |= (AFE_TDM_CH_ZERO << 12);
 430                 break;
 431         case 7:
 432         case 8:
 433                 val = AFE_TDM_CH_START_O30_O31;
 434                 val |= (AFE_TDM_CH_START_O32_O33 << 4);
 435                 val |= (AFE_TDM_CH_START_O34_O35 << 8);
 436                 val |= (AFE_TDM_CH_START_O36_O37 << 12);
 437                 break;
 438         default:
 439                 val = 0;
 440         }
 441         regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
 442
 443         regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
 444                            0x000000f0, runtime->channels << 4);
 445         return 0;
 446 }
 447
 448 static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
 449                                    struct snd_soc_dai *dai)
 450 {
 451         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 452         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 453
 454         dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
 455
 456         switch (cmd) {
 457         case SNDRV_PCM_TRIGGER_START:
 458         case SNDRV_PCM_TRIGGER_RESUME:
 459                 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 460                                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
 461
 462                 /* set connections:  O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
 463                 regmap_write(afe->regmap, AFE_HDMI_CONN0,
 464                                  AFE_HDMI_CONN0_O30_I30 |
 465                                  AFE_HDMI_CONN0_O31_I31 |
 466                                  AFE_HDMI_CONN0_O32_I34 |
 467                                  AFE_HDMI_CONN0_O33_I35 |
 468                                  AFE_HDMI_CONN0_O34_I32 |
 469                                  AFE_HDMI_CONN0_O35_I33 |
 470                                  AFE_HDMI_CONN0_O36_I36 |
 471                                  AFE_HDMI_CONN0_O37_I37);
 472
 473                 /* enable Out control */
 474                 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
 475
 476                 /* enable tdm */
 477                 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
 478
 479                 return 0;
 480         case SNDRV_PCM_TRIGGER_STOP:
 481         case SNDRV_PCM_TRIGGER_SUSPEND:
 482                 /* disable tdm */
 483                 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
 484
 485                 /* disable Out control */
 486                 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
 487
 488                 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 489                                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
 490                                    AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
 491                 return 0;
 492         default:
 493                 return -EINVAL;
 494         }
 495 }
 496
 497 static int mt8173_memif_fs(struct snd_pcm_substream *substream,
 498                            unsigned int rate)
 499 {
 500         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 501         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 502         struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
 503         int fs;
 504
 505         if (memif->data->id == MT8173_AFE_MEMIF_DAI ||
 506             memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) {
 507                 switch (rate) {
 508                 case 8000:
 509                         fs = 0;
 510                         break;
 511                 case 16000:
 512                         fs = 1;
 513                         break;
 514                 case 32000:
 515                         fs = 2;
 516                         break;
 517                 default:
 518                         return -EINVAL;
 519                 }
 520         } else {
 521                 fs = mt8173_afe_i2s_fs(rate);
 522         }
 523         return fs;
 524 }
 525
 526 static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
 527 {
 528         return mt8173_afe_i2s_fs(rate);
 529 }
 530
 531 /* BE DAIs */
 532 static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = {
 533         .startup        = mt8173_afe_i2s_startup,
 534         .shutdown       = mt8173_afe_i2s_shutdown,
 535         .prepare        = mt8173_afe_i2s_prepare,
 536 };
 537
 538 static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = {
 539         .startup        = mt8173_afe_hdmi_startup,
 540         .shutdown       = mt8173_afe_hdmi_shutdown,
 541         .prepare        = mt8173_afe_hdmi_prepare,
 542         .trigger        = mt8173_afe_hdmi_trigger,
 543 };
 544
 545 static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = {
 546         /* FE DAIs: memory intefaces to CPU */
 547         {
 548                 .name = "DL1", /* downlink 1 */
 549                 .id = MT8173_AFE_MEMIF_DL1,
 550                 .suspend = mtk_afe_dai_suspend,
 551                 .resume = mtk_afe_dai_resume,
 552                 .playback = {
 553                         .stream_name = "DL1",
 554                         .channels_min = 1,
 555                         .channels_max = 2,
 556                         .rates = SNDRV_PCM_RATE_8000_48000,
 557                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 558                 },
 559                 .ops = &mtk_afe_fe_ops,
 560         }, {
 561                 .name = "VUL", /* voice uplink */
 562                 .id = MT8173_AFE_MEMIF_VUL,
 563                 .suspend = mtk_afe_dai_suspend,
 564                 .resume = mtk_afe_dai_resume,
 565                 .capture = {
 566                         .stream_name = "VUL",
 567                         .channels_min = 1,
 568                         .channels_max = 2,
 569                         .rates = SNDRV_PCM_RATE_8000_48000,
 570                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 571                 },
 572                 .ops = &mtk_afe_fe_ops,
 573         }, {
 574         /* BE DAIs */
 575                 .name = "I2S",
 576                 .id = MT8173_AFE_IO_I2S,
 577                 .playback = {
 578                         .stream_name = "I2S Playback",
 579                         .channels_min = 1,
 580                         .channels_max = 2,
 581                         .rates = SNDRV_PCM_RATE_8000_48000,
 582                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 583                 },
 584                 .capture = {
 585                         .stream_name = "I2S Capture",
 586                         .channels_min = 1,
 587                         .channels_max = 2,
 588                         .rates = SNDRV_PCM_RATE_8000_48000,
 589                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 590                 },
 591                 .ops = &mt8173_afe_i2s_ops,
 592                 .symmetric_rates = 1,
 593         },
 594 };
 595
 596 static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = {
 597         /* FE DAIs */
 598         {
 599                 .name = "HDMI",
 600                 .id = MT8173_AFE_MEMIF_HDMI,
 601                 .suspend = mtk_afe_dai_suspend,
 602                 .resume = mtk_afe_dai_resume,
 603                 .playback = {
 604                         .stream_name = "HDMI",
 605                         .channels_min = 2,
 606                         .channels_max = 8,
 607                         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 608                                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 609                                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 610                                 SNDRV_PCM_RATE_192000,
 611                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 612                 },
 613                 .ops = &mtk_afe_fe_ops,
 614         }, {
 615         /* BE DAIs */
 616                 .name = "HDMIO",
 617                 .id = MT8173_AFE_IO_HDMI,
 618                 .playback = {
 619                         .stream_name = "HDMIO Playback",
 620                         .channels_min = 2,
 621                         .channels_max = 8,
 622                         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 623                                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 624                                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 625                                 SNDRV_PCM_RATE_192000,
 626                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 627                 },
 628                 .ops = &mt8173_afe_hdmi_ops,
 629         },
 630 };
 631
 632 static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = {
 633         SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
 634 };
 635
 636 static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = {
 637         SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
 638 };
 639
 640 static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = {
 641         SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
 642         SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
 643 };
 644
 645 static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = {
 646         SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
 647         SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
 648 };
 649
 650 static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = {
 651         /* inter-connections */
 652         SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
 653         SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
 654         SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
 655         SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
 656         SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
 657         SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
 658
 659         SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
 660                            mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)),
 661         SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
 662                            mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)),
 663         SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
 664                            mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)),
 665         SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
 666                            mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)),
 667 };
 668
 669 static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = {
 670         {"I05", NULL, "DL1"},
 671         {"I06", NULL, "DL1"},
 672         {"I2S Playback", NULL, "O03"},
 673         {"I2S Playback", NULL, "O04"},
 674         {"VUL", NULL, "O09"},
 675         {"VUL", NULL, "O10"},
 676         {"I03", NULL, "I2S Capture"},
 677         {"I04", NULL, "I2S Capture"},
 678         {"I17", NULL, "I2S Capture"},
 679         {"I18", NULL, "I2S Capture"},
 680         { "O03", "I05 Switch", "I05" },
 681         { "O04", "I06 Switch", "I06" },
 682         { "O09", "I17 Switch", "I17" },
 683         { "O09", "I03 Switch", "I03" },
 684         { "O10", "I18 Switch", "I18" },
 685         { "O10", "I04 Switch", "I04" },
 686 };
 687
 688 static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = {
 689         {"HDMIO Playback", NULL, "HDMI"},
 690 };
 691
 692 static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = {
 693         .name = "mt8173-afe-pcm-dai",
 694         .dapm_widgets = mt8173_afe_pcm_widgets,
 695         .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets),
 696         .dapm_routes = mt8173_afe_pcm_routes,
 697         .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes),
 698 };
 699
 700 static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = {
 701         .name = "mt8173-afe-hdmi-dai",
 702         .dapm_routes = mt8173_afe_hdmi_routes,
 703         .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes),
 704 };
 705
 706 static const char *aud_clks[MT8173_CLK_NUM] = {
 707         [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
 708         [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio",
 709         [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
 710         [MT8173_CLK_I2S0_M] =  "i2s0_m",
 711         [MT8173_CLK_I2S1_M] =  "i2s1_m",
 712         [MT8173_CLK_I2S2_M] =  "i2s2_m",
 713         [MT8173_CLK_I2S3_M] =  "i2s3_m",
 714         [MT8173_CLK_I2S3_B] =  "i2s3_b",
 715         [MT8173_CLK_BCK0] =  "bck0",
 716         [MT8173_CLK_BCK1] =  "bck1",
 717 };
 718
 719 static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
 720         {
 721                 .name = "DL1",
 722                 .id = MT8173_AFE_MEMIF_DL1,
 723                 .reg_ofs_base = AFE_DL1_BASE,
 724                 .reg_ofs_cur = AFE_DL1_CUR,
 725                 .fs_reg = AFE_DAC_CON1,
 726                 .fs_shift = 0,
 727                 .fs_maskbit = 0xf,
 728                 .mono_reg = AFE_DAC_CON1,
 729                 .mono_shift = 21,
 730                 .hd_reg = -1,
 731                 .hd_shift = -1,
 732                 .enable_reg = AFE_DAC_CON0,
 733                 .enable_shift = 1,
 734                 .msb_reg = AFE_MEMIF_MSB,
 735                 .msb_shift = 0,
 736                 .agent_disable_reg = -1,
 737                 .agent_disable_shift = -1,
 738         }, {
 739                 .name = "DL2",
 740                 .id = MT8173_AFE_MEMIF_DL2,
 741                 .reg_ofs_base = AFE_DL2_BASE,
 742                 .reg_ofs_cur = AFE_DL2_CUR,
 743                 .fs_reg = AFE_DAC_CON1,
 744                 .fs_shift = 4,
 745                 .fs_maskbit = 0xf,
 746                 .mono_reg = AFE_DAC_CON1,
 747                 .mono_shift = 22,
 748                 .hd_reg = -1,
 749                 .hd_shift = -1,
 750                 .enable_reg = AFE_DAC_CON0,
 751                 .enable_shift = 2,
 752                 .msb_reg = AFE_MEMIF_MSB,
 753                 .msb_shift = 1,
 754                 .agent_disable_reg = -1,
 755                 .agent_disable_shift = -1,
 756         }, {
 757                 .name = "VUL",
 758                 .id = MT8173_AFE_MEMIF_VUL,
 759                 .reg_ofs_base = AFE_VUL_BASE,
 760                 .reg_ofs_cur = AFE_VUL_CUR,
 761                 .fs_reg = AFE_DAC_CON1,
 762                 .fs_shift = 16,
 763                 .fs_maskbit = 0xf,
 764                 .mono_reg = AFE_DAC_CON1,
 765                 .mono_shift = 27,
 766                 .hd_reg = -1,
 767                 .hd_shift = -1,
 768                 .enable_reg = AFE_DAC_CON0,
 769                 .enable_shift = 3,
 770                 .msb_reg = AFE_MEMIF_MSB,
 771                 .msb_shift = 6,
 772                 .agent_disable_reg = -1,
 773                 .agent_disable_shift = -1,
 774         }, {
 775                 .name = "DAI",
 776                 .id = MT8173_AFE_MEMIF_DAI,
 777                 .reg_ofs_base = AFE_DAI_BASE,
 778                 .reg_ofs_cur = AFE_DAI_CUR,
 779                 .fs_reg = AFE_DAC_CON0,
 780                 .fs_shift = 24,
 781                 .fs_maskbit = 0x3,
 782                 .mono_reg = -1,
 783                 .mono_shift = -1,
 784                 .hd_reg = -1,
 785                 .hd_shift = -1,
 786                 .enable_reg = AFE_DAC_CON0,
 787                 .enable_shift = 4,
 788                 .msb_reg = AFE_MEMIF_MSB,
 789                 .msb_shift = 5,
 790                 .agent_disable_reg = -1,
 791                 .agent_disable_shift = -1,
 792         }, {
 793                 .name = "AWB",
 794                 .id = MT8173_AFE_MEMIF_AWB,
 795                 .reg_ofs_base = AFE_AWB_BASE,
 796                 .reg_ofs_cur = AFE_AWB_CUR,
 797                 .fs_reg = AFE_DAC_CON1,
 798                 .fs_shift = 12,
 799                 .fs_maskbit = 0xf,
 800                 .mono_reg = AFE_DAC_CON1,
 801                 .mono_shift = 24,
 802                 .hd_reg = -1,
 803                 .hd_shift = -1,
 804                 .enable_reg = AFE_DAC_CON0,
 805                 .enable_shift = 6,
 806                 .msb_reg = AFE_MEMIF_MSB,
 807                 .msb_shift = 3,
 808                 .agent_disable_reg = -1,
 809                 .agent_disable_shift = -1,
 810         }, {
 811                 .name = "MOD_DAI",
 812                 .id = MT8173_AFE_MEMIF_MOD_DAI,
 813                 .reg_ofs_base = AFE_MOD_PCM_BASE,
 814                 .reg_ofs_cur = AFE_MOD_PCM_CUR,
 815                 .fs_reg = AFE_DAC_CON1,
 816                 .fs_shift = 30,
 817                 .fs_maskbit = 0x3,
 818                 .mono_reg = AFE_DAC_CON1,
 819                 .mono_shift = 30,
 820                 .hd_reg = -1,
 821                 .hd_shift = -1,
 822                 .enable_reg = AFE_DAC_CON0,
 823                 .enable_shift = 7,
 824                 .msb_reg = AFE_MEMIF_MSB,
 825                 .msb_shift = 4,
 826                 .agent_disable_reg = -1,
 827                 .agent_disable_shift = -1,
 828         }, {
 829                 .name = "HDMI",
 830                 .id = MT8173_AFE_MEMIF_HDMI,
 831                 .reg_ofs_base = AFE_HDMI_OUT_BASE,
 832                 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
 833                 .fs_reg = -1,
 834                 .fs_shift = -1,
 835                 .fs_maskbit = -1,
 836                 .mono_reg = -1,
 837                 .mono_shift = -1,
 838                 .hd_reg = -1,
 839                 .hd_shift = -1,
 840                 .enable_reg = -1,
 841                 .enable_shift = -1,
 842                 .msb_reg = AFE_MEMIF_MSB,
 843                 .msb_shift = 8,
 844                 .agent_disable_reg = -1,
 845                 .agent_disable_shift = -1,
 846         },
 847 };
 848
 849 static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
 850         {
 851                 .id = MT8173_AFE_IRQ_DL1,
 852                 .irq_cnt_reg = AFE_IRQ_CNT1,
 853                 .irq_cnt_shift = 0,
 854                 .irq_cnt_maskbit = 0x3ffff,
 855                 .irq_en_reg = AFE_IRQ_MCU_CON,
 856                 .irq_en_shift = 0,
 857                 .irq_fs_reg = AFE_IRQ_MCU_CON,
 858                 .irq_fs_shift = 4,
 859                 .irq_fs_maskbit = 0xf,
 860                 .irq_clr_reg = AFE_IRQ_CLR,
 861                 .irq_clr_shift = 0,
 862         }, {
 863                 .id = MT8173_AFE_IRQ_DL2,
 864                 .irq_cnt_reg = AFE_IRQ_CNT1,
 865                 .irq_cnt_shift = 20,
 866                 .irq_cnt_maskbit = 0x3ffff,
 867                 .irq_en_reg = AFE_IRQ_MCU_CON,
 868                 .irq_en_shift = 2,
 869                 .irq_fs_reg = AFE_IRQ_MCU_CON,
 870                 .irq_fs_shift = 16,
 871                 .irq_fs_maskbit = 0xf,
 872                 .irq_clr_reg = AFE_IRQ_CLR,
 873                 .irq_clr_shift = 2,
 874
 875         }, {
 876                 .id = MT8173_AFE_IRQ_VUL,
 877                 .irq_cnt_reg = AFE_IRQ_CNT2,
 878                 .irq_cnt_shift = 0,
 879                 .irq_cnt_maskbit = 0x3ffff,
 880                 .irq_en_reg = AFE_IRQ_MCU_CON,
 881                 .irq_en_shift = 1,
 882                 .irq_fs_reg = AFE_IRQ_MCU_CON,
 883                 .irq_fs_shift = 8,
 884                 .irq_fs_maskbit = 0xf,
 885                 .irq_clr_reg = AFE_IRQ_CLR,
 886                 .irq_clr_shift = 1,
 887         }, {
 888                 .id = MT8173_AFE_IRQ_DAI,
 889                 .irq_cnt_reg = AFE_IRQ_CNT2,
 890                 .irq_cnt_shift = 20,
 891                 .irq_cnt_maskbit = 0x3ffff,
 892                 .irq_en_reg = AFE_IRQ_MCU_CON,
 893                 .irq_en_shift = 3,
 894                 .irq_fs_reg = AFE_IRQ_MCU_CON,
 895                 .irq_fs_shift = 20,
 896                 .irq_fs_maskbit = 0xf,
 897                 .irq_clr_reg = AFE_IRQ_CLR,
 898                 .irq_clr_shift = 3,
 899         }, {
 900                 .id = MT8173_AFE_IRQ_AWB,
 901                 .irq_cnt_reg = AFE_IRQ_CNT7,
 902                 .irq_cnt_shift = 0,
 903                 .irq_cnt_maskbit = 0x3ffff,
 904                 .irq_en_reg = AFE_IRQ_MCU_CON,
 905                 .irq_en_shift = 14,
 906                 .irq_fs_reg = AFE_IRQ_MCU_CON,
 907                 .irq_fs_shift = 24,
 908                 .irq_fs_maskbit = 0xf,
 909                 .irq_clr_reg = AFE_IRQ_CLR,
 910                 .irq_clr_shift = 6,
 911         }, {
 912                 .id = MT8173_AFE_IRQ_DAI,
 913                 .irq_cnt_reg = AFE_IRQ_CNT2,
 914                 .irq_cnt_shift = 20,
 915                 .irq_cnt_maskbit = 0x3ffff,
 916                 .irq_en_reg = AFE_IRQ_MCU_CON,
 917                 .irq_en_shift = 3,
 918                 .irq_fs_reg = AFE_IRQ_MCU_CON,
 919                 .irq_fs_shift = 20,
 920                 .irq_fs_maskbit = 0xf,
 921                 .irq_clr_reg = AFE_IRQ_CLR,
 922                 .irq_clr_shift = 3,
 923         }, {
 924                 .id = MT8173_AFE_IRQ_HDMI,
 925                 .irq_cnt_reg = AFE_IRQ_CNT5,
 926                 .irq_cnt_shift = 0,
 927                 .irq_cnt_maskbit = 0x3ffff,
 928                 .irq_en_reg = AFE_IRQ_MCU_CON,
 929                 .irq_en_shift = 12,
 930                 .irq_fs_reg = -1,
 931                 .irq_fs_shift = -1,
 932                 .irq_fs_maskbit = -1,
 933                 .irq_clr_reg = AFE_IRQ_CLR,
 934                 .irq_clr_shift = 4,
 935         },
 936 };
 937
 938 static const struct regmap_config mt8173_afe_regmap_config = {
 939         .reg_bits = 32,
 940         .reg_stride = 4,
 941         .val_bits = 32,
 942         .max_register = AFE_ADDA2_TOP_CON0,
 943         .cache_type = REGCACHE_NONE,
 944 };
 945
 946 static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id)
 947 {
 948         struct mtk_base_afe *afe = dev_id;
 949         unsigned int reg_value;
 950         int i, ret;
 951
 952         ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
 953         if (ret) {
 954                 dev_err(afe->dev, "%s irq status err\n", __func__);
 955                 reg_value = AFE_IRQ_STATUS_BITS;
 956                 goto err_irq;
 957         }
 958
 959         for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) {
 960                 struct mtk_base_afe_memif *memif = &afe->memif[i];
 961                 struct mtk_base_afe_irq *irq;
 962
 963                 if (memif->irq_usage < 0)
 964                         continue;
 965
 966                 irq = &afe->irqs[memif->irq_usage];
 967
 968                 if (!(reg_value & (1 << irq->irq_data->irq_clr_shift)))
 969                         continue;
 970
 971                 snd_pcm_period_elapsed(memif->substream);
 972         }
 973
 974 err_irq:
 975         /* clear irq */
 976         regmap_write(afe->regmap, AFE_IRQ_CLR,
 977                      reg_value & AFE_IRQ_STATUS_BITS);
 978
 979         return IRQ_HANDLED;
 980 }
 981
 982 static int mt8173_afe_runtime_suspend(struct device *dev)
 983 {
 984         struct mtk_base_afe *afe = dev_get_drvdata(dev);
 985         struct mt8173_afe_private *afe_priv = afe->platform_priv;
 986
 987         /* disable AFE */
 988         regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
 989
 990         /* disable AFE clk */
 991         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
 992                            AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
 993
 994         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
 995         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
 996         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
 997         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
 998         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
 999         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1000         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1001         return 0;
1002 }
1003
1004 static int mt8173_afe_runtime_resume(struct device *dev)
1005 {
1006         struct mtk_base_afe *afe = dev_get_drvdata(dev);
1007         struct mt8173_afe_private *afe_priv = afe->platform_priv;
1008         int ret;
1009
1010         ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1011         if (ret)
1012                 return ret;
1013
1014         ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1015         if (ret)
1016                 goto err_infra;
1017
1018         ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1019         if (ret)
1020                 goto err_top_aud_bus;
1021
1022         ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
1023         if (ret)
1024                 goto err_top_aud;
1025
1026         ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
1027         if (ret)
1028                 goto err_bck0;
1029         ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1030         if (ret)
1031                 goto err_i2s1_m;
1032         ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1033         if (ret)
1034                 goto err_i2s2_m;
1035
1036         /* enable AFE clk */
1037         regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1038
1039         /* set O3/O4 16bits */
1040         regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1041                            AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1042
1043         /* unmask all IRQs */
1044         regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1045
1046         /* enable AFE */
1047         regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1048         return 0;
1049
1050 err_i2s1_m:
1051         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1052 err_i2s2_m:
1053         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1054 err_bck0:
1055         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
1056 err_top_aud:
1057         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1058 err_top_aud_bus:
1059         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1060 err_infra:
1061         clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1062         return ret;
1063 }
1064
1065 static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
1066 {
1067         size_t i;
1068         struct mt8173_afe_private *afe_priv = afe->platform_priv;
1069
1070         for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1071                 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1072                 if (IS_ERR(afe_priv->clocks[i])) {
1073                         dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1074                                 __func__, aud_clks[i]);
1075                         return PTR_ERR(afe_priv->clocks[i]);
1076                 }
1077         }
1078         clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
1079         clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */
1080         return 0;
1081 }
1082
1083 static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
1084 {
1085         int ret, i;
1086         int irq_id;
1087         struct mtk_base_afe *afe;
1088         struct mt8173_afe_private *afe_priv;
1089         struct resource *res;
1090
1091         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
1092         if (ret)
1093                 return ret;
1094
1095         afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1096         if (!afe)
1097                 return -ENOMEM;
1098
1099         afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1100                                           GFP_KERNEL);
1101         afe_priv = afe->platform_priv;
1102         if (!afe_priv)
1103                 return -ENOMEM;
1104
1105         afe->dev = &pdev->dev;
1106
1107         irq_id = platform_get_irq(pdev, 0);
1108         if (irq_id <= 0) {
1109                 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1110                 return irq_id < 0 ? irq_id : -ENXIO;
1111         }
1112         ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
1113                                0, "Afe_ISR_Handle", (void *)afe);
1114         if (ret) {
1115                 dev_err(afe->dev, "could not request_irq\n");
1116                 return ret;
1117         }
1118
1119         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120         afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1121         if (IS_ERR(afe->base_addr))
1122                 return PTR_ERR(afe->base_addr);
1123
1124         afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1125                 &mt8173_afe_regmap_config);
1126         if (IS_ERR(afe->regmap))
1127                 return PTR_ERR(afe->regmap);
1128
1129         /* initial audio related clock */
1130         ret = mt8173_afe_init_audio_clk(afe);
1131         if (ret) {
1132                 dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n");
1133                 return ret;
1134         }
1135
1136         /* memif % irq initialize*/
1137         afe->memif_size = MT8173_AFE_MEMIF_NUM;
1138         afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
1139                                   sizeof(*afe->memif), GFP_KERNEL);
1140         if (!afe->memif)
1141                 return -ENOMEM;
1142
1143         afe->irqs_size = MT8173_AFE_IRQ_NUM;
1144         afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
1145                                  sizeof(*afe->irqs), GFP_KERNEL);
1146         if (!afe->irqs)
1147                 return -ENOMEM;
1148
1149         for (i = 0; i < afe->irqs_size; i++) {
1150                 afe->memif[i].data = &memif_data[i];
1151                 afe->irqs[i].irq_data = &irq_data[i];
1152                 afe->irqs[i].irq_occupyed = true;
1153                 afe->memif[i].irq_usage = i;
1154                 afe->memif[i].const_irq = 1;
1155         }
1156
1157         afe->mtk_afe_hardware = &mt8173_afe_hardware;
1158         afe->memif_fs = mt8173_memif_fs;
1159         afe->irq_fs = mt8173_irq_fs;
1160
1161         platform_set_drvdata(pdev, afe);
1162
1163         pm_runtime_enable(&pdev->dev);
1164         if (!pm_runtime_enabled(&pdev->dev)) {
1165                 ret = mt8173_afe_runtime_resume(&pdev->dev);
1166                 if (ret)
1167                         goto err_pm_disable;
1168         }
1169
1170         afe->reg_back_up_list = mt8173_afe_backup_list;
1171         afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list);
1172         afe->runtime_resume = mt8173_afe_runtime_resume;
1173         afe->runtime_suspend = mt8173_afe_runtime_suspend;
1174
1175         ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
1176         if (ret)
1177                 goto err_pm_disable;
1178
1179         ret = snd_soc_register_component(&pdev->dev,
1180                                          &mt8173_afe_pcm_dai_component,
1181                                          mt8173_afe_pcm_dais,
1182                                          ARRAY_SIZE(mt8173_afe_pcm_dais));
1183         if (ret)
1184                 goto err_platform;
1185
1186         ret = snd_soc_register_component(&pdev->dev,
1187                                          &mt8173_afe_hdmi_dai_component,
1188                                          mt8173_afe_hdmi_dais,
1189                                          ARRAY_SIZE(mt8173_afe_hdmi_dais));
1190         if (ret)
1191                 goto err_comp;
1192
1193         dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n");
1194         return 0;
1195
1196 err_comp:
1197         snd_soc_unregister_component(&pdev->dev);
1198 err_platform:
1199         snd_soc_unregister_platform(&pdev->dev);
1200 err_pm_disable:
1201         pm_runtime_disable(&pdev->dev);
1202         return ret;
1203 }
1204
1205 static int mt8173_afe_pcm_dev_remove(struct platform_device *pdev)
1206 {
1207         pm_runtime_disable(&pdev->dev);
1208         if (!pm_runtime_status_suspended(&pdev->dev))
1209                 mt8173_afe_runtime_suspend(&pdev->dev);
1210         snd_soc_unregister_component(&pdev->dev);
1211         snd_soc_unregister_platform(&pdev->dev);
1212         return 0;
1213 }
1214
1215 static const struct of_device_id mt8173_afe_pcm_dt_match[] = {
1216         { .compatible = "mediatek,mt8173-afe-pcm", },
1217         { }
1218 };
1219 MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match);
1220
1221 static const struct dev_pm_ops mt8173_afe_pm_ops = {
1222         SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend,
1223                            mt8173_afe_runtime_resume, NULL)
1224 };
1225
1226 static struct platform_driver mt8173_afe_pcm_driver = {
1227         .driver = {
1228                    .name = "mt8173-afe-pcm",
1229                    .of_match_table = mt8173_afe_pcm_dt_match,
1230                    .pm = &mt8173_afe_pm_ops,
1231         },
1232         .probe = mt8173_afe_pcm_dev_probe,
1233         .remove = mt8173_afe_pcm_dev_remove,
1234 };
1235
1236 module_platform_driver(mt8173_afe_pcm_driver);
1237
1238 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1239 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1240 MODULE_LICENSE("GPL v2");