2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/ctype.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/firmware.h>
19 #include <linux/list.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/vmalloc.h>
26 #include <linux/workqueue.h>
27 #include <linux/debugfs.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/jack.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
38 #define adsp_crit(_dsp, fmt, ...) \
39 dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
40 #define adsp_err(_dsp, fmt, ...) \
41 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
42 #define adsp_warn(_dsp, fmt, ...) \
43 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
44 #define adsp_info(_dsp, fmt, ...) \
45 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
46 #define adsp_dbg(_dsp, fmt, ...) \
47 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
49 #define compr_err(_obj, fmt, ...) \
50 adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
52 #define compr_dbg(_obj, fmt, ...) \
53 adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
56 #define ADSP1_CONTROL_1 0x00
57 #define ADSP1_CONTROL_2 0x02
58 #define ADSP1_CONTROL_3 0x03
59 #define ADSP1_CONTROL_4 0x04
60 #define ADSP1_CONTROL_5 0x06
61 #define ADSP1_CONTROL_6 0x07
62 #define ADSP1_CONTROL_7 0x08
63 #define ADSP1_CONTROL_8 0x09
64 #define ADSP1_CONTROL_9 0x0A
65 #define ADSP1_CONTROL_10 0x0B
66 #define ADSP1_CONTROL_11 0x0C
67 #define ADSP1_CONTROL_12 0x0D
68 #define ADSP1_CONTROL_13 0x0F
69 #define ADSP1_CONTROL_14 0x10
70 #define ADSP1_CONTROL_15 0x11
71 #define ADSP1_CONTROL_16 0x12
72 #define ADSP1_CONTROL_17 0x13
73 #define ADSP1_CONTROL_18 0x14
74 #define ADSP1_CONTROL_19 0x16
75 #define ADSP1_CONTROL_20 0x17
76 #define ADSP1_CONTROL_21 0x18
77 #define ADSP1_CONTROL_22 0x1A
78 #define ADSP1_CONTROL_23 0x1B
79 #define ADSP1_CONTROL_24 0x1C
80 #define ADSP1_CONTROL_25 0x1E
81 #define ADSP1_CONTROL_26 0x20
82 #define ADSP1_CONTROL_27 0x21
83 #define ADSP1_CONTROL_28 0x22
84 #define ADSP1_CONTROL_29 0x23
85 #define ADSP1_CONTROL_30 0x24
86 #define ADSP1_CONTROL_31 0x26
91 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
92 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
93 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
99 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
100 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
101 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
102 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
103 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
104 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
105 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
106 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
107 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
108 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
109 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
110 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
111 #define ADSP1_START 0x0001 /* DSP1_START */
112 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
113 #define ADSP1_START_SHIFT 0 /* DSP1_START */
114 #define ADSP1_START_WIDTH 1 /* DSP1_START */
119 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
120 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
121 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
123 #define ADSP2_CONTROL 0x0
124 #define ADSP2_CLOCKING 0x1
125 #define ADSP2V2_CLOCKING 0x2
126 #define ADSP2_STATUS1 0x4
127 #define ADSP2_WDMA_CONFIG_1 0x30
128 #define ADSP2_WDMA_CONFIG_2 0x31
129 #define ADSP2V2_WDMA_CONFIG_2 0x32
130 #define ADSP2_RDMA_CONFIG_1 0x34
132 #define ADSP2_SCRATCH0 0x40
133 #define ADSP2_SCRATCH1 0x41
134 #define ADSP2_SCRATCH2 0x42
135 #define ADSP2_SCRATCH3 0x43
137 #define ADSP2V2_SCRATCH0_1 0x40
138 #define ADSP2V2_SCRATCH2_3 0x42
144 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
145 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
146 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
147 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
148 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
149 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
150 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
151 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
152 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
153 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
154 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
155 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
156 #define ADSP2_START 0x0001 /* DSP1_START */
157 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
158 #define ADSP2_START_SHIFT 0 /* DSP1_START */
159 #define ADSP2_START_WIDTH 1 /* DSP1_START */
164 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
165 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
166 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
171 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
172 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
173 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
175 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
176 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
177 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
182 #define ADSP2_RAM_RDY 0x0001
183 #define ADSP2_RAM_RDY_MASK 0x0001
184 #define ADSP2_RAM_RDY_SHIFT 0
185 #define ADSP2_RAM_RDY_WIDTH 1
190 #define ADSP2_LOCK_CODE_0 0x5555
191 #define ADSP2_LOCK_CODE_1 0xAAAA
193 #define ADSP2_WATCHDOG 0x0A
194 #define ADSP2_BUS_ERR_ADDR 0x52
195 #define ADSP2_REGION_LOCK_STATUS 0x64
196 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
197 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
198 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
199 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
200 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
201 #define ADSP2_LOCK_REGION_CTRL 0x7A
202 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
204 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
205 #define ADSP2_SLAVE_ERR_MASK 0x4000
206 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
207 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
208 #define ADSP2_CTRL_ERR_EINT 0x0001
210 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
211 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
212 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
213 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
214 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
216 #define ADSP2_LOCK_REGION_SHIFT 16
218 #define ADSP_MAX_STD_CTRL_SIZE 512
220 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
221 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
222 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0
223 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
226 * Event control messages
228 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
233 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040
234 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044
239 #define HALO_SCRATCH1 0x005c0
240 #define HALO_SCRATCH2 0x005c8
241 #define HALO_SCRATCH3 0x005d0
242 #define HALO_SCRATCH4 0x005d8
243 #define HALO_CCM_CORE_CONTROL 0x41000
244 #define HALO_CORE_SOFT_RESET 0x00010
245 #define HALO_WDT_CONTROL 0x47000
250 #define HALO_MPU_XMEM_ACCESS_0 0x43000
251 #define HALO_MPU_YMEM_ACCESS_0 0x43004
252 #define HALO_MPU_WINDOW_ACCESS_0 0x43008
253 #define HALO_MPU_XREG_ACCESS_0 0x4300C
254 #define HALO_MPU_YREG_ACCESS_0 0x43014
255 #define HALO_MPU_XMEM_ACCESS_1 0x43018
256 #define HALO_MPU_YMEM_ACCESS_1 0x4301C
257 #define HALO_MPU_WINDOW_ACCESS_1 0x43020
258 #define HALO_MPU_XREG_ACCESS_1 0x43024
259 #define HALO_MPU_YREG_ACCESS_1 0x4302C
260 #define HALO_MPU_XMEM_ACCESS_2 0x43030
261 #define HALO_MPU_YMEM_ACCESS_2 0x43034
262 #define HALO_MPU_WINDOW_ACCESS_2 0x43038
263 #define HALO_MPU_XREG_ACCESS_2 0x4303C
264 #define HALO_MPU_YREG_ACCESS_2 0x43044
265 #define HALO_MPU_XMEM_ACCESS_3 0x43048
266 #define HALO_MPU_YMEM_ACCESS_3 0x4304C
267 #define HALO_MPU_WINDOW_ACCESS_3 0x43050
268 #define HALO_MPU_XREG_ACCESS_3 0x43054
269 #define HALO_MPU_YREG_ACCESS_3 0x4305C
270 #define HALO_MPU_XM_VIO_ADDR 0x43100
271 #define HALO_MPU_XM_VIO_STATUS 0x43104
272 #define HALO_MPU_YM_VIO_ADDR 0x43108
273 #define HALO_MPU_YM_VIO_STATUS 0x4310C
274 #define HALO_MPU_PM_VIO_ADDR 0x43110
275 #define HALO_MPU_PM_VIO_STATUS 0x43114
276 #define HALO_MPU_LOCK_CONFIG 0x43140
279 * HALO_AHBM_WINDOW_DEBUG_1
281 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00
282 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8
283 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff
286 * HALO_CCM_CORE_CONTROL
288 #define HALO_CORE_EN 0x00000001
291 * HALO_CORE_SOFT_RESET
293 #define HALO_CORE_SOFT_RESET_MASK 0x00000001
298 #define HALO_WDT_EN_MASK 0x00000001
301 * HALO_MPU_?M_VIO_STATUS
303 #define HALO_MPU_VIO_STS_MASK 0x007e0000
304 #define HALO_MPU_VIO_STS_SHIFT 17
305 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000
306 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff
307 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0
309 static struct wm_adsp_ops wm_adsp1_ops;
310 static struct wm_adsp_ops wm_adsp2_ops[];
311 static struct wm_adsp_ops wm_halo_ops;
314 struct list_head list;
318 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
319 struct list_head *list)
321 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
326 buf->buf = vmalloc(len);
331 memcpy(buf->buf, src, len);
334 list_add_tail(&buf->list, list);
339 static void wm_adsp_buf_free(struct list_head *list)
341 while (!list_empty(list)) {
342 struct wm_adsp_buf *buf = list_first_entry(list,
345 list_del(&buf->list);
351 #define WM_ADSP_FW_MBC_VSS 0
352 #define WM_ADSP_FW_HIFI 1
353 #define WM_ADSP_FW_TX 2
354 #define WM_ADSP_FW_TX_SPK 3
355 #define WM_ADSP_FW_RX 4
356 #define WM_ADSP_FW_RX_ANC 5
357 #define WM_ADSP_FW_CTRL 6
358 #define WM_ADSP_FW_ASR 7
359 #define WM_ADSP_FW_TRACE 8
360 #define WM_ADSP_FW_SPK_PROT 9
361 #define WM_ADSP_FW_MISC 10
363 #define WM_ADSP_NUM_FW 11
365 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
366 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
367 [WM_ADSP_FW_HIFI] = "MasterHiFi",
368 [WM_ADSP_FW_TX] = "Tx",
369 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
370 [WM_ADSP_FW_RX] = "Rx",
371 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
372 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
373 [WM_ADSP_FW_ASR] = "ASR Assist",
374 [WM_ADSP_FW_TRACE] = "Dbg Trace",
375 [WM_ADSP_FW_SPK_PROT] = "Protection",
376 [WM_ADSP_FW_MISC] = "Misc",
379 struct wm_adsp_system_config_xm_hdr {
385 __be32 dma_buffer_size;
388 __be32 build_job_name[3];
389 __be32 build_job_number;
392 struct wm_halo_system_config_xm_hdr {
393 __be32 halo_heartbeat;
394 __be32 build_job_name[3];
395 __be32 build_job_number;
398 struct wm_adsp_alg_xm_struct {
404 __be32 high_water_mark;
405 __be32 low_water_mark;
406 __be64 smoothed_power;
409 struct wm_adsp_host_buf_coeff_v1 {
410 __be32 host_buf_ptr; /* Host buffer pointer */
411 __be32 versions; /* Version numbers */
412 __be32 name[4]; /* The buffer name */
415 struct wm_adsp_buffer {
416 __be32 buf1_base; /* Base addr of first buffer area */
417 __be32 buf1_size; /* Size of buf1 area in DSP words */
418 __be32 buf2_base; /* Base addr of 2nd buffer area */
419 __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */
420 __be32 buf3_base; /* Base addr of buf3 area */
421 __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */
422 __be32 high_water_mark; /* Point at which IRQ is asserted */
423 __be32 irq_count; /* bits 1-31 count IRQ assertions */
424 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
425 __be32 next_write_index; /* word index of next write */
426 __be32 next_read_index; /* word index of next read */
427 __be32 error; /* error if any */
428 __be32 oldest_block_index; /* word index of oldest surviving */
429 __be32 requested_rewind; /* how many blocks rewind was done */
430 __be32 reserved_space; /* internal */
431 __be32 min_free; /* min free space since stream start */
432 __be32 blocks_written[2]; /* total blocks written (64 bit) */
433 __be32 words_written[2]; /* total words written (64 bit) */
436 struct wm_adsp_compr;
438 struct wm_adsp_compr_buf {
439 struct list_head list;
441 struct wm_adsp_compr *compr;
443 struct wm_adsp_buffer_region *regions;
450 int host_buf_mem_type;
455 struct wm_adsp_compr {
456 struct list_head list;
458 struct wm_adsp_compr_buf *buf;
460 struct snd_compr_stream *stream;
461 struct snd_compressed_buffer size;
464 unsigned int copied_total;
466 unsigned int sample_rate;
471 #define WM_ADSP_DATA_WORD_SIZE 3
473 #define WM_ADSP_MIN_FRAGMENTS 1
474 #define WM_ADSP_MAX_FRAGMENTS 256
475 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
476 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
478 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
480 #define HOST_BUFFER_FIELD(field) \
481 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
483 #define ALG_XM_FIELD(field) \
484 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
486 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1
488 #define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00
489 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8
491 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
492 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
494 struct wm_adsp_buffer_region {
496 unsigned int cumulative_size;
497 unsigned int mem_type;
498 unsigned int base_addr;
501 struct wm_adsp_buffer_region_def {
502 unsigned int mem_type;
503 unsigned int base_offset;
504 unsigned int size_offset;
507 static const struct wm_adsp_buffer_region_def default_regions[] = {
509 .mem_type = WMFW_ADSP2_XM,
510 .base_offset = HOST_BUFFER_FIELD(buf1_base),
511 .size_offset = HOST_BUFFER_FIELD(buf1_size),
514 .mem_type = WMFW_ADSP2_XM,
515 .base_offset = HOST_BUFFER_FIELD(buf2_base),
516 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
519 .mem_type = WMFW_ADSP2_YM,
520 .base_offset = HOST_BUFFER_FIELD(buf3_base),
521 .size_offset = HOST_BUFFER_FIELD(buf_total_size),
525 struct wm_adsp_fw_caps {
527 struct snd_codec_desc desc;
529 const struct wm_adsp_buffer_region_def *region_defs;
532 static const struct wm_adsp_fw_caps ctrl_caps[] = {
534 .id = SND_AUDIOCODEC_BESPOKE,
537 .sample_rates = { 16000 },
538 .num_sample_rates = 1,
539 .formats = SNDRV_PCM_FMTBIT_S16_LE,
541 .num_regions = ARRAY_SIZE(default_regions),
542 .region_defs = default_regions,
546 static const struct wm_adsp_fw_caps trace_caps[] = {
548 .id = SND_AUDIOCODEC_BESPOKE,
552 4000, 8000, 11025, 12000, 16000, 22050,
553 24000, 32000, 44100, 48000, 64000, 88200,
554 96000, 176400, 192000
556 .num_sample_rates = 15,
557 .formats = SNDRV_PCM_FMTBIT_S16_LE,
559 .num_regions = ARRAY_SIZE(default_regions),
560 .region_defs = default_regions,
564 static const struct {
568 const struct wm_adsp_fw_caps *caps;
570 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
571 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
572 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
573 [WM_ADSP_FW_TX] = { .file = "tx" },
574 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
575 [WM_ADSP_FW_RX] = { .file = "rx" },
576 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
577 [WM_ADSP_FW_CTRL] = {
579 .compr_direction = SND_COMPRESS_CAPTURE,
580 .num_caps = ARRAY_SIZE(ctrl_caps),
582 .voice_trigger = true,
584 [WM_ADSP_FW_ASR] = { .file = "asr" },
585 [WM_ADSP_FW_TRACE] = {
587 .compr_direction = SND_COMPRESS_CAPTURE,
588 .num_caps = ARRAY_SIZE(trace_caps),
591 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
592 [WM_ADSP_FW_MISC] = { .file = "misc" },
595 struct wm_coeff_ctl_ops {
596 int (*xget)(struct snd_kcontrol *kcontrol,
597 struct snd_ctl_elem_value *ucontrol);
598 int (*xput)(struct snd_kcontrol *kcontrol,
599 struct snd_ctl_elem_value *ucontrol);
602 struct wm_coeff_ctl {
605 struct wm_adsp_alg_region alg_region;
606 struct wm_coeff_ctl_ops ops;
608 unsigned int enabled:1;
609 struct list_head list;
614 struct soc_bytes_ext bytes_ext;
619 static const char *wm_adsp_mem_region_name(unsigned int type)
624 case WMFW_HALO_PM_PACKED:
630 case WMFW_HALO_XM_PACKED:
634 case WMFW_HALO_YM_PACKED:
643 #ifdef CONFIG_DEBUG_FS
644 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
646 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
648 kfree(dsp->wmfw_file_name);
649 dsp->wmfw_file_name = tmp;
652 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
654 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
656 kfree(dsp->bin_file_name);
657 dsp->bin_file_name = tmp;
660 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
662 kfree(dsp->wmfw_file_name);
663 kfree(dsp->bin_file_name);
664 dsp->wmfw_file_name = NULL;
665 dsp->bin_file_name = NULL;
668 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
669 char __user *user_buf,
670 size_t count, loff_t *ppos)
672 struct wm_adsp *dsp = file->private_data;
675 mutex_lock(&dsp->pwr_lock);
677 if (!dsp->wmfw_file_name || !dsp->booted)
680 ret = simple_read_from_buffer(user_buf, count, ppos,
682 strlen(dsp->wmfw_file_name));
684 mutex_unlock(&dsp->pwr_lock);
688 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
689 char __user *user_buf,
690 size_t count, loff_t *ppos)
692 struct wm_adsp *dsp = file->private_data;
695 mutex_lock(&dsp->pwr_lock);
697 if (!dsp->bin_file_name || !dsp->booted)
700 ret = simple_read_from_buffer(user_buf, count, ppos,
702 strlen(dsp->bin_file_name));
704 mutex_unlock(&dsp->pwr_lock);
708 static const struct {
710 const struct file_operations fops;
711 } wm_adsp_debugfs_fops[] = {
713 .name = "wmfw_file_name",
716 .read = wm_adsp_debugfs_wmfw_read,
720 .name = "bin_file_name",
723 .read = wm_adsp_debugfs_bin_read,
728 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
729 struct snd_soc_component *component)
731 struct dentry *root = NULL;
734 if (!component->debugfs_root) {
735 adsp_err(dsp, "No codec debugfs root\n");
739 root = debugfs_create_dir(dsp->name, component->debugfs_root);
744 if (!debugfs_create_bool("booted", 0444, root, &dsp->booted))
747 if (!debugfs_create_bool("running", 0444, root, &dsp->running))
750 if (!debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id))
753 if (!debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version))
756 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
757 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
759 &wm_adsp_debugfs_fops[i].fops))
763 dsp->debugfs_root = root;
767 debugfs_remove_recursive(root);
768 adsp_err(dsp, "Failed to create debugfs\n");
771 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
773 wm_adsp_debugfs_clear(dsp);
774 debugfs_remove_recursive(dsp->debugfs_root);
777 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
778 struct snd_soc_component *component)
782 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
786 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
791 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
796 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
801 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
802 struct snd_ctl_elem_value *ucontrol)
804 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
805 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
806 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
808 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
812 EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
814 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
815 struct snd_ctl_elem_value *ucontrol)
817 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
818 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
819 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
822 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
825 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
828 mutex_lock(&dsp[e->shift_l].pwr_lock);
830 if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list))
833 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
835 mutex_unlock(&dsp[e->shift_l].pwr_lock);
839 EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
841 const struct soc_enum wm_adsp_fw_enum[] = {
842 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
843 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
844 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
845 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
846 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
847 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
848 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
850 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
852 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
857 for (i = 0; i < dsp->num_mems; i++)
858 if (dsp->mem[i].type == type)
864 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
869 return mem->base + (offset * 3);
874 return mem->base + (offset * 2);
876 WARN(1, "Unknown memory region type");
881 static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem,
887 return mem->base + (offset * 4);
888 case WMFW_HALO_XM_PACKED:
889 case WMFW_HALO_YM_PACKED:
890 return (mem->base + (offset * 3)) & ~0x3;
891 case WMFW_HALO_PM_PACKED:
892 return mem->base + (offset * 5);
894 WARN(1, "Unknown memory region type");
899 static void wm_adsp_read_fw_status(struct wm_adsp *dsp,
900 int noffs, unsigned int *offs)
905 for (i = 0; i < noffs; ++i) {
906 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]);
908 adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
914 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
916 unsigned int offs[] = {
917 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3,
920 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
922 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
923 offs[0], offs[1], offs[2], offs[3]);
926 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
928 unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 };
930 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
932 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
933 offs[0] & 0xFFFF, offs[0] >> 16,
934 offs[1] & 0xFFFF, offs[1] >> 16);
937 static void wm_halo_show_fw_status(struct wm_adsp *dsp)
939 unsigned int offs[] = {
940 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4,
943 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
945 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
946 offs[0], offs[1], offs[2], offs[3]);
949 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
951 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
954 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
956 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
957 struct wm_adsp *dsp = ctl->dsp;
958 const struct wm_adsp_region *mem;
960 mem = wm_adsp_find_region(dsp, alg_region->type);
962 adsp_err(dsp, "No base for region %x\n",
967 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset);
972 static int wm_coeff_info(struct snd_kcontrol *kctl,
973 struct snd_ctl_elem_info *uinfo)
975 struct soc_bytes_ext *bytes_ext =
976 (struct soc_bytes_ext *)kctl->private_value;
977 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
980 case WMFW_CTL_TYPE_ACKED:
981 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
982 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
983 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
984 uinfo->value.integer.step = 1;
988 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
989 uinfo->count = ctl->len;
996 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
997 unsigned int event_id)
999 struct wm_adsp *dsp = ctl->dsp;
1000 u32 val = cpu_to_be32(event_id);
1004 ret = wm_coeff_base_reg(ctl, ®);
1008 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
1009 event_id, ctl->alg_region.alg,
1010 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
1012 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
1014 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
1019 * Poll for ack, we initially poll at ~1ms intervals for firmwares
1020 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
1021 * to ack instantly so we do the first 1ms delay before reading the
1022 * control to avoid a pointless bus transaction
1024 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
1026 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
1027 usleep_range(1000, 2000);
1031 usleep_range(10000, 20000);
1036 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1038 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
1043 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
1048 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
1049 reg, ctl->alg_region.alg,
1050 wm_adsp_mem_region_name(ctl->alg_region.type),
1056 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
1057 const void *buf, size_t len)
1059 struct wm_adsp *dsp = ctl->dsp;
1064 ret = wm_coeff_base_reg(ctl, ®);
1068 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
1072 ret = regmap_raw_write(dsp->regmap, reg, scratch,
1075 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
1080 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
1087 static int wm_coeff_put(struct snd_kcontrol *kctl,
1088 struct snd_ctl_elem_value *ucontrol)
1090 struct soc_bytes_ext *bytes_ext =
1091 (struct soc_bytes_ext *)kctl->private_value;
1092 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1093 char *p = ucontrol->value.bytes.data;
1096 mutex_lock(&ctl->dsp->pwr_lock);
1098 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1101 memcpy(ctl->cache, p, ctl->len);
1104 if (ctl->enabled && ctl->dsp->running)
1105 ret = wm_coeff_write_control(ctl, p, ctl->len);
1107 mutex_unlock(&ctl->dsp->pwr_lock);
1112 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
1113 const unsigned int __user *bytes, unsigned int size)
1115 struct soc_bytes_ext *bytes_ext =
1116 (struct soc_bytes_ext *)kctl->private_value;
1117 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1120 mutex_lock(&ctl->dsp->pwr_lock);
1122 if (copy_from_user(ctl->cache, bytes, size)) {
1126 if (ctl->enabled && ctl->dsp->running)
1127 ret = wm_coeff_write_control(ctl, ctl->cache, size);
1128 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1132 mutex_unlock(&ctl->dsp->pwr_lock);
1137 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1138 struct snd_ctl_elem_value *ucontrol)
1140 struct soc_bytes_ext *bytes_ext =
1141 (struct soc_bytes_ext *)kctl->private_value;
1142 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1143 unsigned int val = ucontrol->value.integer.value[0];
1147 return 0; /* 0 means no event */
1149 mutex_lock(&ctl->dsp->pwr_lock);
1151 if (ctl->enabled && ctl->dsp->running)
1152 ret = wm_coeff_write_acked_control(ctl, val);
1156 mutex_unlock(&ctl->dsp->pwr_lock);
1161 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
1162 void *buf, size_t len)
1164 struct wm_adsp *dsp = ctl->dsp;
1169 ret = wm_coeff_base_reg(ctl, ®);
1173 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1177 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1179 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1184 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1186 memcpy(buf, scratch, len);
1192 static int wm_coeff_get(struct snd_kcontrol *kctl,
1193 struct snd_ctl_elem_value *ucontrol)
1195 struct soc_bytes_ext *bytes_ext =
1196 (struct soc_bytes_ext *)kctl->private_value;
1197 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1198 char *p = ucontrol->value.bytes.data;
1201 mutex_lock(&ctl->dsp->pwr_lock);
1203 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1204 if (ctl->enabled && ctl->dsp->running)
1205 ret = wm_coeff_read_control(ctl, p, ctl->len);
1209 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1210 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1212 memcpy(p, ctl->cache, ctl->len);
1215 mutex_unlock(&ctl->dsp->pwr_lock);
1220 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1221 unsigned int __user *bytes, unsigned int size)
1223 struct soc_bytes_ext *bytes_ext =
1224 (struct soc_bytes_ext *)kctl->private_value;
1225 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1228 mutex_lock(&ctl->dsp->pwr_lock);
1230 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1231 if (ctl->enabled && ctl->dsp->running)
1232 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1236 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1237 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1240 if (!ret && copy_to_user(bytes, ctl->cache, size))
1243 mutex_unlock(&ctl->dsp->pwr_lock);
1248 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1249 struct snd_ctl_elem_value *ucontrol)
1252 * Although it's not useful to read an acked control, we must satisfy
1253 * user-side assumptions that all controls are readable and that a
1254 * write of the same value should be filtered out (it's valid to send
1255 * the same event number again to the firmware). We therefore return 0,
1256 * meaning "no event" so valid event numbers will always be a change
1258 ucontrol->value.integer.value[0] = 0;
1263 struct wmfw_ctl_work {
1264 struct wm_adsp *dsp;
1265 struct wm_coeff_ctl *ctl;
1266 struct work_struct work;
1269 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1271 unsigned int out, rd, wr, vol;
1273 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1274 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1275 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1276 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1278 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1280 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1281 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1282 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1288 if (in & WMFW_CTL_FLAG_READABLE)
1290 if (in & WMFW_CTL_FLAG_WRITEABLE)
1292 if (in & WMFW_CTL_FLAG_VOLATILE)
1295 out |= rd | wr | vol;
1301 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1303 struct snd_kcontrol_new *kcontrol;
1306 if (!ctl || !ctl->name)
1309 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1313 kcontrol->name = ctl->name;
1314 kcontrol->info = wm_coeff_info;
1315 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1316 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1317 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1318 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1320 switch (ctl->type) {
1321 case WMFW_CTL_TYPE_ACKED:
1322 kcontrol->get = wm_coeff_get_acked;
1323 kcontrol->put = wm_coeff_put_acked;
1326 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1327 ctl->bytes_ext.max = ctl->len;
1328 ctl->bytes_ext.get = wm_coeff_tlv_get;
1329 ctl->bytes_ext.put = wm_coeff_tlv_put;
1331 kcontrol->get = wm_coeff_get;
1332 kcontrol->put = wm_coeff_put;
1337 ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
1350 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1352 struct wm_coeff_ctl *ctl;
1355 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1356 if (!ctl->enabled || ctl->set)
1358 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1362 * For readable controls populate the cache from the DSP memory.
1363 * For non-readable controls the cache was zero-filled when
1364 * created so we don't need to do anything.
1366 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1367 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1376 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1378 struct wm_coeff_ctl *ctl;
1381 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1384 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1385 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
1394 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1397 struct wm_coeff_ctl *ctl;
1400 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1401 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1407 ret = wm_coeff_write_acked_control(ctl, event);
1410 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1411 event, ctl->alg_region.alg, ret);
1415 static void wm_adsp_ctl_work(struct work_struct *work)
1417 struct wmfw_ctl_work *ctl_work = container_of(work,
1418 struct wmfw_ctl_work,
1421 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1425 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1432 static int wm_adsp_create_control(struct wm_adsp *dsp,
1433 const struct wm_adsp_alg_region *alg_region,
1434 unsigned int offset, unsigned int len,
1435 const char *subname, unsigned int subname_len,
1436 unsigned int flags, unsigned int type)
1438 struct wm_coeff_ctl *ctl;
1439 struct wmfw_ctl_work *ctl_work;
1440 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1441 const char *region_name;
1444 region_name = wm_adsp_mem_region_name(alg_region->type);
1446 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1450 switch (dsp->fw_ver) {
1453 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x",
1454 dsp->name, region_name, alg_region->alg);
1455 subname = NULL; /* don't append subname */
1458 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1459 "%s%c %.12s %x", dsp->name, *region_name,
1460 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1463 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1464 "%s %.12s %x", dsp->name,
1465 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1470 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1473 if (dsp->component->name_prefix)
1474 avail -= strlen(dsp->component->name_prefix) + 1;
1476 /* Truncate the subname from the start if it is too long */
1477 if (subname_len > avail)
1478 skip = subname_len - avail;
1480 snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret,
1481 " %.*s", subname_len - skip, subname + skip);
1484 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1485 if (!strcmp(ctl->name, name)) {
1492 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1495 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1496 ctl->alg_region = *alg_region;
1497 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1504 ctl->ops.xget = wm_coeff_get;
1505 ctl->ops.xput = wm_coeff_put;
1510 ctl->offset = offset;
1512 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1518 list_add(&ctl->list, &dsp->ctl_list);
1520 if (flags & WMFW_CTL_FLAG_SYS)
1523 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1529 ctl_work->dsp = dsp;
1530 ctl_work->ctl = ctl;
1531 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1532 schedule_work(&ctl_work->work);
1546 struct wm_coeff_parsed_alg {
1553 struct wm_coeff_parsed_coeff {
1563 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1572 length = le16_to_cpu(*((__le16 *)*pos));
1579 *str = *pos + bytes;
1581 *pos += ((length + bytes) + 3) & ~0x03;
1586 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1592 val = le16_to_cpu(*((__le16 *)*pos));
1595 val = le32_to_cpu(*((__le32 *)*pos));
1606 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1607 struct wm_coeff_parsed_alg *blk)
1609 const struct wmfw_adsp_alg_data *raw;
1611 switch (dsp->fw_ver) {
1614 raw = (const struct wmfw_adsp_alg_data *)*data;
1617 blk->id = le32_to_cpu(raw->id);
1618 blk->name = raw->name;
1619 blk->name_len = strlen(raw->name);
1620 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1623 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1624 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1626 wm_coeff_parse_string(sizeof(u16), data, NULL);
1627 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1631 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1632 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1633 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1636 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1637 struct wm_coeff_parsed_coeff *blk)
1639 const struct wmfw_adsp_coeff_data *raw;
1643 switch (dsp->fw_ver) {
1646 raw = (const struct wmfw_adsp_coeff_data *)*data;
1647 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1649 blk->offset = le16_to_cpu(raw->hdr.offset);
1650 blk->mem_type = le16_to_cpu(raw->hdr.type);
1651 blk->name = raw->name;
1652 blk->name_len = strlen(raw->name);
1653 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1654 blk->flags = le16_to_cpu(raw->flags);
1655 blk->len = le32_to_cpu(raw->len);
1659 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1660 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1661 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1662 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1664 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1665 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1666 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1667 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1668 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1670 *data = *data + sizeof(raw->hdr) + length;
1674 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1675 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1676 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1677 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1678 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1679 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1682 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1683 const struct wm_coeff_parsed_coeff *coeff_blk,
1684 unsigned int f_required,
1685 unsigned int f_illegal)
1687 if ((coeff_blk->flags & f_illegal) ||
1688 ((coeff_blk->flags & f_required) != f_required)) {
1689 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1690 coeff_blk->flags, coeff_blk->ctl_type);
1697 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1698 const struct wmfw_region *region)
1700 struct wm_adsp_alg_region alg_region = {};
1701 struct wm_coeff_parsed_alg alg_blk;
1702 struct wm_coeff_parsed_coeff coeff_blk;
1703 const u8 *data = region->data;
1706 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1707 for (i = 0; i < alg_blk.ncoeff; i++) {
1708 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1710 switch (coeff_blk.ctl_type) {
1711 case SNDRV_CTL_ELEM_TYPE_BYTES:
1713 case WMFW_CTL_TYPE_ACKED:
1714 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1715 continue; /* ignore */
1717 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1718 WMFW_CTL_FLAG_VOLATILE |
1719 WMFW_CTL_FLAG_WRITEABLE |
1720 WMFW_CTL_FLAG_READABLE,
1725 case WMFW_CTL_TYPE_HOSTEVENT:
1726 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1728 WMFW_CTL_FLAG_VOLATILE |
1729 WMFW_CTL_FLAG_WRITEABLE |
1730 WMFW_CTL_FLAG_READABLE,
1735 case WMFW_CTL_TYPE_HOST_BUFFER:
1736 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1738 WMFW_CTL_FLAG_VOLATILE |
1739 WMFW_CTL_FLAG_READABLE,
1745 adsp_err(dsp, "Unknown control type: %d\n",
1746 coeff_blk.ctl_type);
1750 alg_region.type = coeff_blk.mem_type;
1751 alg_region.alg = alg_blk.id;
1753 ret = wm_adsp_create_control(dsp, &alg_region,
1759 coeff_blk.ctl_type);
1761 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1762 coeff_blk.name_len, coeff_blk.name, ret);
1768 static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp,
1769 const char * const file,
1771 const struct firmware *firmware)
1773 const struct wmfw_adsp1_sizes *adsp1_sizes;
1775 adsp1_sizes = (void *)&firmware->data[pos];
1777 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file,
1778 le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm),
1779 le32_to_cpu(adsp1_sizes->zm));
1781 return pos + sizeof(*adsp1_sizes);
1784 static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp,
1785 const char * const file,
1787 const struct firmware *firmware)
1789 const struct wmfw_adsp2_sizes *adsp2_sizes;
1791 adsp2_sizes = (void *)&firmware->data[pos];
1793 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file,
1794 le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym),
1795 le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm));
1797 return pos + sizeof(*adsp2_sizes);
1800 static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version)
1804 adsp_warn(dsp, "Deprecated file format %d\n", version);
1814 static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version)
1824 static int wm_adsp_load(struct wm_adsp *dsp)
1826 LIST_HEAD(buf_list);
1827 const struct firmware *firmware;
1828 struct regmap *regmap = dsp->regmap;
1829 unsigned int pos = 0;
1830 const struct wmfw_header *header;
1831 const struct wmfw_adsp1_sizes *adsp1_sizes;
1832 const struct wmfw_footer *footer;
1833 const struct wmfw_region *region;
1834 const struct wm_adsp_region *mem;
1835 const char *region_name;
1836 char *file, *text = NULL;
1837 struct wm_adsp_buf *buf;
1840 int ret, offset, type;
1842 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1846 snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name,
1847 wm_adsp_fw[dsp->fw].file);
1848 file[PAGE_SIZE - 1] = '\0';
1850 ret = request_firmware(&firmware, file, dsp->dev);
1852 adsp_err(dsp, "Failed to request '%s'\n", file);
1857 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1858 if (pos >= firmware->size) {
1859 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1860 file, firmware->size);
1864 header = (void *)&firmware->data[0];
1866 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1867 adsp_err(dsp, "%s: invalid magic\n", file);
1871 if (!dsp->ops->validate_version(dsp, header->ver)) {
1872 adsp_err(dsp, "%s: unknown file format %d\n",
1877 adsp_info(dsp, "Firmware version: %d\n", header->ver);
1878 dsp->fw_ver = header->ver;
1880 if (header->core != dsp->type) {
1881 adsp_err(dsp, "%s: invalid core %d != %d\n",
1882 file, header->core, dsp->type);
1886 pos = sizeof(*header);
1887 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware);
1889 footer = (void *)&firmware->data[pos];
1890 pos += sizeof(*footer);
1892 if (le32_to_cpu(header->len) != pos) {
1893 adsp_err(dsp, "%s: unexpected header length %d\n",
1894 file, le32_to_cpu(header->len));
1898 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1899 le64_to_cpu(footer->timestamp));
1901 while (pos < firmware->size &&
1902 sizeof(*region) < firmware->size - pos) {
1903 region = (void *)&(firmware->data[pos]);
1904 region_name = "Unknown";
1907 offset = le32_to_cpu(region->offset) & 0xffffff;
1908 type = be32_to_cpu(region->type) & 0xff;
1911 case WMFW_NAME_TEXT:
1912 region_name = "Firmware name";
1913 text = kzalloc(le32_to_cpu(region->len) + 1,
1916 case WMFW_ALGORITHM_DATA:
1917 region_name = "Algorithm";
1918 ret = wm_adsp_parse_coeff(dsp, region);
1922 case WMFW_INFO_TEXT:
1923 region_name = "Information";
1924 text = kzalloc(le32_to_cpu(region->len) + 1,
1928 region_name = "Absolute";
1936 case WMFW_HALO_PM_PACKED:
1937 case WMFW_HALO_XM_PACKED:
1938 case WMFW_HALO_YM_PACKED:
1939 mem = wm_adsp_find_region(dsp, type);
1941 adsp_err(dsp, "No region of type: %x\n", type);
1945 region_name = wm_adsp_mem_region_name(type);
1946 reg = dsp->ops->region_to_reg(mem, offset);
1950 "%s.%d: Unknown region type %x at %d(%x)\n",
1951 file, regions, type, pos, pos);
1955 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1956 regions, le32_to_cpu(region->len), offset,
1959 if (le32_to_cpu(region->len) >
1960 firmware->size - pos - sizeof(*region)) {
1962 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1963 file, regions, region_name,
1964 le32_to_cpu(region->len), firmware->size);
1970 memcpy(text, region->data, le32_to_cpu(region->len));
1971 adsp_info(dsp, "%s: %s\n", file, text);
1977 buf = wm_adsp_buf_alloc(region->data,
1978 le32_to_cpu(region->len),
1981 adsp_err(dsp, "Out of memory\n");
1986 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1987 le32_to_cpu(region->len));
1990 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1992 le32_to_cpu(region->len), offset,
1998 pos += le32_to_cpu(region->len) + sizeof(*region);
2002 ret = regmap_async_complete(regmap);
2004 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2008 if (pos > firmware->size)
2009 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2010 file, regions, pos - firmware->size);
2012 wm_adsp_debugfs_save_wmfwname(dsp, file);
2015 regmap_async_complete(regmap);
2016 wm_adsp_buf_free(&buf_list);
2017 release_firmware(firmware);
2025 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
2026 const struct wm_adsp_alg_region *alg_region)
2028 struct wm_coeff_ctl *ctl;
2030 list_for_each_entry(ctl, &dsp->ctl_list, list) {
2031 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
2032 alg_region->alg == ctl->alg_region.alg &&
2033 alg_region->type == ctl->alg_region.type) {
2034 ctl->alg_region.base = alg_region->base;
2039 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
2040 const struct wm_adsp_region *mem,
2041 unsigned int pos, unsigned int len)
2049 adsp_err(dsp, "No algorithms\n");
2050 return ERR_PTR(-EINVAL);
2053 if (n_algs > 1024) {
2054 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
2055 return ERR_PTR(-EINVAL);
2058 /* Read the terminator first to validate the length */
2059 reg = dsp->ops->region_to_reg(mem, pos + len);
2061 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
2063 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
2065 return ERR_PTR(ret);
2068 if (be32_to_cpu(val) != 0xbedead)
2069 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
2070 reg, be32_to_cpu(val));
2072 /* Convert length from DSP words to bytes */
2075 alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
2077 return ERR_PTR(-ENOMEM);
2079 reg = dsp->ops->region_to_reg(mem, pos);
2081 ret = regmap_raw_read(dsp->regmap, reg, alg, len);
2083 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
2085 return ERR_PTR(ret);
2091 static struct wm_adsp_alg_region *
2092 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
2094 struct wm_adsp_alg_region *alg_region;
2096 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
2097 if (id == alg_region->alg && type == alg_region->type)
2104 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
2105 int type, __be32 id,
2108 struct wm_adsp_alg_region *alg_region;
2110 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
2112 return ERR_PTR(-ENOMEM);
2114 alg_region->type = type;
2115 alg_region->alg = be32_to_cpu(id);
2116 alg_region->base = be32_to_cpu(base);
2118 list_add_tail(&alg_region->list, &dsp->alg_regions);
2120 if (dsp->fw_ver > 0)
2121 wm_adsp_ctl_fixup_base(dsp, alg_region);
2126 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
2128 struct wm_adsp_alg_region *alg_region;
2130 while (!list_empty(&dsp->alg_regions)) {
2131 alg_region = list_first_entry(&dsp->alg_regions,
2132 struct wm_adsp_alg_region,
2134 list_del(&alg_region->list);
2139 static void wmfw_parse_id_header(struct wm_adsp *dsp,
2140 struct wmfw_id_hdr *fw, int nalgs)
2142 dsp->fw_id = be32_to_cpu(fw->id);
2143 dsp->fw_id_version = be32_to_cpu(fw->ver);
2145 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n",
2146 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16,
2147 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2151 static void wmfw_v3_parse_id_header(struct wm_adsp *dsp,
2152 struct wmfw_v3_id_hdr *fw, int nalgs)
2154 dsp->fw_id = be32_to_cpu(fw->id);
2155 dsp->fw_id_version = be32_to_cpu(fw->ver);
2156 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id);
2158 adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n",
2159 dsp->fw_id, dsp->fw_vendor_id,
2160 (dsp->fw_id_version & 0xff0000) >> 16,
2161 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2165 static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions,
2166 int *type, __be32 *base)
2168 struct wm_adsp_alg_region *alg_region;
2171 for (i = 0; i < nregions; i++) {
2172 alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]);
2173 if (IS_ERR(alg_region))
2174 return PTR_ERR(alg_region);
2180 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
2182 struct wmfw_adsp1_id_hdr adsp1_id;
2183 struct wmfw_adsp1_alg_hdr *adsp1_alg;
2184 struct wm_adsp_alg_region *alg_region;
2185 const struct wm_adsp_region *mem;
2186 unsigned int pos, len;
2190 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
2194 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2197 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2202 n_algs = be32_to_cpu(adsp1_id.n_algs);
2204 wmfw_parse_id_header(dsp, &adsp1_id.fw, n_algs);
2206 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2207 adsp1_id.fw.id, adsp1_id.zm);
2208 if (IS_ERR(alg_region))
2209 return PTR_ERR(alg_region);
2211 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2212 adsp1_id.fw.id, adsp1_id.dm);
2213 if (IS_ERR(alg_region))
2214 return PTR_ERR(alg_region);
2216 /* Calculate offset and length in DSP words */
2217 pos = sizeof(adsp1_id) / sizeof(u32);
2218 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
2220 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2221 if (IS_ERR(adsp1_alg))
2222 return PTR_ERR(adsp1_alg);
2224 for (i = 0; i < n_algs; i++) {
2225 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2226 i, be32_to_cpu(adsp1_alg[i].alg.id),
2227 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2228 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2229 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2230 be32_to_cpu(adsp1_alg[i].dm),
2231 be32_to_cpu(adsp1_alg[i].zm));
2233 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2234 adsp1_alg[i].alg.id,
2236 if (IS_ERR(alg_region)) {
2237 ret = PTR_ERR(alg_region);
2240 if (dsp->fw_ver == 0) {
2241 if (i + 1 < n_algs) {
2242 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2243 len -= be32_to_cpu(adsp1_alg[i].dm);
2245 wm_adsp_create_control(dsp, alg_region, 0,
2247 SNDRV_CTL_ELEM_TYPE_BYTES);
2249 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2250 be32_to_cpu(adsp1_alg[i].alg.id));
2254 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2255 adsp1_alg[i].alg.id,
2257 if (IS_ERR(alg_region)) {
2258 ret = PTR_ERR(alg_region);
2261 if (dsp->fw_ver == 0) {
2262 if (i + 1 < n_algs) {
2263 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2264 len -= be32_to_cpu(adsp1_alg[i].zm);
2266 wm_adsp_create_control(dsp, alg_region, 0,
2268 SNDRV_CTL_ELEM_TYPE_BYTES);
2270 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2271 be32_to_cpu(adsp1_alg[i].alg.id));
2281 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2283 struct wmfw_adsp2_id_hdr adsp2_id;
2284 struct wmfw_adsp2_alg_hdr *adsp2_alg;
2285 struct wm_adsp_alg_region *alg_region;
2286 const struct wm_adsp_region *mem;
2287 unsigned int pos, len;
2291 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2295 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2298 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2303 n_algs = be32_to_cpu(adsp2_id.n_algs);
2305 wmfw_parse_id_header(dsp, &adsp2_id.fw, n_algs);
2307 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2308 adsp2_id.fw.id, adsp2_id.xm);
2309 if (IS_ERR(alg_region))
2310 return PTR_ERR(alg_region);
2312 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2313 adsp2_id.fw.id, adsp2_id.ym);
2314 if (IS_ERR(alg_region))
2315 return PTR_ERR(alg_region);
2317 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2318 adsp2_id.fw.id, adsp2_id.zm);
2319 if (IS_ERR(alg_region))
2320 return PTR_ERR(alg_region);
2322 /* Calculate offset and length in DSP words */
2323 pos = sizeof(adsp2_id) / sizeof(u32);
2324 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
2326 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2327 if (IS_ERR(adsp2_alg))
2328 return PTR_ERR(adsp2_alg);
2330 for (i = 0; i < n_algs; i++) {
2332 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2333 i, be32_to_cpu(adsp2_alg[i].alg.id),
2334 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2335 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2336 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2337 be32_to_cpu(adsp2_alg[i].xm),
2338 be32_to_cpu(adsp2_alg[i].ym),
2339 be32_to_cpu(adsp2_alg[i].zm));
2341 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2342 adsp2_alg[i].alg.id,
2344 if (IS_ERR(alg_region)) {
2345 ret = PTR_ERR(alg_region);
2348 if (dsp->fw_ver == 0) {
2349 if (i + 1 < n_algs) {
2350 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2351 len -= be32_to_cpu(adsp2_alg[i].xm);
2353 wm_adsp_create_control(dsp, alg_region, 0,
2355 SNDRV_CTL_ELEM_TYPE_BYTES);
2357 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2358 be32_to_cpu(adsp2_alg[i].alg.id));
2362 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2363 adsp2_alg[i].alg.id,
2365 if (IS_ERR(alg_region)) {
2366 ret = PTR_ERR(alg_region);
2369 if (dsp->fw_ver == 0) {
2370 if (i + 1 < n_algs) {
2371 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2372 len -= be32_to_cpu(adsp2_alg[i].ym);
2374 wm_adsp_create_control(dsp, alg_region, 0,
2376 SNDRV_CTL_ELEM_TYPE_BYTES);
2378 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2379 be32_to_cpu(adsp2_alg[i].alg.id));
2383 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2384 adsp2_alg[i].alg.id,
2386 if (IS_ERR(alg_region)) {
2387 ret = PTR_ERR(alg_region);
2390 if (dsp->fw_ver == 0) {
2391 if (i + 1 < n_algs) {
2392 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2393 len -= be32_to_cpu(adsp2_alg[i].zm);
2395 wm_adsp_create_control(dsp, alg_region, 0,
2397 SNDRV_CTL_ELEM_TYPE_BYTES);
2399 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2400 be32_to_cpu(adsp2_alg[i].alg.id));
2410 static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id,
2411 __be32 xm_base, __be32 ym_base)
2414 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED,
2415 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED
2417 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base };
2419 return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases);
2422 static int wm_halo_setup_algs(struct wm_adsp *dsp)
2424 struct wmfw_halo_id_hdr halo_id;
2425 struct wmfw_halo_alg_hdr *halo_alg;
2426 const struct wm_adsp_region *mem;
2427 unsigned int pos, len;
2431 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2435 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id,
2438 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2443 n_algs = be32_to_cpu(halo_id.n_algs);
2445 wmfw_v3_parse_id_header(dsp, &halo_id.fw, n_algs);
2447 ret = wm_halo_create_regions(dsp, halo_id.fw.id,
2448 halo_id.xm_base, halo_id.ym_base);
2452 /* Calculate offset and length in DSP words */
2453 pos = sizeof(halo_id) / sizeof(u32);
2454 len = (sizeof(*halo_alg) * n_algs) / sizeof(u32);
2456 halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2457 if (IS_ERR(halo_alg))
2458 return PTR_ERR(halo_alg);
2460 for (i = 0; i < n_algs; i++) {
2462 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n",
2463 i, be32_to_cpu(halo_alg[i].alg.id),
2464 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16,
2465 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8,
2466 be32_to_cpu(halo_alg[i].alg.ver) & 0xff,
2467 be32_to_cpu(halo_alg[i].xm_base),
2468 be32_to_cpu(halo_alg[i].ym_base));
2470 ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id,
2471 halo_alg[i].xm_base,
2472 halo_alg[i].ym_base);
2482 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2484 LIST_HEAD(buf_list);
2485 struct regmap *regmap = dsp->regmap;
2486 struct wmfw_coeff_hdr *hdr;
2487 struct wmfw_coeff_item *blk;
2488 const struct firmware *firmware;
2489 const struct wm_adsp_region *mem;
2490 struct wm_adsp_alg_region *alg_region;
2491 const char *region_name;
2492 int ret, pos, blocks, type, offset, reg;
2494 struct wm_adsp_buf *buf;
2496 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2500 snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name,
2501 wm_adsp_fw[dsp->fw].file);
2502 file[PAGE_SIZE - 1] = '\0';
2504 ret = request_firmware(&firmware, file, dsp->dev);
2506 adsp_warn(dsp, "Failed to request '%s'\n", file);
2512 if (sizeof(*hdr) >= firmware->size) {
2513 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2514 file, firmware->size);
2518 hdr = (void *)&firmware->data[0];
2519 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2520 adsp_err(dsp, "%s: invalid magic\n", file);
2524 switch (be32_to_cpu(hdr->rev) & 0xff) {
2528 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2529 file, be32_to_cpu(hdr->rev) & 0xff);
2534 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2535 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2536 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2537 le32_to_cpu(hdr->ver) & 0xff);
2539 pos = le32_to_cpu(hdr->len);
2542 while (pos < firmware->size &&
2543 sizeof(*blk) < firmware->size - pos) {
2544 blk = (void *)(&firmware->data[pos]);
2546 type = le16_to_cpu(blk->type);
2547 offset = le16_to_cpu(blk->offset);
2549 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2550 file, blocks, le32_to_cpu(blk->id),
2551 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2552 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2553 le32_to_cpu(blk->ver) & 0xff);
2554 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2555 file, blocks, le32_to_cpu(blk->len), offset, type);
2558 region_name = "Unknown";
2560 case (WMFW_NAME_TEXT << 8):
2561 case (WMFW_INFO_TEXT << 8):
2563 case (WMFW_ABSOLUTE << 8):
2565 * Old files may use this for global
2568 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2570 region_name = "global coefficients";
2571 mem = wm_adsp_find_region(dsp, type);
2573 adsp_err(dsp, "No ZM\n");
2576 reg = dsp->ops->region_to_reg(mem, 0);
2579 region_name = "register";
2588 case WMFW_HALO_XM_PACKED:
2589 case WMFW_HALO_YM_PACKED:
2590 case WMFW_HALO_PM_PACKED:
2591 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2592 file, blocks, le32_to_cpu(blk->len),
2593 type, le32_to_cpu(blk->id));
2595 mem = wm_adsp_find_region(dsp, type);
2597 adsp_err(dsp, "No base for region %x\n", type);
2601 alg_region = wm_adsp_find_alg_region(dsp, type,
2602 le32_to_cpu(blk->id));
2604 reg = alg_region->base;
2605 reg = dsp->ops->region_to_reg(mem, reg);
2608 adsp_err(dsp, "No %x for algorithm %x\n",
2609 type, le32_to_cpu(blk->id));
2614 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2615 file, blocks, type, pos);
2620 if (le32_to_cpu(blk->len) >
2621 firmware->size - pos - sizeof(*blk)) {
2623 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2624 file, blocks, region_name,
2625 le32_to_cpu(blk->len),
2631 buf = wm_adsp_buf_alloc(blk->data,
2632 le32_to_cpu(blk->len),
2635 adsp_err(dsp, "Out of memory\n");
2640 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2641 file, blocks, le32_to_cpu(blk->len),
2643 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2644 le32_to_cpu(blk->len));
2647 "%s.%d: Failed to write to %x in %s: %d\n",
2648 file, blocks, reg, region_name, ret);
2652 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2656 ret = regmap_async_complete(regmap);
2658 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2660 if (pos > firmware->size)
2661 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2662 file, blocks, pos - firmware->size);
2664 wm_adsp_debugfs_save_binname(dsp, file);
2667 regmap_async_complete(regmap);
2668 release_firmware(firmware);
2669 wm_adsp_buf_free(&buf_list);
2675 static int wm_adsp_create_name(struct wm_adsp *dsp)
2680 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2686 if (!dsp->fwf_name) {
2687 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL);
2692 for (; *p != 0; ++p)
2699 static int wm_adsp_common_init(struct wm_adsp *dsp)
2703 ret = wm_adsp_create_name(dsp);
2707 INIT_LIST_HEAD(&dsp->alg_regions);
2708 INIT_LIST_HEAD(&dsp->ctl_list);
2709 INIT_LIST_HEAD(&dsp->compr_list);
2710 INIT_LIST_HEAD(&dsp->buffer_list);
2712 mutex_init(&dsp->pwr_lock);
2717 int wm_adsp1_init(struct wm_adsp *dsp)
2719 dsp->ops = &wm_adsp1_ops;
2721 return wm_adsp_common_init(dsp);
2723 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2725 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2726 struct snd_kcontrol *kcontrol,
2729 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2730 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2731 struct wm_adsp *dsp = &dsps[w->shift];
2732 struct wm_coeff_ctl *ctl;
2736 dsp->component = component;
2738 mutex_lock(&dsp->pwr_lock);
2741 case SND_SOC_DAPM_POST_PMU:
2742 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2743 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2746 * For simplicity set the DSP clock rate to be the
2747 * SYSCLK rate rather than making it configurable.
2749 if (dsp->sysclk_reg) {
2750 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2752 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2757 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2759 ret = regmap_update_bits(dsp->regmap,
2760 dsp->base + ADSP1_CONTROL_31,
2761 ADSP1_CLK_SEL_MASK, val);
2763 adsp_err(dsp, "Failed to set clock rate: %d\n",
2769 ret = wm_adsp_load(dsp);
2773 ret = wm_adsp1_setup_algs(dsp);
2777 ret = wm_adsp_load_coeff(dsp);
2781 /* Initialize caches for enabled and unset controls */
2782 ret = wm_coeff_init_control_caches(dsp);
2786 /* Sync set controls */
2787 ret = wm_coeff_sync_controls(dsp);
2793 /* Start the core running */
2794 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2795 ADSP1_CORE_ENA | ADSP1_START,
2796 ADSP1_CORE_ENA | ADSP1_START);
2798 dsp->running = true;
2801 case SND_SOC_DAPM_PRE_PMD:
2802 dsp->running = false;
2803 dsp->booted = false;
2806 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2807 ADSP1_CORE_ENA | ADSP1_START, 0);
2809 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2810 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2812 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2815 list_for_each_entry(ctl, &dsp->ctl_list, list)
2819 wm_adsp_free_alg_regions(dsp);
2826 mutex_unlock(&dsp->pwr_lock);
2831 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2834 mutex_unlock(&dsp->pwr_lock);
2838 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2840 static int wm_adsp2v2_enable_core(struct wm_adsp *dsp)
2845 /* Wait for the RAM to start, should be near instantaneous */
2846 for (count = 0; count < 10; ++count) {
2847 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2851 if (val & ADSP2_RAM_RDY)
2854 usleep_range(250, 500);
2857 if (!(val & ADSP2_RAM_RDY)) {
2858 adsp_err(dsp, "Failed to start DSP RAM\n");
2862 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2867 static int wm_adsp2_enable_core(struct wm_adsp *dsp)
2871 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2872 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2876 return wm_adsp2v2_enable_core(dsp);
2879 static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
2881 struct regmap *regmap = dsp->regmap;
2882 unsigned int code0, code1, lock_reg;
2884 if (!(lock_regions & WM_ADSP2_REGION_ALL))
2887 lock_regions &= WM_ADSP2_REGION_ALL;
2888 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
2890 while (lock_regions) {
2892 if (lock_regions & BIT(0)) {
2893 code0 = ADSP2_LOCK_CODE_0;
2894 code1 = ADSP2_LOCK_CODE_1;
2896 if (lock_regions & BIT(1)) {
2897 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
2898 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
2900 regmap_write(regmap, lock_reg, code0);
2901 regmap_write(regmap, lock_reg, code1);
2909 static int wm_adsp2_enable_memory(struct wm_adsp *dsp)
2911 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2912 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2915 static void wm_adsp2_disable_memory(struct wm_adsp *dsp)
2917 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2921 static void wm_adsp2_disable_core(struct wm_adsp *dsp)
2923 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2924 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2925 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2927 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2931 static void wm_adsp2v2_disable_core(struct wm_adsp *dsp)
2933 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2934 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2935 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2938 static void wm_adsp_boot_work(struct work_struct *work)
2940 struct wm_adsp *dsp = container_of(work,
2945 mutex_lock(&dsp->pwr_lock);
2947 if (dsp->ops->enable_memory) {
2948 ret = dsp->ops->enable_memory(dsp);
2953 if (dsp->ops->enable_core) {
2954 ret = dsp->ops->enable_core(dsp);
2959 ret = wm_adsp_load(dsp);
2963 ret = dsp->ops->setup_algs(dsp);
2967 ret = wm_adsp_load_coeff(dsp);
2971 /* Initialize caches for enabled and unset controls */
2972 ret = wm_coeff_init_control_caches(dsp);
2976 if (dsp->ops->disable_core)
2977 dsp->ops->disable_core(dsp);
2981 mutex_unlock(&dsp->pwr_lock);
2986 if (dsp->ops->disable_core)
2987 dsp->ops->disable_core(dsp);
2989 if (dsp->ops->disable_memory)
2990 dsp->ops->disable_memory(dsp);
2992 mutex_unlock(&dsp->pwr_lock);
2995 static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions)
2997 struct reg_sequence config[] = {
2998 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 },
2999 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA },
3000 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF },
3001 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF },
3002 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions },
3003 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions },
3004 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions },
3005 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF },
3006 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF },
3007 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions },
3008 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions },
3009 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions },
3010 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF },
3011 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF },
3012 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions },
3013 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions },
3014 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions },
3015 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF },
3016 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF },
3017 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions },
3018 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions },
3019 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions },
3020 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 },
3023 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config));
3026 int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq)
3028 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3029 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3030 struct wm_adsp *dsp = &dsps[w->shift];
3033 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING,
3035 freq << ADSP2_CLK_SEL_SHIFT);
3037 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
3041 EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk);
3043 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
3044 struct snd_ctl_elem_value *ucontrol)
3046 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3047 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3048 struct soc_mixer_control *mc =
3049 (struct soc_mixer_control *)kcontrol->private_value;
3050 struct wm_adsp *dsp = &dsps[mc->shift - 1];
3052 ucontrol->value.integer.value[0] = dsp->preloaded;
3056 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
3058 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
3059 struct snd_ctl_elem_value *ucontrol)
3061 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3062 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3063 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3064 struct soc_mixer_control *mc =
3065 (struct soc_mixer_control *)kcontrol->private_value;
3066 struct wm_adsp *dsp = &dsps[mc->shift - 1];
3069 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3071 dsp->preloaded = ucontrol->value.integer.value[0];
3073 if (ucontrol->value.integer.value[0])
3074 snd_soc_component_force_enable_pin(component, preload);
3076 snd_soc_component_disable_pin(component, preload);
3078 snd_soc_dapm_sync(dapm);
3080 flush_work(&dsp->boot_work);
3084 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
3086 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
3088 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
3089 ADSP2_WDT_ENA_MASK, 0);
3092 static void wm_halo_stop_watchdog(struct wm_adsp *dsp)
3094 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL,
3095 HALO_WDT_EN_MASK, 0);
3098 int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
3099 struct snd_kcontrol *kcontrol, int event)
3101 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3102 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3103 struct wm_adsp *dsp = &dsps[w->shift];
3104 struct wm_coeff_ctl *ctl;
3107 case SND_SOC_DAPM_PRE_PMU:
3108 queue_work(system_unbound_wq, &dsp->boot_work);
3110 case SND_SOC_DAPM_PRE_PMD:
3111 mutex_lock(&dsp->pwr_lock);
3113 wm_adsp_debugfs_clear(dsp);
3116 dsp->fw_id_version = 0;
3118 dsp->booted = false;
3120 if (dsp->ops->disable_memory)
3121 dsp->ops->disable_memory(dsp);
3123 list_for_each_entry(ctl, &dsp->ctl_list, list)
3126 wm_adsp_free_alg_regions(dsp);
3128 mutex_unlock(&dsp->pwr_lock);
3130 adsp_dbg(dsp, "Shutdown complete\n");
3138 EXPORT_SYMBOL_GPL(wm_adsp_early_event);
3140 static int wm_adsp2_start_core(struct wm_adsp *dsp)
3142 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3143 ADSP2_CORE_ENA | ADSP2_START,
3144 ADSP2_CORE_ENA | ADSP2_START);
3147 static void wm_adsp2_stop_core(struct wm_adsp *dsp)
3149 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3150 ADSP2_CORE_ENA | ADSP2_START, 0);
3153 int wm_adsp_event(struct snd_soc_dapm_widget *w,
3154 struct snd_kcontrol *kcontrol, int event)
3156 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3157 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3158 struct wm_adsp *dsp = &dsps[w->shift];
3162 case SND_SOC_DAPM_POST_PMU:
3163 flush_work(&dsp->boot_work);
3165 mutex_lock(&dsp->pwr_lock);
3172 if (dsp->ops->enable_core) {
3173 ret = dsp->ops->enable_core(dsp);
3178 /* Sync set controls */
3179 ret = wm_coeff_sync_controls(dsp);
3183 if (dsp->ops->lock_memory) {
3184 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions);
3186 adsp_err(dsp, "Error configuring MPU: %d\n",
3192 if (dsp->ops->start_core) {
3193 ret = dsp->ops->start_core(dsp);
3198 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
3199 ret = wm_adsp_buffer_init(dsp);
3204 dsp->running = true;
3206 mutex_unlock(&dsp->pwr_lock);
3209 case SND_SOC_DAPM_PRE_PMD:
3210 /* Tell the firmware to cleanup */
3211 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
3213 if (dsp->ops->stop_watchdog)
3214 dsp->ops->stop_watchdog(dsp);
3216 /* Log firmware state, it can be useful for analysis */
3217 if (dsp->ops->show_fw_status)
3218 dsp->ops->show_fw_status(dsp);
3220 mutex_lock(&dsp->pwr_lock);
3222 dsp->running = false;
3224 if (dsp->ops->stop_core)
3225 dsp->ops->stop_core(dsp);
3226 if (dsp->ops->disable_core)
3227 dsp->ops->disable_core(dsp);
3229 if (wm_adsp_fw[dsp->fw].num_caps != 0)
3230 wm_adsp_buffer_free(dsp);
3232 dsp->fatal_error = false;
3234 mutex_unlock(&dsp->pwr_lock);
3236 adsp_dbg(dsp, "Execution stopped\n");
3245 if (dsp->ops->stop_core)
3246 dsp->ops->stop_core(dsp);
3247 if (dsp->ops->disable_core)
3248 dsp->ops->disable_core(dsp);
3249 mutex_unlock(&dsp->pwr_lock);
3252 EXPORT_SYMBOL_GPL(wm_adsp_event);
3254 static int wm_halo_start_core(struct wm_adsp *dsp)
3256 return regmap_update_bits(dsp->regmap,
3257 dsp->base + HALO_CCM_CORE_CONTROL,
3258 HALO_CORE_EN, HALO_CORE_EN);
3261 static void wm_halo_stop_core(struct wm_adsp *dsp)
3263 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
3266 /* reset halo core with CORE_SOFT_RESET */
3267 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET,
3268 HALO_CORE_SOFT_RESET_MASK, 1);
3271 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
3275 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3276 snd_soc_component_disable_pin(component, preload);
3278 wm_adsp2_init_debugfs(dsp, component);
3280 dsp->component = component;
3284 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
3286 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
3288 wm_adsp2_cleanup_debugfs(dsp);
3292 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
3294 int wm_adsp2_init(struct wm_adsp *dsp)
3298 ret = wm_adsp_common_init(dsp);
3305 * Disable the DSP memory by default when in reset for a small
3308 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3312 "Failed to clear memory retention: %d\n", ret);
3316 dsp->ops = &wm_adsp2_ops[0];
3319 dsp->ops = &wm_adsp2_ops[1];
3322 dsp->ops = &wm_adsp2_ops[2];
3326 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3330 EXPORT_SYMBOL_GPL(wm_adsp2_init);
3332 int wm_halo_init(struct wm_adsp *dsp)
3336 ret = wm_adsp_common_init(dsp);
3340 dsp->ops = &wm_halo_ops;
3342 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3346 EXPORT_SYMBOL_GPL(wm_halo_init);
3348 void wm_adsp2_remove(struct wm_adsp *dsp)
3350 struct wm_coeff_ctl *ctl;
3352 while (!list_empty(&dsp->ctl_list)) {
3353 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
3355 list_del(&ctl->list);
3356 wm_adsp_free_ctl_blk(ctl);
3359 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
3361 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
3363 return compr->buf != NULL;
3366 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
3368 struct wm_adsp_compr_buf *buf = NULL, *tmp;
3370 if (compr->dsp->fatal_error)
3373 list_for_each_entry(tmp, &compr->dsp->buffer_list, list) {
3374 if (!tmp->name || !strcmp(compr->name, tmp->name)) {
3389 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
3394 /* Wake the poll so it can see buffer is no longer attached */
3396 snd_compr_fragment_elapsed(compr->stream);
3398 if (wm_adsp_compr_attached(compr)) {
3399 compr->buf->compr = NULL;
3404 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
3406 struct wm_adsp_compr *compr, *tmp;
3407 struct snd_soc_pcm_runtime *rtd = stream->private_data;
3410 mutex_lock(&dsp->pwr_lock);
3412 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
3413 adsp_err(dsp, "%s: Firmware does not support compressed API\n",
3414 rtd->codec_dai->name);
3419 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
3420 adsp_err(dsp, "%s: Firmware does not support stream direction\n",
3421 rtd->codec_dai->name);
3426 list_for_each_entry(tmp, &dsp->compr_list, list) {
3427 if (!strcmp(tmp->name, rtd->codec_dai->name)) {
3428 adsp_err(dsp, "%s: Only a single stream supported per dai\n",
3429 rtd->codec_dai->name);
3435 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3442 compr->stream = stream;
3443 compr->name = rtd->codec_dai->name;
3445 list_add_tail(&compr->list, &dsp->compr_list);
3447 stream->runtime->private_data = compr;
3450 mutex_unlock(&dsp->pwr_lock);
3454 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3456 int wm_adsp_compr_free(struct snd_compr_stream *stream)
3458 struct wm_adsp_compr *compr = stream->runtime->private_data;
3459 struct wm_adsp *dsp = compr->dsp;
3461 mutex_lock(&dsp->pwr_lock);
3463 wm_adsp_compr_detach(compr);
3464 list_del(&compr->list);
3466 kfree(compr->raw_buf);
3469 mutex_unlock(&dsp->pwr_lock);
3473 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3475 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3476 struct snd_compr_params *params)
3478 struct wm_adsp_compr *compr = stream->runtime->private_data;
3479 struct wm_adsp *dsp = compr->dsp;
3480 const struct wm_adsp_fw_caps *caps;
3481 const struct snd_codec_desc *desc;
3484 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3485 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3486 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3487 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3488 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3489 compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n",
3490 params->buffer.fragment_size,
3491 params->buffer.fragments);
3496 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3497 caps = &wm_adsp_fw[dsp->fw].caps[i];
3500 if (caps->id != params->codec.id)
3503 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3504 if (desc->max_ch < params->codec.ch_out)
3507 if (desc->max_ch < params->codec.ch_in)
3511 if (!(desc->formats & (1 << params->codec.format)))
3514 for (j = 0; j < desc->num_sample_rates; ++j)
3515 if (desc->sample_rates[j] == params->codec.sample_rate)
3519 compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3520 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3521 params->codec.sample_rate, params->codec.format);
3525 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3527 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3530 int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3531 struct snd_compr_params *params)
3533 struct wm_adsp_compr *compr = stream->runtime->private_data;
3537 ret = wm_adsp_compr_check_params(stream, params);
3541 compr->size = params->buffer;
3543 compr_dbg(compr, "fragment_size=%d fragments=%d\n",
3544 compr->size.fragment_size, compr->size.fragments);
3546 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3547 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3548 if (!compr->raw_buf)
3551 compr->sample_rate = params->codec.sample_rate;
3555 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3557 int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3558 struct snd_compr_caps *caps)
3560 struct wm_adsp_compr *compr = stream->runtime->private_data;
3561 int fw = compr->dsp->fw;
3564 if (wm_adsp_fw[fw].caps) {
3565 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3566 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3568 caps->num_codecs = i;
3569 caps->direction = wm_adsp_fw[fw].compr_direction;
3571 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3572 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3573 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3574 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3579 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3581 static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3582 unsigned int mem_addr,
3583 unsigned int num_words, u32 *data)
3585 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3586 unsigned int i, reg;
3592 reg = dsp->ops->region_to_reg(mem, mem_addr);
3594 ret = regmap_raw_read(dsp->regmap, reg, data,
3595 sizeof(*data) * num_words);
3599 for (i = 0; i < num_words; ++i)
3600 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3605 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3606 unsigned int mem_addr, u32 *data)
3608 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3611 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3612 unsigned int mem_addr, u32 data)
3614 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3620 reg = dsp->ops->region_to_reg(mem, mem_addr);
3622 data = cpu_to_be32(data & 0x00ffffffu);
3624 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3627 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3628 unsigned int field_offset, u32 *data)
3630 return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type,
3631 buf->host_buf_ptr + field_offset, data);
3634 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3635 unsigned int field_offset, u32 data)
3637 return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type,
3638 buf->host_buf_ptr + field_offset, data);
3641 static void wm_adsp_remove_padding(u32 *buf, int nwords, int data_word_size)
3643 u8 *pack_in = (u8 *)buf;
3644 u8 *pack_out = (u8 *)buf;
3647 /* Remove the padding bytes from the data read from the DSP */
3648 for (i = 0; i < nwords; i++) {
3649 for (j = 0; j < data_word_size; j++)
3650 *pack_out++ = *pack_in++;
3652 pack_in += sizeof(*buf) - data_word_size;
3656 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3658 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3659 struct wm_adsp_buffer_region *region;
3663 buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions),
3668 for (i = 0; i < caps->num_regions; ++i) {
3669 region = &buf->regions[i];
3671 region->offset = offset;
3672 region->mem_type = caps->region_defs[i].mem_type;
3674 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3675 ®ion->base_addr);
3679 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3684 region->cumulative_size = offset;
3687 "region=%d type=%d base=%08x off=%08x size=%08x\n",
3688 i, region->mem_type, region->base_addr,
3689 region->offset, region->cumulative_size);
3695 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3697 buf->irq_count = 0xFFFFFFFF;
3698 buf->read_index = -1;
3702 static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp)
3704 struct wm_adsp_compr_buf *buf;
3706 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3712 wm_adsp_buffer_clear(buf);
3714 list_add_tail(&buf->list, &dsp->buffer_list);
3719 static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp)
3721 struct wm_adsp_alg_region *alg_region;
3722 struct wm_adsp_compr_buf *buf;
3723 u32 xmalg, addr, magic;
3726 buf = wm_adsp_buffer_alloc(dsp);
3730 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3731 xmalg = dsp->ops->sys_config_size / sizeof(__be32);
3733 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3734 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3738 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3741 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3742 for (i = 0; i < 5; ++i) {
3743 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3744 &buf->host_buf_ptr);
3748 if (buf->host_buf_ptr)
3751 usleep_range(1000, 2000);
3754 if (!buf->host_buf_ptr)
3757 buf->host_buf_mem_type = WMFW_ADSP2_XM;
3759 ret = wm_adsp_buffer_populate(buf);
3763 compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr);
3768 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl)
3770 struct wm_adsp_host_buf_coeff_v1 coeff_v1;
3771 struct wm_adsp_compr_buf *buf;
3772 unsigned int val, reg;
3775 ret = wm_coeff_base_reg(ctl, ®);
3779 for (i = 0; i < 5; ++i) {
3780 ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val));
3787 usleep_range(1000, 2000);
3791 adsp_err(ctl->dsp, "Failed to acquire host buffer\n");
3795 buf = wm_adsp_buffer_alloc(ctl->dsp);
3799 buf->host_buf_mem_type = ctl->alg_region.type;
3800 buf->host_buf_ptr = be32_to_cpu(val);
3802 ret = wm_adsp_buffer_populate(buf);
3807 * v0 host_buffer coefficients didn't have versioning, so if the
3808 * control is one word, assume version 0.
3810 if (ctl->len == 4) {
3811 compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3815 ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1,
3820 coeff_v1.versions = be32_to_cpu(coeff_v1.versions);
3821 val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK;
3822 val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT;
3824 if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) {
3826 "Host buffer coeff ver %u > supported version %u\n",
3827 val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER);
3831 for (i = 0; i < ARRAY_SIZE(coeff_v1.name); i++)
3832 coeff_v1.name[i] = be32_to_cpu(coeff_v1.name[i]);
3834 wm_adsp_remove_padding((u32 *)&coeff_v1.name,
3835 ARRAY_SIZE(coeff_v1.name),
3836 WM_ADSP_DATA_WORD_SIZE);
3838 buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part,
3839 (char *)&coeff_v1.name);
3841 compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n",
3842 buf->host_buf_ptr, val);
3847 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3849 struct wm_coeff_ctl *ctl;
3852 list_for_each_entry(ctl, &dsp->ctl_list, list) {
3853 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3859 ret = wm_adsp_buffer_parse_coeff(ctl);
3861 adsp_err(dsp, "Failed to parse coeff: %d\n", ret);
3863 } else if (ret == 0) {
3864 /* Only one buffer supported for version 0 */
3869 if (list_empty(&dsp->buffer_list)) {
3870 /* Fall back to legacy support */
3871 ret = wm_adsp_buffer_parse_legacy(dsp);
3873 adsp_err(dsp, "Failed to parse legacy: %d\n", ret);
3881 wm_adsp_buffer_free(dsp);
3885 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3887 struct wm_adsp_compr_buf *buf, *tmp;
3889 list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) {
3890 wm_adsp_compr_detach(buf->compr);
3893 kfree(buf->regions);
3894 list_del(&buf->list);
3901 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3905 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3907 compr_err(buf, "Failed to check buffer error: %d\n", ret);
3910 if (buf->error != 0) {
3911 compr_err(buf, "Buffer error occurred: %d\n", buf->error);
3918 int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3920 struct wm_adsp_compr *compr = stream->runtime->private_data;
3921 struct wm_adsp *dsp = compr->dsp;
3924 compr_dbg(compr, "Trigger: %d\n", cmd);
3926 mutex_lock(&dsp->pwr_lock);
3929 case SNDRV_PCM_TRIGGER_START:
3930 if (!wm_adsp_compr_attached(compr)) {
3931 ret = wm_adsp_compr_attach(compr);
3933 compr_err(compr, "Failed to link buffer and stream: %d\n",
3939 ret = wm_adsp_buffer_get_error(compr->buf);
3943 /* Trigger the IRQ at one fragment of data */
3944 ret = wm_adsp_buffer_write(compr->buf,
3945 HOST_BUFFER_FIELD(high_water_mark),
3946 wm_adsp_compr_frag_words(compr));
3948 compr_err(compr, "Failed to set high water mark: %d\n",
3953 case SNDRV_PCM_TRIGGER_STOP:
3954 if (wm_adsp_compr_attached(compr))
3955 wm_adsp_buffer_clear(compr->buf);
3962 mutex_unlock(&dsp->pwr_lock);
3966 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3968 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3970 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3972 return buf->regions[last_region].cumulative_size;
3975 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3977 u32 next_read_index, next_write_index;
3978 int write_index, read_index, avail;
3981 /* Only sync read index if we haven't already read a valid index */
3982 if (buf->read_index < 0) {
3983 ret = wm_adsp_buffer_read(buf,
3984 HOST_BUFFER_FIELD(next_read_index),
3989 read_index = sign_extend32(next_read_index, 23);
3991 if (read_index < 0) {
3992 compr_dbg(buf, "Avail check on unstarted stream\n");
3996 buf->read_index = read_index;
3999 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
4004 write_index = sign_extend32(next_write_index, 23);
4006 avail = write_index - buf->read_index;
4008 avail += wm_adsp_buffer_size(buf);
4010 compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
4011 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
4018 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
4020 struct wm_adsp_compr_buf *buf;
4021 struct wm_adsp_compr *compr;
4024 mutex_lock(&dsp->pwr_lock);
4026 if (list_empty(&dsp->buffer_list)) {
4031 adsp_dbg(dsp, "Handling buffer IRQ\n");
4033 list_for_each_entry(buf, &dsp->buffer_list, list) {
4036 ret = wm_adsp_buffer_get_error(buf);
4038 goto out_notify; /* Wake poll to report error */
4040 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
4043 compr_err(buf, "Failed to get irq_count: %d\n", ret);
4047 ret = wm_adsp_buffer_update_avail(buf);
4049 compr_err(buf, "Error reading avail: %d\n", ret);
4053 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
4054 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
4057 if (compr && compr->stream)
4058 snd_compr_fragment_elapsed(compr->stream);
4062 mutex_unlock(&dsp->pwr_lock);
4066 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
4068 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
4070 if (buf->irq_count & 0x01)
4073 compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count);
4075 buf->irq_count |= 0x01;
4077 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
4081 int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
4082 struct snd_compr_tstamp *tstamp)
4084 struct wm_adsp_compr *compr = stream->runtime->private_data;
4085 struct wm_adsp *dsp = compr->dsp;
4086 struct wm_adsp_compr_buf *buf;
4089 compr_dbg(compr, "Pointer request\n");
4091 mutex_lock(&dsp->pwr_lock);
4095 if (dsp->fatal_error || !buf || buf->error) {
4096 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
4101 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4102 ret = wm_adsp_buffer_update_avail(buf);
4104 compr_err(compr, "Error reading avail: %d\n", ret);
4109 * If we really have less than 1 fragment available tell the
4110 * DSP to inform us once a whole fragment is available.
4112 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4113 ret = wm_adsp_buffer_get_error(buf);
4116 snd_compr_stop_error(stream,
4117 SNDRV_PCM_STATE_XRUN);
4121 ret = wm_adsp_buffer_reenable_irq(buf);
4123 compr_err(compr, "Failed to re-enable buffer IRQ: %d\n",
4130 tstamp->copied_total = compr->copied_total;
4131 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
4132 tstamp->sampling_rate = compr->sample_rate;
4135 mutex_unlock(&dsp->pwr_lock);
4139 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
4141 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
4143 struct wm_adsp_compr_buf *buf = compr->buf;
4144 unsigned int adsp_addr;
4145 int mem_type, nwords, max_read;
4148 /* Calculate read parameters */
4149 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
4150 if (buf->read_index < buf->regions[i].cumulative_size)
4153 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
4156 mem_type = buf->regions[i].mem_type;
4157 adsp_addr = buf->regions[i].base_addr +
4158 (buf->read_index - buf->regions[i].offset);
4160 max_read = wm_adsp_compr_frag_words(compr);
4161 nwords = buf->regions[i].cumulative_size - buf->read_index;
4163 if (nwords > target)
4165 if (nwords > buf->avail)
4166 nwords = buf->avail;
4167 if (nwords > max_read)
4172 /* Read data from DSP */
4173 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
4174 nwords, compr->raw_buf);
4178 wm_adsp_remove_padding(compr->raw_buf, nwords, WM_ADSP_DATA_WORD_SIZE);
4180 /* update read index to account for words read */
4181 buf->read_index += nwords;
4182 if (buf->read_index == wm_adsp_buffer_size(buf))
4183 buf->read_index = 0;
4185 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
4190 /* update avail to account for words read */
4191 buf->avail -= nwords;
4196 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
4197 char __user *buf, size_t count)
4199 struct wm_adsp *dsp = compr->dsp;
4203 compr_dbg(compr, "Requested read of %zu bytes\n", count);
4205 if (dsp->fatal_error || !compr->buf || compr->buf->error) {
4206 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
4210 count /= WM_ADSP_DATA_WORD_SIZE;
4213 nwords = wm_adsp_buffer_capture_block(compr, count);
4215 compr_err(compr, "Failed to capture block: %d\n",
4220 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
4222 compr_dbg(compr, "Read %d bytes\n", nbytes);
4224 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
4225 compr_err(compr, "Failed to copy data to user: %d, %d\n",
4232 } while (nwords > 0 && count > 0);
4234 compr->copied_total += ntotal;
4239 int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
4242 struct wm_adsp_compr *compr = stream->runtime->private_data;
4243 struct wm_adsp *dsp = compr->dsp;
4246 mutex_lock(&dsp->pwr_lock);
4248 if (stream->direction == SND_COMPRESS_CAPTURE)
4249 ret = wm_adsp_compr_read(compr, buf, count);
4253 mutex_unlock(&dsp->pwr_lock);
4257 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
4259 static void wm_adsp_fatal_error(struct wm_adsp *dsp)
4261 struct wm_adsp_compr *compr;
4263 dsp->fatal_error = true;
4265 list_for_each_entry(compr, &dsp->compr_list, list) {
4267 snd_compr_fragment_elapsed(compr->stream);
4271 irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp)
4274 struct regmap *regmap = dsp->regmap;
4277 mutex_lock(&dsp->pwr_lock);
4279 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
4282 "Failed to read Region Lock Ctrl register: %d\n", ret);
4286 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
4287 adsp_err(dsp, "watchdog timeout error\n");
4288 dsp->ops->stop_watchdog(dsp);
4289 wm_adsp_fatal_error(dsp);
4292 if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
4293 if (val & ADSP2_SLAVE_ERR_MASK)
4294 adsp_err(dsp, "bus error: slave error\n");
4296 adsp_err(dsp, "bus error: region lock error\n");
4298 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
4301 "Failed to read Bus Err Addr register: %d\n",
4306 adsp_err(dsp, "bus error address = 0x%x\n",
4307 val & ADSP2_BUS_ERR_ADDR_MASK);
4309 ret = regmap_read(regmap,
4310 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
4314 "Failed to read Pmem Xmem Err Addr register: %d\n",
4319 adsp_err(dsp, "xmem error address = 0x%x\n",
4320 val & ADSP2_XMEM_ERR_ADDR_MASK);
4321 adsp_err(dsp, "pmem error address = 0x%x\n",
4322 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
4323 ADSP2_PMEM_ERR_ADDR_SHIFT);
4326 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
4327 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
4330 mutex_unlock(&dsp->pwr_lock);
4334 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
4336 irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp)
4338 struct regmap *regmap = dsp->regmap;
4339 unsigned int fault[6];
4340 struct reg_sequence clear[] = {
4341 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 },
4342 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 },
4343 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 },
4347 mutex_lock(&dsp->pwr_lock);
4349 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1,
4352 adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret);
4356 adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n",
4357 *fault & HALO_AHBM_FLAGS_ERR_MASK,
4358 (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >>
4359 HALO_AHBM_CORE_ERR_ADDR_SHIFT);
4361 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0,
4364 adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret);
4368 adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault);
4370 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR,
4371 fault, ARRAY_SIZE(fault));
4373 adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret);
4377 adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]);
4378 adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]);
4379 adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]);
4381 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear));
4383 adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret);
4386 mutex_unlock(&dsp->pwr_lock);
4390 EXPORT_SYMBOL_GPL(wm_halo_bus_error);
4392 irqreturn_t wm_halo_wdt_expire(int irq, void *data)
4394 struct wm_adsp *dsp = data;
4396 mutex_lock(&dsp->pwr_lock);
4398 adsp_warn(dsp, "WDT Expiry Fault\n");
4399 dsp->ops->stop_watchdog(dsp);
4400 wm_adsp_fatal_error(dsp);
4402 mutex_unlock(&dsp->pwr_lock);
4406 EXPORT_SYMBOL_GPL(wm_halo_wdt_expire);
4408 static struct wm_adsp_ops wm_adsp1_ops = {
4409 .validate_version = wm_adsp_validate_version,
4410 .parse_sizes = wm_adsp1_parse_sizes,
4411 .region_to_reg = wm_adsp_region_to_reg,
4414 static struct wm_adsp_ops wm_adsp2_ops[] = {
4416 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4417 .parse_sizes = wm_adsp2_parse_sizes,
4418 .validate_version = wm_adsp_validate_version,
4419 .setup_algs = wm_adsp2_setup_algs,
4420 .region_to_reg = wm_adsp_region_to_reg,
4422 .show_fw_status = wm_adsp2_show_fw_status,
4424 .enable_memory = wm_adsp2_enable_memory,
4425 .disable_memory = wm_adsp2_disable_memory,
4427 .enable_core = wm_adsp2_enable_core,
4428 .disable_core = wm_adsp2_disable_core,
4430 .start_core = wm_adsp2_start_core,
4431 .stop_core = wm_adsp2_stop_core,
4435 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4436 .parse_sizes = wm_adsp2_parse_sizes,
4437 .validate_version = wm_adsp_validate_version,
4438 .setup_algs = wm_adsp2_setup_algs,
4439 .region_to_reg = wm_adsp_region_to_reg,
4441 .show_fw_status = wm_adsp2v2_show_fw_status,
4443 .enable_memory = wm_adsp2_enable_memory,
4444 .disable_memory = wm_adsp2_disable_memory,
4445 .lock_memory = wm_adsp2_lock,
4447 .enable_core = wm_adsp2v2_enable_core,
4448 .disable_core = wm_adsp2v2_disable_core,
4450 .start_core = wm_adsp2_start_core,
4451 .stop_core = wm_adsp2_stop_core,
4454 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4455 .parse_sizes = wm_adsp2_parse_sizes,
4456 .validate_version = wm_adsp_validate_version,
4457 .setup_algs = wm_adsp2_setup_algs,
4458 .region_to_reg = wm_adsp_region_to_reg,
4460 .show_fw_status = wm_adsp2v2_show_fw_status,
4461 .stop_watchdog = wm_adsp_stop_watchdog,
4463 .enable_memory = wm_adsp2_enable_memory,
4464 .disable_memory = wm_adsp2_disable_memory,
4465 .lock_memory = wm_adsp2_lock,
4467 .enable_core = wm_adsp2v2_enable_core,
4468 .disable_core = wm_adsp2v2_disable_core,
4470 .start_core = wm_adsp2_start_core,
4471 .stop_core = wm_adsp2_stop_core,
4475 static struct wm_adsp_ops wm_halo_ops = {
4476 .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr),
4477 .parse_sizes = wm_adsp2_parse_sizes,
4478 .validate_version = wm_halo_validate_version,
4479 .setup_algs = wm_halo_setup_algs,
4480 .region_to_reg = wm_halo_region_to_reg,
4482 .show_fw_status = wm_halo_show_fw_status,
4483 .stop_watchdog = wm_halo_stop_watchdog,
4485 .lock_memory = wm_halo_configure_mpu,
4487 .start_core = wm_halo_start_core,
4488 .stop_core = wm_halo_stop_core,
4491 MODULE_LICENSE("GPL v2");