sound/soc/codecs/wm8962.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * wm8962.c  --  WM8962 ALSA SoC Audio driver
   4  *
   5  * Copyright 2010-2 Wolfson Microelectronics plc
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/pm.h>
  16 #include <linux/gcd.h>
  17 #include <linux/gpio/driver.h>
  18 #include <linux/i2c.h>
  19 #include <linux/input.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/mutex.h>
  26 #include <sound/core.h>
  27 #include <sound/jack.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/initval.h>
  32 #include <sound/tlv.h>
  33 #include <sound/wm8962.h>
  34 #include <trace/events/asoc.h>
  35
  36 #include "wm8962.h"
  37
  38 #define WM8962_NUM_SUPPLIES 8
  39 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  40         "DCVDD",
  41         "DBVDD",
  42         "AVDD",
  43         "CPVDD",
  44         "MICVDD",
  45         "PLLVDD",
  46         "SPKVDD1",
  47         "SPKVDD2",
  48 };
  49
  50 /* codec private data */
  51 struct wm8962_priv {
  52         struct wm8962_pdata pdata;
  53         struct regmap *regmap;
  54         struct snd_soc_component *component;
  55
  56         int sysclk;
  57         int sysclk_rate;
  58
  59         int bclk;  /* Desired BCLK */
  60         int lrclk;
  61
  62         struct completion fll_lock;
  63         int fll_src;
  64         int fll_fref;
  65         int fll_fout;
  66
  67         struct mutex dsp2_ena_lock;
  68         u16 dsp2_ena;
  69
  70         struct delayed_work mic_work;
  71         struct snd_soc_jack *jack;
  72
  73         struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  74         struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  75
  76         struct input_dev *beep;
  77         struct work_struct beep_work;
  78         int beep_rate;
  79
  80 #ifdef CONFIG_GPIOLIB
  81         struct gpio_chip gpio_chip;
  82 #endif
  83
  84         int irq;
  85 };
  86
  87 /* We can't use the same notifier block for more than one supply and
  88  * there's no way I can see to get from a callback to the caller
  89  * except container_of().
  90  */
  91 #define WM8962_REGULATOR_EVENT(n) \
  92 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  93                                     unsigned long event, void *data)    \
  94 { \
  95         struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  96                                                   disable_nb[n]); \
  97         if (event & REGULATOR_EVENT_DISABLE) { \
  98                 regcache_mark_dirty(wm8962->regmap);    \
  99         } \
 100         return 0; \
 101 }
 102
 103 WM8962_REGULATOR_EVENT(0)
 104 WM8962_REGULATOR_EVENT(1)
 105 WM8962_REGULATOR_EVENT(2)
 106 WM8962_REGULATOR_EVENT(3)
 107 WM8962_REGULATOR_EVENT(4)
 108 WM8962_REGULATOR_EVENT(5)
 109 WM8962_REGULATOR_EVENT(6)
 110 WM8962_REGULATOR_EVENT(7)
 111
 112 static const struct reg_default wm8962_reg[] = {
 113         { 0, 0x009F },   /* R0     - Left Input volume */
 114         { 1, 0x049F },   /* R1     - Right Input volume */
 115         { 2, 0x0000 },   /* R2     - HPOUTL volume */
 116         { 3, 0x0000 },   /* R3     - HPOUTR volume */
 117
 118         { 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
 119         { 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
 120         { 7, 0x000A },   /* R7     - Audio Interface 0 */
 121         { 8, 0x01E4 },   /* R8     - Clocking2 */
 122         { 9, 0x0300 },   /* R9     - Audio Interface 1 */
 123         { 10, 0x00C0 },  /* R10    - Left DAC volume */
 124         { 11, 0x00C0 },  /* R11    - Right DAC volume */
 125
 126         { 14, 0x0040 },   /* R14    - Audio Interface 2 */
 127         { 15, 0x6243 },   /* R15    - Software Reset */
 128
 129         { 17, 0x007B },   /* R17    - ALC1 */
 130         { 18, 0x0000 },   /* R18    - ALC2 */
 131         { 19, 0x1C32 },   /* R19    - ALC3 */
 132         { 20, 0x3200 },   /* R20    - Noise Gate */
 133         { 21, 0x00C0 },   /* R21    - Left ADC volume */
 134         { 22, 0x00C0 },   /* R22    - Right ADC volume */
 135         { 23, 0x0160 },   /* R23    - Additional control(1) */
 136         { 24, 0x0000 },   /* R24    - Additional control(2) */
 137         { 25, 0x0000 },   /* R25    - Pwr Mgmt (1) */
 138         { 26, 0x0000 },   /* R26    - Pwr Mgmt (2) */
 139         { 27, 0x0010 },   /* R27    - Additional Control (3) */
 140         { 28, 0x0000 },   /* R28    - Anti-pop */
 141
 142         { 30, 0x005E },   /* R30    - Clocking 3 */
 143         { 31, 0x0000 },   /* R31    - Input mixer control (1) */
 144         { 32, 0x0145 },   /* R32    - Left input mixer volume */
 145         { 33, 0x0145 },   /* R33    - Right input mixer volume */
 146         { 34, 0x0009 },   /* R34    - Input mixer control (2) */
 147         { 35, 0x0003 },   /* R35    - Input bias control */
 148         { 37, 0x0008 },   /* R37    - Left input PGA control */
 149         { 38, 0x0008 },   /* R38    - Right input PGA control */
 150
 151         { 40, 0x0000 },   /* R40    - SPKOUTL volume */
 152         { 41, 0x0000 },   /* R41    - SPKOUTR volume */
 153
 154         { 49, 0x0010 },   /* R49    - Class D Control 1 */
 155         { 51, 0x0003 },   /* R51    - Class D Control 2 */
 156
 157         { 56, 0x0506 },   /* R56    - Clocking 4 */
 158         { 57, 0x0000 },   /* R57    - DAC DSP Mixing (1) */
 159         { 58, 0x0000 },   /* R58    - DAC DSP Mixing (2) */
 160
 161         { 60, 0x0300 },   /* R60    - DC Servo 0 */
 162         { 61, 0x0300 },   /* R61    - DC Servo 1 */
 163
 164         { 64, 0x0810 },   /* R64    - DC Servo 4 */
 165
 166         { 68, 0x001B },   /* R68    - Analogue PGA Bias */
 167         { 69, 0x0000 },   /* R69    - Analogue HP 0 */
 168
 169         { 71, 0x01FB },   /* R71    - Analogue HP 2 */
 170         { 72, 0x0000 },   /* R72    - Charge Pump 1 */
 171
 172         { 82, 0x0004 },   /* R82    - Charge Pump B */
 173
 174         { 87, 0x0000 },   /* R87    - Write Sequencer Control 1 */
 175
 176         { 90, 0x0000 },   /* R90    - Write Sequencer Control 2 */
 177
 178         { 93, 0x0000 },   /* R93    - Write Sequencer Control 3 */
 179         { 94, 0x0000 },   /* R94    - Control Interface */
 180
 181         { 99, 0x0000 },   /* R99    - Mixer Enables */
 182         { 100, 0x0000 },   /* R100   - Headphone Mixer (1) */
 183         { 101, 0x0000 },   /* R101   - Headphone Mixer (2) */
 184         { 102, 0x013F },   /* R102   - Headphone Mixer (3) */
 185         { 103, 0x013F },   /* R103   - Headphone Mixer (4) */
 186
 187         { 105, 0x0000 },   /* R105   - Speaker Mixer (1) */
 188         { 106, 0x0000 },   /* R106   - Speaker Mixer (2) */
 189         { 107, 0x013F },   /* R107   - Speaker Mixer (3) */
 190         { 108, 0x013F },   /* R108   - Speaker Mixer (4) */
 191         { 109, 0x0003 },   /* R109   - Speaker Mixer (5) */
 192         { 110, 0x0002 },   /* R110   - Beep Generator (1) */
 193
 194         { 115, 0x0006 },   /* R115   - Oscillator Trim (3) */
 195         { 116, 0x0026 },   /* R116   - Oscillator Trim (4) */
 196
 197         { 119, 0x0000 },   /* R119   - Oscillator Trim (7) */
 198
 199         { 124, 0x0011 },   /* R124   - Analogue Clocking1 */
 200         { 125, 0x004B },   /* R125   - Analogue Clocking2 */
 201         { 126, 0x000D },   /* R126   - Analogue Clocking3 */
 202         { 127, 0x0000 },   /* R127   - PLL Software Reset */
 203
 204         { 131, 0x0000 },   /* R131   - PLL 4 */
 205
 206         { 136, 0x0067 },   /* R136   - PLL 9 */
 207         { 137, 0x001C },   /* R137   - PLL 10 */
 208         { 138, 0x0071 },   /* R138   - PLL 11 */
 209         { 139, 0x00C7 },   /* R139   - PLL 12 */
 210         { 140, 0x0067 },   /* R140   - PLL 13 */
 211         { 141, 0x0048 },   /* R141   - PLL 14 */
 212         { 142, 0x0022 },   /* R142   - PLL 15 */
 213         { 143, 0x0097 },   /* R143   - PLL 16 */
 214
 215         { 155, 0x000C },   /* R155   - FLL Control (1) */
 216         { 156, 0x0039 },   /* R156   - FLL Control (2) */
 217         { 157, 0x0180 },   /* R157   - FLL Control (3) */
 218
 219         { 159, 0x0032 },   /* R159   - FLL Control (5) */
 220         { 160, 0x0018 },   /* R160   - FLL Control (6) */
 221         { 161, 0x007D },   /* R161   - FLL Control (7) */
 222         { 162, 0x0008 },   /* R162   - FLL Control (8) */
 223
 224         { 252, 0x0005 },   /* R252   - General test 1 */
 225
 226         { 256, 0x0000 },   /* R256   - DF1 */
 227         { 257, 0x0000 },   /* R257   - DF2 */
 228         { 258, 0x0000 },   /* R258   - DF3 */
 229         { 259, 0x0000 },   /* R259   - DF4 */
 230         { 260, 0x0000 },   /* R260   - DF5 */
 231         { 261, 0x0000 },   /* R261   - DF6 */
 232         { 262, 0x0000 },   /* R262   - DF7 */
 233
 234         { 264, 0x0000 },   /* R264   - LHPF1 */
 235         { 265, 0x0000 },   /* R265   - LHPF2 */
 236
 237         { 268, 0x0000 },   /* R268   - THREED1 */
 238         { 269, 0x0000 },   /* R269   - THREED2 */
 239         { 270, 0x0000 },   /* R270   - THREED3 */
 240         { 271, 0x0000 },   /* R271   - THREED4 */
 241
 242         { 276, 0x000C },   /* R276   - DRC 1 */
 243         { 277, 0x0925 },   /* R277   - DRC 2 */
 244         { 278, 0x0000 },   /* R278   - DRC 3 */
 245         { 279, 0x0000 },   /* R279   - DRC 4 */
 246         { 280, 0x0000 },   /* R280   - DRC 5 */
 247
 248         { 285, 0x0000 },   /* R285   - Tloopback */
 249
 250         { 335, 0x0004 },   /* R335   - EQ1 */
 251         { 336, 0x6318 },   /* R336   - EQ2 */
 252         { 337, 0x6300 },   /* R337   - EQ3 */
 253         { 338, 0x0FCA },   /* R338   - EQ4 */
 254         { 339, 0x0400 },   /* R339   - EQ5 */
 255         { 340, 0x00D8 },   /* R340   - EQ6 */
 256         { 341, 0x1EB5 },   /* R341   - EQ7 */
 257         { 342, 0xF145 },   /* R342   - EQ8 */
 258         { 343, 0x0B75 },   /* R343   - EQ9 */
 259         { 344, 0x01C5 },   /* R344   - EQ10 */
 260         { 345, 0x1C58 },   /* R345   - EQ11 */
 261         { 346, 0xF373 },   /* R346   - EQ12 */
 262         { 347, 0x0A54 },   /* R347   - EQ13 */
 263         { 348, 0x0558 },   /* R348   - EQ14 */
 264         { 349, 0x168E },   /* R349   - EQ15 */
 265         { 350, 0xF829 },   /* R350   - EQ16 */
 266         { 351, 0x07AD },   /* R351   - EQ17 */
 267         { 352, 0x1103 },   /* R352   - EQ18 */
 268         { 353, 0x0564 },   /* R353   - EQ19 */
 269         { 354, 0x0559 },   /* R354   - EQ20 */
 270         { 355, 0x4000 },   /* R355   - EQ21 */
 271         { 356, 0x6318 },   /* R356   - EQ22 */
 272         { 357, 0x6300 },   /* R357   - EQ23 */
 273         { 358, 0x0FCA },   /* R358   - EQ24 */
 274         { 359, 0x0400 },   /* R359   - EQ25 */
 275         { 360, 0x00D8 },   /* R360   - EQ26 */
 276         { 361, 0x1EB5 },   /* R361   - EQ27 */
 277         { 362, 0xF145 },   /* R362   - EQ28 */
 278         { 363, 0x0B75 },   /* R363   - EQ29 */
 279         { 364, 0x01C5 },   /* R364   - EQ30 */
 280         { 365, 0x1C58 },   /* R365   - EQ31 */
 281         { 366, 0xF373 },   /* R366   - EQ32 */
 282         { 367, 0x0A54 },   /* R367   - EQ33 */
 283         { 368, 0x0558 },   /* R368   - EQ34 */
 284         { 369, 0x168E },   /* R369   - EQ35 */
 285         { 370, 0xF829 },   /* R370   - EQ36 */
 286         { 371, 0x07AD },   /* R371   - EQ37 */
 287         { 372, 0x1103 },   /* R372   - EQ38 */
 288         { 373, 0x0564 },   /* R373   - EQ39 */
 289         { 374, 0x0559 },   /* R374   - EQ40 */
 290         { 375, 0x4000 },   /* R375   - EQ41 */
 291
 292         { 513, 0x0000 },   /* R513   - GPIO 2 */
 293         { 514, 0x0000 },   /* R514   - GPIO 3 */
 294
 295         { 516, 0x8100 },   /* R516   - GPIO 5 */
 296         { 517, 0x8100 },   /* R517   - GPIO 6 */
 297
 298         { 568, 0x0030 },   /* R568   - Interrupt Status 1 Mask */
 299         { 569, 0xFFED },   /* R569   - Interrupt Status 2 Mask */
 300
 301         { 576, 0x0000 },   /* R576   - Interrupt Control */
 302
 303         { 584, 0x002D },   /* R584   - IRQ Debounce */
 304
 305         { 586, 0x0000 },   /* R586   -  MICINT Source Pol */
 306
 307         { 768, 0x1C00 },   /* R768   - DSP2 Power Management */
 308
 309         { 8192, 0x0000 },   /* R8192  - DSP2 Instruction RAM 0 */
 310
 311         { 9216, 0x0030 },   /* R9216  - DSP2 Address RAM 2 */
 312         { 9217, 0x0000 },   /* R9217  - DSP2 Address RAM 1 */
 313         { 9218, 0x0000 },   /* R9218  - DSP2 Address RAM 0 */
 314
 315         { 12288, 0x0000 },   /* R12288 - DSP2 Data1 RAM 1 */
 316         { 12289, 0x0000 },   /* R12289 - DSP2 Data1 RAM 0 */
 317
 318         { 13312, 0x0000 },   /* R13312 - DSP2 Data2 RAM 1 */
 319         { 13313, 0x0000 },   /* R13313 - DSP2 Data2 RAM 0 */
 320
 321         { 14336, 0x0000 },   /* R14336 - DSP2 Data3 RAM 1 */
 322         { 14337, 0x0000 },   /* R14337 - DSP2 Data3 RAM 0 */
 323
 324         { 15360, 0x000A },   /* R15360 - DSP2 Coeff RAM 0 */
 325
 326         { 16384, 0x0000 },   /* R16384 - RETUNEADC_SHARED_COEFF_1 */
 327         { 16385, 0x0000 },   /* R16385 - RETUNEADC_SHARED_COEFF_0 */
 328         { 16386, 0x0000 },   /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
 329         { 16387, 0x0000 },   /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
 330         { 16388, 0x0000 },   /* R16388 - SOUNDSTAGE_ENABLES_1 */
 331         { 16389, 0x0000 },   /* R16389 - SOUNDSTAGE_ENABLES_0 */
 332
 333         { 16896, 0x0002 },   /* R16896 - HDBASS_AI_1 */
 334         { 16897, 0xBD12 },   /* R16897 - HDBASS_AI_0 */
 335         { 16898, 0x007C },   /* R16898 - HDBASS_AR_1 */
 336         { 16899, 0x586C },   /* R16899 - HDBASS_AR_0 */
 337         { 16900, 0x0053 },   /* R16900 - HDBASS_B_1 */
 338         { 16901, 0x8121 },   /* R16901 - HDBASS_B_0 */
 339         { 16902, 0x003F },   /* R16902 - HDBASS_K_1 */
 340         { 16903, 0x8BD8 },   /* R16903 - HDBASS_K_0 */
 341         { 16904, 0x0032 },   /* R16904 - HDBASS_N1_1 */
 342         { 16905, 0xF52D },   /* R16905 - HDBASS_N1_0 */
 343         { 16906, 0x0065 },   /* R16906 - HDBASS_N2_1 */
 344         { 16907, 0xAC8C },   /* R16907 - HDBASS_N2_0 */
 345         { 16908, 0x006B },   /* R16908 - HDBASS_N3_1 */
 346         { 16909, 0xE087 },   /* R16909 - HDBASS_N3_0 */
 347         { 16910, 0x0072 },   /* R16910 - HDBASS_N4_1 */
 348         { 16911, 0x1483 },   /* R16911 - HDBASS_N4_0 */
 349         { 16912, 0x0072 },   /* R16912 - HDBASS_N5_1 */
 350         { 16913, 0x1483 },   /* R16913 - HDBASS_N5_0 */
 351         { 16914, 0x0043 },   /* R16914 - HDBASS_X1_1 */
 352         { 16915, 0x3525 },   /* R16915 - HDBASS_X1_0 */
 353         { 16916, 0x0006 },   /* R16916 - HDBASS_X2_1 */
 354         { 16917, 0x6A4A },   /* R16917 - HDBASS_X2_0 */
 355         { 16918, 0x0043 },   /* R16918 - HDBASS_X3_1 */
 356         { 16919, 0x6079 },   /* R16919 - HDBASS_X3_0 */
 357         { 16920, 0x0008 },   /* R16920 - HDBASS_ATK_1 */
 358         { 16921, 0x0000 },   /* R16921 - HDBASS_ATK_0 */
 359         { 16922, 0x0001 },   /* R16922 - HDBASS_DCY_1 */
 360         { 16923, 0x0000 },   /* R16923 - HDBASS_DCY_0 */
 361         { 16924, 0x0059 },   /* R16924 - HDBASS_PG_1 */
 362         { 16925, 0x999A },   /* R16925 - HDBASS_PG_0 */
 363
 364         { 17408, 0x0083 },   /* R17408 - HPF_C_1 */
 365         { 17409, 0x98AD },   /* R17409 - HPF_C_0 */
 366
 367         { 17920, 0x007F },   /* R17920 - ADCL_RETUNE_C1_1 */
 368         { 17921, 0xFFFF },   /* R17921 - ADCL_RETUNE_C1_0 */
 369         { 17922, 0x0000 },   /* R17922 - ADCL_RETUNE_C2_1 */
 370         { 17923, 0x0000 },   /* R17923 - ADCL_RETUNE_C2_0 */
 371         { 17924, 0x0000 },   /* R17924 - ADCL_RETUNE_C3_1 */
 372         { 17925, 0x0000 },   /* R17925 - ADCL_RETUNE_C3_0 */
 373         { 17926, 0x0000 },   /* R17926 - ADCL_RETUNE_C4_1 */
 374         { 17927, 0x0000 },   /* R17927 - ADCL_RETUNE_C4_0 */
 375         { 17928, 0x0000 },   /* R17928 - ADCL_RETUNE_C5_1 */
 376         { 17929, 0x0000 },   /* R17929 - ADCL_RETUNE_C5_0 */
 377         { 17930, 0x0000 },   /* R17930 - ADCL_RETUNE_C6_1 */
 378         { 17931, 0x0000 },   /* R17931 - ADCL_RETUNE_C6_0 */
 379         { 17932, 0x0000 },   /* R17932 - ADCL_RETUNE_C7_1 */
 380         { 17933, 0x0000 },   /* R17933 - ADCL_RETUNE_C7_0 */
 381         { 17934, 0x0000 },   /* R17934 - ADCL_RETUNE_C8_1 */
 382         { 17935, 0x0000 },   /* R17935 - ADCL_RETUNE_C8_0 */
 383         { 17936, 0x0000 },   /* R17936 - ADCL_RETUNE_C9_1 */
 384         { 17937, 0x0000 },   /* R17937 - ADCL_RETUNE_C9_0 */
 385         { 17938, 0x0000 },   /* R17938 - ADCL_RETUNE_C10_1 */
 386         { 17939, 0x0000 },   /* R17939 - ADCL_RETUNE_C10_0 */
 387         { 17940, 0x0000 },   /* R17940 - ADCL_RETUNE_C11_1 */
 388         { 17941, 0x0000 },   /* R17941 - ADCL_RETUNE_C11_0 */
 389         { 17942, 0x0000 },   /* R17942 - ADCL_RETUNE_C12_1 */
 390         { 17943, 0x0000 },   /* R17943 - ADCL_RETUNE_C12_0 */
 391         { 17944, 0x0000 },   /* R17944 - ADCL_RETUNE_C13_1 */
 392         { 17945, 0x0000 },   /* R17945 - ADCL_RETUNE_C13_0 */
 393         { 17946, 0x0000 },   /* R17946 - ADCL_RETUNE_C14_1 */
 394         { 17947, 0x0000 },   /* R17947 - ADCL_RETUNE_C14_0 */
 395         { 17948, 0x0000 },   /* R17948 - ADCL_RETUNE_C15_1 */
 396         { 17949, 0x0000 },   /* R17949 - ADCL_RETUNE_C15_0 */
 397         { 17950, 0x0000 },   /* R17950 - ADCL_RETUNE_C16_1 */
 398         { 17951, 0x0000 },   /* R17951 - ADCL_RETUNE_C16_0 */
 399         { 17952, 0x0000 },   /* R17952 - ADCL_RETUNE_C17_1 */
 400         { 17953, 0x0000 },   /* R17953 - ADCL_RETUNE_C17_0 */
 401         { 17954, 0x0000 },   /* R17954 - ADCL_RETUNE_C18_1 */
 402         { 17955, 0x0000 },   /* R17955 - ADCL_RETUNE_C18_0 */
 403         { 17956, 0x0000 },   /* R17956 - ADCL_RETUNE_C19_1 */
 404         { 17957, 0x0000 },   /* R17957 - ADCL_RETUNE_C19_0 */
 405         { 17958, 0x0000 },   /* R17958 - ADCL_RETUNE_C20_1 */
 406         { 17959, 0x0000 },   /* R17959 - ADCL_RETUNE_C20_0 */
 407         { 17960, 0x0000 },   /* R17960 - ADCL_RETUNE_C21_1 */
 408         { 17961, 0x0000 },   /* R17961 - ADCL_RETUNE_C21_0 */
 409         { 17962, 0x0000 },   /* R17962 - ADCL_RETUNE_C22_1 */
 410         { 17963, 0x0000 },   /* R17963 - ADCL_RETUNE_C22_0 */
 411         { 17964, 0x0000 },   /* R17964 - ADCL_RETUNE_C23_1 */
 412         { 17965, 0x0000 },   /* R17965 - ADCL_RETUNE_C23_0 */
 413         { 17966, 0x0000 },   /* R17966 - ADCL_RETUNE_C24_1 */
 414         { 17967, 0x0000 },   /* R17967 - ADCL_RETUNE_C24_0 */
 415         { 17968, 0x0000 },   /* R17968 - ADCL_RETUNE_C25_1 */
 416         { 17969, 0x0000 },   /* R17969 - ADCL_RETUNE_C25_0 */
 417         { 17970, 0x0000 },   /* R17970 - ADCL_RETUNE_C26_1 */
 418         { 17971, 0x0000 },   /* R17971 - ADCL_RETUNE_C26_0 */
 419         { 17972, 0x0000 },   /* R17972 - ADCL_RETUNE_C27_1 */
 420         { 17973, 0x0000 },   /* R17973 - ADCL_RETUNE_C27_0 */
 421         { 17974, 0x0000 },   /* R17974 - ADCL_RETUNE_C28_1 */
 422         { 17975, 0x0000 },   /* R17975 - ADCL_RETUNE_C28_0 */
 423         { 17976, 0x0000 },   /* R17976 - ADCL_RETUNE_C29_1 */
 424         { 17977, 0x0000 },   /* R17977 - ADCL_RETUNE_C29_0 */
 425         { 17978, 0x0000 },   /* R17978 - ADCL_RETUNE_C30_1 */
 426         { 17979, 0x0000 },   /* R17979 - ADCL_RETUNE_C30_0 */
 427         { 17980, 0x0000 },   /* R17980 - ADCL_RETUNE_C31_1 */
 428         { 17981, 0x0000 },   /* R17981 - ADCL_RETUNE_C31_0 */
 429         { 17982, 0x0000 },   /* R17982 - ADCL_RETUNE_C32_1 */
 430         { 17983, 0x0000 },   /* R17983 - ADCL_RETUNE_C32_0 */
 431
 432         { 18432, 0x0020 },   /* R18432 - RETUNEADC_PG2_1 */
 433         { 18433, 0x0000 },   /* R18433 - RETUNEADC_PG2_0 */
 434         { 18434, 0x0040 },   /* R18434 - RETUNEADC_PG_1 */
 435         { 18435, 0x0000 },   /* R18435 - RETUNEADC_PG_0 */
 436
 437         { 18944, 0x007F },   /* R18944 - ADCR_RETUNE_C1_1 */
 438         { 18945, 0xFFFF },   /* R18945 - ADCR_RETUNE_C1_0 */
 439         { 18946, 0x0000 },   /* R18946 - ADCR_RETUNE_C2_1 */
 440         { 18947, 0x0000 },   /* R18947 - ADCR_RETUNE_C2_0 */
 441         { 18948, 0x0000 },   /* R18948 - ADCR_RETUNE_C3_1 */
 442         { 18949, 0x0000 },   /* R18949 - ADCR_RETUNE_C3_0 */
 443         { 18950, 0x0000 },   /* R18950 - ADCR_RETUNE_C4_1 */
 444         { 18951, 0x0000 },   /* R18951 - ADCR_RETUNE_C4_0 */
 445         { 18952, 0x0000 },   /* R18952 - ADCR_RETUNE_C5_1 */
 446         { 18953, 0x0000 },   /* R18953 - ADCR_RETUNE_C5_0 */
 447         { 18954, 0x0000 },   /* R18954 - ADCR_RETUNE_C6_1 */
 448         { 18955, 0x0000 },   /* R18955 - ADCR_RETUNE_C6_0 */
 449         { 18956, 0x0000 },   /* R18956 - ADCR_RETUNE_C7_1 */
 450         { 18957, 0x0000 },   /* R18957 - ADCR_RETUNE_C7_0 */
 451         { 18958, 0x0000 },   /* R18958 - ADCR_RETUNE_C8_1 */
 452         { 18959, 0x0000 },   /* R18959 - ADCR_RETUNE_C8_0 */
 453         { 18960, 0x0000 },   /* R18960 - ADCR_RETUNE_C9_1 */
 454         { 18961, 0x0000 },   /* R18961 - ADCR_RETUNE_C9_0 */
 455         { 18962, 0x0000 },   /* R18962 - ADCR_RETUNE_C10_1 */
 456         { 18963, 0x0000 },   /* R18963 - ADCR_RETUNE_C10_0 */
 457         { 18964, 0x0000 },   /* R18964 - ADCR_RETUNE_C11_1 */
 458         { 18965, 0x0000 },   /* R18965 - ADCR_RETUNE_C11_0 */
 459         { 18966, 0x0000 },   /* R18966 - ADCR_RETUNE_C12_1 */
 460         { 18967, 0x0000 },   /* R18967 - ADCR_RETUNE_C12_0 */
 461         { 18968, 0x0000 },   /* R18968 - ADCR_RETUNE_C13_1 */
 462         { 18969, 0x0000 },   /* R18969 - ADCR_RETUNE_C13_0 */
 463         { 18970, 0x0000 },   /* R18970 - ADCR_RETUNE_C14_1 */
 464         { 18971, 0x0000 },   /* R18971 - ADCR_RETUNE_C14_0 */
 465         { 18972, 0x0000 },   /* R18972 - ADCR_RETUNE_C15_1 */
 466         { 18973, 0x0000 },   /* R18973 - ADCR_RETUNE_C15_0 */
 467         { 18974, 0x0000 },   /* R18974 - ADCR_RETUNE_C16_1 */
 468         { 18975, 0x0000 },   /* R18975 - ADCR_RETUNE_C16_0 */
 469         { 18976, 0x0000 },   /* R18976 - ADCR_RETUNE_C17_1 */
 470         { 18977, 0x0000 },   /* R18977 - ADCR_RETUNE_C17_0 */
 471         { 18978, 0x0000 },   /* R18978 - ADCR_RETUNE_C18_1 */
 472         { 18979, 0x0000 },   /* R18979 - ADCR_RETUNE_C18_0 */
 473         { 18980, 0x0000 },   /* R18980 - ADCR_RETUNE_C19_1 */
 474         { 18981, 0x0000 },   /* R18981 - ADCR_RETUNE_C19_0 */
 475         { 18982, 0x0000 },   /* R18982 - ADCR_RETUNE_C20_1 */
 476         { 18983, 0x0000 },   /* R18983 - ADCR_RETUNE_C20_0 */
 477         { 18984, 0x0000 },   /* R18984 - ADCR_RETUNE_C21_1 */
 478         { 18985, 0x0000 },   /* R18985 - ADCR_RETUNE_C21_0 */
 479         { 18986, 0x0000 },   /* R18986 - ADCR_RETUNE_C22_1 */
 480         { 18987, 0x0000 },   /* R18987 - ADCR_RETUNE_C22_0 */
 481         { 18988, 0x0000 },   /* R18988 - ADCR_RETUNE_C23_1 */
 482         { 18989, 0x0000 },   /* R18989 - ADCR_RETUNE_C23_0 */
 483         { 18990, 0x0000 },   /* R18990 - ADCR_RETUNE_C24_1 */
 484         { 18991, 0x0000 },   /* R18991 - ADCR_RETUNE_C24_0 */
 485         { 18992, 0x0000 },   /* R18992 - ADCR_RETUNE_C25_1 */
 486         { 18993, 0x0000 },   /* R18993 - ADCR_RETUNE_C25_0 */
 487         { 18994, 0x0000 },   /* R18994 - ADCR_RETUNE_C26_1 */
 488         { 18995, 0x0000 },   /* R18995 - ADCR_RETUNE_C26_0 */
 489         { 18996, 0x0000 },   /* R18996 - ADCR_RETUNE_C27_1 */
 490         { 18997, 0x0000 },   /* R18997 - ADCR_RETUNE_C27_0 */
 491         { 18998, 0x0000 },   /* R18998 - ADCR_RETUNE_C28_1 */
 492         { 18999, 0x0000 },   /* R18999 - ADCR_RETUNE_C28_0 */
 493         { 19000, 0x0000 },   /* R19000 - ADCR_RETUNE_C29_1 */
 494         { 19001, 0x0000 },   /* R19001 - ADCR_RETUNE_C29_0 */
 495         { 19002, 0x0000 },   /* R19002 - ADCR_RETUNE_C30_1 */
 496         { 19003, 0x0000 },   /* R19003 - ADCR_RETUNE_C30_0 */
 497         { 19004, 0x0000 },   /* R19004 - ADCR_RETUNE_C31_1 */
 498         { 19005, 0x0000 },   /* R19005 - ADCR_RETUNE_C31_0 */
 499         { 19006, 0x0000 },   /* R19006 - ADCR_RETUNE_C32_1 */
 500         { 19007, 0x0000 },   /* R19007 - ADCR_RETUNE_C32_0 */
 501
 502         { 19456, 0x007F },   /* R19456 - DACL_RETUNE_C1_1 */
 503         { 19457, 0xFFFF },   /* R19457 - DACL_RETUNE_C1_0 */
 504         { 19458, 0x0000 },   /* R19458 - DACL_RETUNE_C2_1 */
 505         { 19459, 0x0000 },   /* R19459 - DACL_RETUNE_C2_0 */
 506         { 19460, 0x0000 },   /* R19460 - DACL_RETUNE_C3_1 */
 507         { 19461, 0x0000 },   /* R19461 - DACL_RETUNE_C3_0 */
 508         { 19462, 0x0000 },   /* R19462 - DACL_RETUNE_C4_1 */
 509         { 19463, 0x0000 },   /* R19463 - DACL_RETUNE_C4_0 */
 510         { 19464, 0x0000 },   /* R19464 - DACL_RETUNE_C5_1 */
 511         { 19465, 0x0000 },   /* R19465 - DACL_RETUNE_C5_0 */
 512         { 19466, 0x0000 },   /* R19466 - DACL_RETUNE_C6_1 */
 513         { 19467, 0x0000 },   /* R19467 - DACL_RETUNE_C6_0 */
 514         { 19468, 0x0000 },   /* R19468 - DACL_RETUNE_C7_1 */
 515         { 19469, 0x0000 },   /* R19469 - DACL_RETUNE_C7_0 */
 516         { 19470, 0x0000 },   /* R19470 - DACL_RETUNE_C8_1 */
 517         { 19471, 0x0000 },   /* R19471 - DACL_RETUNE_C8_0 */
 518         { 19472, 0x0000 },   /* R19472 - DACL_RETUNE_C9_1 */
 519         { 19473, 0x0000 },   /* R19473 - DACL_RETUNE_C9_0 */
 520         { 19474, 0x0000 },   /* R19474 - DACL_RETUNE_C10_1 */
 521         { 19475, 0x0000 },   /* R19475 - DACL_RETUNE_C10_0 */
 522         { 19476, 0x0000 },   /* R19476 - DACL_RETUNE_C11_1 */
 523         { 19477, 0x0000 },   /* R19477 - DACL_RETUNE_C11_0 */
 524         { 19478, 0x0000 },   /* R19478 - DACL_RETUNE_C12_1 */
 525         { 19479, 0x0000 },   /* R19479 - DACL_RETUNE_C12_0 */
 526         { 19480, 0x0000 },   /* R19480 - DACL_RETUNE_C13_1 */
 527         { 19481, 0x0000 },   /* R19481 - DACL_RETUNE_C13_0 */
 528         { 19482, 0x0000 },   /* R19482 - DACL_RETUNE_C14_1 */
 529         { 19483, 0x0000 },   /* R19483 - DACL_RETUNE_C14_0 */
 530         { 19484, 0x0000 },   /* R19484 - DACL_RETUNE_C15_1 */
 531         { 19485, 0x0000 },   /* R19485 - DACL_RETUNE_C15_0 */
 532         { 19486, 0x0000 },   /* R19486 - DACL_RETUNE_C16_1 */
 533         { 19487, 0x0000 },   /* R19487 - DACL_RETUNE_C16_0 */
 534         { 19488, 0x0000 },   /* R19488 - DACL_RETUNE_C17_1 */
 535         { 19489, 0x0000 },   /* R19489 - DACL_RETUNE_C17_0 */
 536         { 19490, 0x0000 },   /* R19490 - DACL_RETUNE_C18_1 */
 537         { 19491, 0x0000 },   /* R19491 - DACL_RETUNE_C18_0 */
 538         { 19492, 0x0000 },   /* R19492 - DACL_RETUNE_C19_1 */
 539         { 19493, 0x0000 },   /* R19493 - DACL_RETUNE_C19_0 */
 540         { 19494, 0x0000 },   /* R19494 - DACL_RETUNE_C20_1 */
 541         { 19495, 0x0000 },   /* R19495 - DACL_RETUNE_C20_0 */
 542         { 19496, 0x0000 },   /* R19496 - DACL_RETUNE_C21_1 */
 543         { 19497, 0x0000 },   /* R19497 - DACL_RETUNE_C21_0 */
 544         { 19498, 0x0000 },   /* R19498 - DACL_RETUNE_C22_1 */
 545         { 19499, 0x0000 },   /* R19499 - DACL_RETUNE_C22_0 */
 546         { 19500, 0x0000 },   /* R19500 - DACL_RETUNE_C23_1 */
 547         { 19501, 0x0000 },   /* R19501 - DACL_RETUNE_C23_0 */
 548         { 19502, 0x0000 },   /* R19502 - DACL_RETUNE_C24_1 */
 549         { 19503, 0x0000 },   /* R19503 - DACL_RETUNE_C24_0 */
 550         { 19504, 0x0000 },   /* R19504 - DACL_RETUNE_C25_1 */
 551         { 19505, 0x0000 },   /* R19505 - DACL_RETUNE_C25_0 */
 552         { 19506, 0x0000 },   /* R19506 - DACL_RETUNE_C26_1 */
 553         { 19507, 0x0000 },   /* R19507 - DACL_RETUNE_C26_0 */
 554         { 19508, 0x0000 },   /* R19508 - DACL_RETUNE_C27_1 */
 555         { 19509, 0x0000 },   /* R19509 - DACL_RETUNE_C27_0 */
 556         { 19510, 0x0000 },   /* R19510 - DACL_RETUNE_C28_1 */
 557         { 19511, 0x0000 },   /* R19511 - DACL_RETUNE_C28_0 */
 558         { 19512, 0x0000 },   /* R19512 - DACL_RETUNE_C29_1 */
 559         { 19513, 0x0000 },   /* R19513 - DACL_RETUNE_C29_0 */
 560         { 19514, 0x0000 },   /* R19514 - DACL_RETUNE_C30_1 */
 561         { 19515, 0x0000 },   /* R19515 - DACL_RETUNE_C30_0 */
 562         { 19516, 0x0000 },   /* R19516 - DACL_RETUNE_C31_1 */
 563         { 19517, 0x0000 },   /* R19517 - DACL_RETUNE_C31_0 */
 564         { 19518, 0x0000 },   /* R19518 - DACL_RETUNE_C32_1 */
 565         { 19519, 0x0000 },   /* R19519 - DACL_RETUNE_C32_0 */
 566
 567         { 19968, 0x0020 },   /* R19968 - RETUNEDAC_PG2_1 */
 568         { 19969, 0x0000 },   /* R19969 - RETUNEDAC_PG2_0 */
 569         { 19970, 0x0040 },   /* R19970 - RETUNEDAC_PG_1 */
 570         { 19971, 0x0000 },   /* R19971 - RETUNEDAC_PG_0 */
 571
 572         { 20480, 0x007F },   /* R20480 - DACR_RETUNE_C1_1 */
 573         { 20481, 0xFFFF },   /* R20481 - DACR_RETUNE_C1_0 */
 574         { 20482, 0x0000 },   /* R20482 - DACR_RETUNE_C2_1 */
 575         { 20483, 0x0000 },   /* R20483 - DACR_RETUNE_C2_0 */
 576         { 20484, 0x0000 },   /* R20484 - DACR_RETUNE_C3_1 */
 577         { 20485, 0x0000 },   /* R20485 - DACR_RETUNE_C3_0 */
 578         { 20486, 0x0000 },   /* R20486 - DACR_RETUNE_C4_1 */
 579         { 20487, 0x0000 },   /* R20487 - DACR_RETUNE_C4_0 */
 580         { 20488, 0x0000 },   /* R20488 - DACR_RETUNE_C5_1 */
 581         { 20489, 0x0000 },   /* R20489 - DACR_RETUNE_C5_0 */
 582         { 20490, 0x0000 },   /* R20490 - DACR_RETUNE_C6_1 */
 583         { 20491, 0x0000 },   /* R20491 - DACR_RETUNE_C6_0 */
 584         { 20492, 0x0000 },   /* R20492 - DACR_RETUNE_C7_1 */
 585         { 20493, 0x0000 },   /* R20493 - DACR_RETUNE_C7_0 */
 586         { 20494, 0x0000 },   /* R20494 - DACR_RETUNE_C8_1 */
 587         { 20495, 0x0000 },   /* R20495 - DACR_RETUNE_C8_0 */
 588         { 20496, 0x0000 },   /* R20496 - DACR_RETUNE_C9_1 */
 589         { 20497, 0x0000 },   /* R20497 - DACR_RETUNE_C9_0 */
 590         { 20498, 0x0000 },   /* R20498 - DACR_RETUNE_C10_1 */
 591         { 20499, 0x0000 },   /* R20499 - DACR_RETUNE_C10_0 */
 592         { 20500, 0x0000 },   /* R20500 - DACR_RETUNE_C11_1 */
 593         { 20501, 0x0000 },   /* R20501 - DACR_RETUNE_C11_0 */
 594         { 20502, 0x0000 },   /* R20502 - DACR_RETUNE_C12_1 */
 595         { 20503, 0x0000 },   /* R20503 - DACR_RETUNE_C12_0 */
 596         { 20504, 0x0000 },   /* R20504 - DACR_RETUNE_C13_1 */
 597         { 20505, 0x0000 },   /* R20505 - DACR_RETUNE_C13_0 */
 598         { 20506, 0x0000 },   /* R20506 - DACR_RETUNE_C14_1 */
 599         { 20507, 0x0000 },   /* R20507 - DACR_RETUNE_C14_0 */
 600         { 20508, 0x0000 },   /* R20508 - DACR_RETUNE_C15_1 */
 601         { 20509, 0x0000 },   /* R20509 - DACR_RETUNE_C15_0 */
 602         { 20510, 0x0000 },   /* R20510 - DACR_RETUNE_C16_1 */
 603         { 20511, 0x0000 },   /* R20511 - DACR_RETUNE_C16_0 */
 604         { 20512, 0x0000 },   /* R20512 - DACR_RETUNE_C17_1 */
 605         { 20513, 0x0000 },   /* R20513 - DACR_RETUNE_C17_0 */
 606         { 20514, 0x0000 },   /* R20514 - DACR_RETUNE_C18_1 */
 607         { 20515, 0x0000 },   /* R20515 - DACR_RETUNE_C18_0 */
 608         { 20516, 0x0000 },   /* R20516 - DACR_RETUNE_C19_1 */
 609         { 20517, 0x0000 },   /* R20517 - DACR_RETUNE_C19_0 */
 610         { 20518, 0x0000 },   /* R20518 - DACR_RETUNE_C20_1 */
 611         { 20519, 0x0000 },   /* R20519 - DACR_RETUNE_C20_0 */
 612         { 20520, 0x0000 },   /* R20520 - DACR_RETUNE_C21_1 */
 613         { 20521, 0x0000 },   /* R20521 - DACR_RETUNE_C21_0 */
 614         { 20522, 0x0000 },   /* R20522 - DACR_RETUNE_C22_1 */
 615         { 20523, 0x0000 },   /* R20523 - DACR_RETUNE_C22_0 */
 616         { 20524, 0x0000 },   /* R20524 - DACR_RETUNE_C23_1 */
 617         { 20525, 0x0000 },   /* R20525 - DACR_RETUNE_C23_0 */
 618         { 20526, 0x0000 },   /* R20526 - DACR_RETUNE_C24_1 */
 619         { 20527, 0x0000 },   /* R20527 - DACR_RETUNE_C24_0 */
 620         { 20528, 0x0000 },   /* R20528 - DACR_RETUNE_C25_1 */
 621         { 20529, 0x0000 },   /* R20529 - DACR_RETUNE_C25_0 */
 622         { 20530, 0x0000 },   /* R20530 - DACR_RETUNE_C26_1 */
 623         { 20531, 0x0000 },   /* R20531 - DACR_RETUNE_C26_0 */
 624         { 20532, 0x0000 },   /* R20532 - DACR_RETUNE_C27_1 */
 625         { 20533, 0x0000 },   /* R20533 - DACR_RETUNE_C27_0 */
 626         { 20534, 0x0000 },   /* R20534 - DACR_RETUNE_C28_1 */
 627         { 20535, 0x0000 },   /* R20535 - DACR_RETUNE_C28_0 */
 628         { 20536, 0x0000 },   /* R20536 - DACR_RETUNE_C29_1 */
 629         { 20537, 0x0000 },   /* R20537 - DACR_RETUNE_C29_0 */
 630         { 20538, 0x0000 },   /* R20538 - DACR_RETUNE_C30_1 */
 631         { 20539, 0x0000 },   /* R20539 - DACR_RETUNE_C30_0 */
 632         { 20540, 0x0000 },   /* R20540 - DACR_RETUNE_C31_1 */
 633         { 20541, 0x0000 },   /* R20541 - DACR_RETUNE_C31_0 */
 634         { 20542, 0x0000 },   /* R20542 - DACR_RETUNE_C32_1 */
 635         { 20543, 0x0000 },   /* R20543 - DACR_RETUNE_C32_0 */
 636
 637         { 20992, 0x008C },   /* R20992 - VSS_XHD2_1 */
 638         { 20993, 0x0200 },   /* R20993 - VSS_XHD2_0 */
 639         { 20994, 0x0035 },   /* R20994 - VSS_XHD3_1 */
 640         { 20995, 0x0700 },   /* R20995 - VSS_XHD3_0 */
 641         { 20996, 0x003A },   /* R20996 - VSS_XHN1_1 */
 642         { 20997, 0x4100 },   /* R20997 - VSS_XHN1_0 */
 643         { 20998, 0x008B },   /* R20998 - VSS_XHN2_1 */
 644         { 20999, 0x7D00 },   /* R20999 - VSS_XHN2_0 */
 645         { 21000, 0x003A },   /* R21000 - VSS_XHN3_1 */
 646         { 21001, 0x4100 },   /* R21001 - VSS_XHN3_0 */
 647         { 21002, 0x008C },   /* R21002 - VSS_XLA_1 */
 648         { 21003, 0xFEE8 },   /* R21003 - VSS_XLA_0 */
 649         { 21004, 0x0078 },   /* R21004 - VSS_XLB_1 */
 650         { 21005, 0x0000 },   /* R21005 - VSS_XLB_0 */
 651         { 21006, 0x003F },   /* R21006 - VSS_XLG_1 */
 652         { 21007, 0xB260 },   /* R21007 - VSS_XLG_0 */
 653         { 21008, 0x002D },   /* R21008 - VSS_PG2_1 */
 654         { 21009, 0x1818 },   /* R21009 - VSS_PG2_0 */
 655         { 21010, 0x0020 },   /* R21010 - VSS_PG_1 */
 656         { 21011, 0x0000 },   /* R21011 - VSS_PG_0 */
 657         { 21012, 0x00F1 },   /* R21012 - VSS_XTD1_1 */
 658         { 21013, 0x8340 },   /* R21013 - VSS_XTD1_0 */
 659         { 21014, 0x00FB },   /* R21014 - VSS_XTD2_1 */
 660         { 21015, 0x8300 },   /* R21015 - VSS_XTD2_0 */
 661         { 21016, 0x00EE },   /* R21016 - VSS_XTD3_1 */
 662         { 21017, 0xAEC0 },   /* R21017 - VSS_XTD3_0 */
 663         { 21018, 0x00FB },   /* R21018 - VSS_XTD4_1 */
 664         { 21019, 0xAC40 },   /* R21019 - VSS_XTD4_0 */
 665         { 21020, 0x00F1 },   /* R21020 - VSS_XTD5_1 */
 666         { 21021, 0x7F80 },   /* R21021 - VSS_XTD5_0 */
 667         { 21022, 0x00F4 },   /* R21022 - VSS_XTD6_1 */
 668         { 21023, 0x3B40 },   /* R21023 - VSS_XTD6_0 */
 669         { 21024, 0x00F5 },   /* R21024 - VSS_XTD7_1 */
 670         { 21025, 0xFB00 },   /* R21025 - VSS_XTD7_0 */
 671         { 21026, 0x00EA },   /* R21026 - VSS_XTD8_1 */
 672         { 21027, 0x10C0 },   /* R21027 - VSS_XTD8_0 */
 673         { 21028, 0x00FC },   /* R21028 - VSS_XTD9_1 */
 674         { 21029, 0xC580 },   /* R21029 - VSS_XTD9_0 */
 675         { 21030, 0x00E2 },   /* R21030 - VSS_XTD10_1 */
 676         { 21031, 0x75C0 },   /* R21031 - VSS_XTD10_0 */
 677         { 21032, 0x0004 },   /* R21032 - VSS_XTD11_1 */
 678         { 21033, 0xB480 },   /* R21033 - VSS_XTD11_0 */
 679         { 21034, 0x00D4 },   /* R21034 - VSS_XTD12_1 */
 680         { 21035, 0xF980 },   /* R21035 - VSS_XTD12_0 */
 681         { 21036, 0x0004 },   /* R21036 - VSS_XTD13_1 */
 682         { 21037, 0x9140 },   /* R21037 - VSS_XTD13_0 */
 683         { 21038, 0x00D8 },   /* R21038 - VSS_XTD14_1 */
 684         { 21039, 0xA480 },   /* R21039 - VSS_XTD14_0 */
 685         { 21040, 0x0002 },   /* R21040 - VSS_XTD15_1 */
 686         { 21041, 0x3DC0 },   /* R21041 - VSS_XTD15_0 */
 687         { 21042, 0x00CF },   /* R21042 - VSS_XTD16_1 */
 688         { 21043, 0x7A80 },   /* R21043 - VSS_XTD16_0 */
 689         { 21044, 0x00DC },   /* R21044 - VSS_XTD17_1 */
 690         { 21045, 0x0600 },   /* R21045 - VSS_XTD17_0 */
 691         { 21046, 0x00F2 },   /* R21046 - VSS_XTD18_1 */
 692         { 21047, 0xDAC0 },   /* R21047 - VSS_XTD18_0 */
 693         { 21048, 0x00BA },   /* R21048 - VSS_XTD19_1 */
 694         { 21049, 0xF340 },   /* R21049 - VSS_XTD19_0 */
 695         { 21050, 0x000A },   /* R21050 - VSS_XTD20_1 */
 696         { 21051, 0x7940 },   /* R21051 - VSS_XTD20_0 */
 697         { 21052, 0x001C },   /* R21052 - VSS_XTD21_1 */
 698         { 21053, 0x0680 },   /* R21053 - VSS_XTD21_0 */
 699         { 21054, 0x00FD },   /* R21054 - VSS_XTD22_1 */
 700         { 21055, 0x2D00 },   /* R21055 - VSS_XTD22_0 */
 701         { 21056, 0x001C },   /* R21056 - VSS_XTD23_1 */
 702         { 21057, 0xE840 },   /* R21057 - VSS_XTD23_0 */
 703         { 21058, 0x000D },   /* R21058 - VSS_XTD24_1 */
 704         { 21059, 0xDC40 },   /* R21059 - VSS_XTD24_0 */
 705         { 21060, 0x00FC },   /* R21060 - VSS_XTD25_1 */
 706         { 21061, 0x9D00 },   /* R21061 - VSS_XTD25_0 */
 707         { 21062, 0x0009 },   /* R21062 - VSS_XTD26_1 */
 708         { 21063, 0x5580 },   /* R21063 - VSS_XTD26_0 */
 709         { 21064, 0x00FE },   /* R21064 - VSS_XTD27_1 */
 710         { 21065, 0x7E80 },   /* R21065 - VSS_XTD27_0 */
 711         { 21066, 0x000E },   /* R21066 - VSS_XTD28_1 */
 712         { 21067, 0xAB40 },   /* R21067 - VSS_XTD28_0 */
 713         { 21068, 0x00F9 },   /* R21068 - VSS_XTD29_1 */
 714         { 21069, 0x9880 },   /* R21069 - VSS_XTD29_0 */
 715         { 21070, 0x0009 },   /* R21070 - VSS_XTD30_1 */
 716         { 21071, 0x87C0 },   /* R21071 - VSS_XTD30_0 */
 717         { 21072, 0x00FD },   /* R21072 - VSS_XTD31_1 */
 718         { 21073, 0x2C40 },   /* R21073 - VSS_XTD31_0 */
 719         { 21074, 0x0009 },   /* R21074 - VSS_XTD32_1 */
 720         { 21075, 0x4800 },   /* R21075 - VSS_XTD32_0 */
 721         { 21076, 0x0003 },   /* R21076 - VSS_XTS1_1 */
 722         { 21077, 0x5F40 },   /* R21077 - VSS_XTS1_0 */
 723         { 21078, 0x0000 },   /* R21078 - VSS_XTS2_1 */
 724         { 21079, 0x8700 },   /* R21079 - VSS_XTS2_0 */
 725         { 21080, 0x00FA },   /* R21080 - VSS_XTS3_1 */
 726         { 21081, 0xE4C0 },   /* R21081 - VSS_XTS3_0 */
 727         { 21082, 0x0000 },   /* R21082 - VSS_XTS4_1 */
 728         { 21083, 0x0B40 },   /* R21083 - VSS_XTS4_0 */
 729         { 21084, 0x0004 },   /* R21084 - VSS_XTS5_1 */
 730         { 21085, 0xE180 },   /* R21085 - VSS_XTS5_0 */
 731         { 21086, 0x0001 },   /* R21086 - VSS_XTS6_1 */
 732         { 21087, 0x1F40 },   /* R21087 - VSS_XTS6_0 */
 733         { 21088, 0x00F8 },   /* R21088 - VSS_XTS7_1 */
 734         { 21089, 0xB000 },   /* R21089 - VSS_XTS7_0 */
 735         { 21090, 0x00FB },   /* R21090 - VSS_XTS8_1 */
 736         { 21091, 0xCBC0 },   /* R21091 - VSS_XTS8_0 */
 737         { 21092, 0x0004 },   /* R21092 - VSS_XTS9_1 */
 738         { 21093, 0xF380 },   /* R21093 - VSS_XTS9_0 */
 739         { 21094, 0x0007 },   /* R21094 - VSS_XTS10_1 */
 740         { 21095, 0xDF40 },   /* R21095 - VSS_XTS10_0 */
 741         { 21096, 0x00FF },   /* R21096 - VSS_XTS11_1 */
 742         { 21097, 0x0700 },   /* R21097 - VSS_XTS11_0 */
 743         { 21098, 0x00EF },   /* R21098 - VSS_XTS12_1 */
 744         { 21099, 0xD700 },   /* R21099 - VSS_XTS12_0 */
 745         { 21100, 0x00FB },   /* R21100 - VSS_XTS13_1 */
 746         { 21101, 0xAF40 },   /* R21101 - VSS_XTS13_0 */
 747         { 21102, 0x0010 },   /* R21102 - VSS_XTS14_1 */
 748         { 21103, 0x8A80 },   /* R21103 - VSS_XTS14_0 */
 749         { 21104, 0x0011 },   /* R21104 - VSS_XTS15_1 */
 750         { 21105, 0x07C0 },   /* R21105 - VSS_XTS15_0 */
 751         { 21106, 0x00E0 },   /* R21106 - VSS_XTS16_1 */
 752         { 21107, 0x0800 },   /* R21107 - VSS_XTS16_0 */
 753         { 21108, 0x00D2 },   /* R21108 - VSS_XTS17_1 */
 754         { 21109, 0x7600 },   /* R21109 - VSS_XTS17_0 */
 755         { 21110, 0x0020 },   /* R21110 - VSS_XTS18_1 */
 756         { 21111, 0xCF40 },   /* R21111 - VSS_XTS18_0 */
 757         { 21112, 0x0030 },   /* R21112 - VSS_XTS19_1 */
 758         { 21113, 0x2340 },   /* R21113 - VSS_XTS19_0 */
 759         { 21114, 0x00FD },   /* R21114 - VSS_XTS20_1 */
 760         { 21115, 0x69C0 },   /* R21115 - VSS_XTS20_0 */
 761         { 21116, 0x0028 },   /* R21116 - VSS_XTS21_1 */
 762         { 21117, 0x3500 },   /* R21117 - VSS_XTS21_0 */
 763         { 21118, 0x0006 },   /* R21118 - VSS_XTS22_1 */
 764         { 21119, 0x3300 },   /* R21119 - VSS_XTS22_0 */
 765         { 21120, 0x00D9 },   /* R21120 - VSS_XTS23_1 */
 766         { 21121, 0xF6C0 },   /* R21121 - VSS_XTS23_0 */
 767         { 21122, 0x00F3 },   /* R21122 - VSS_XTS24_1 */
 768         { 21123, 0x3340 },   /* R21123 - VSS_XTS24_0 */
 769         { 21124, 0x000F },   /* R21124 - VSS_XTS25_1 */
 770         { 21125, 0x4200 },   /* R21125 - VSS_XTS25_0 */
 771         { 21126, 0x0004 },   /* R21126 - VSS_XTS26_1 */
 772         { 21127, 0x0C80 },   /* R21127 - VSS_XTS26_0 */
 773         { 21128, 0x00FB },   /* R21128 - VSS_XTS27_1 */
 774         { 21129, 0x3F80 },   /* R21129 - VSS_XTS27_0 */
 775         { 21130, 0x00F7 },   /* R21130 - VSS_XTS28_1 */
 776         { 21131, 0x57C0 },   /* R21131 - VSS_XTS28_0 */
 777         { 21132, 0x0003 },   /* R21132 - VSS_XTS29_1 */
 778         { 21133, 0x5400 },   /* R21133 - VSS_XTS29_0 */
 779         { 21134, 0x0000 },   /* R21134 - VSS_XTS30_1 */
 780         { 21135, 0xC6C0 },   /* R21135 - VSS_XTS30_0 */
 781         { 21136, 0x0003 },   /* R21136 - VSS_XTS31_1 */
 782         { 21137, 0x12C0 },   /* R21137 - VSS_XTS31_0 */
 783         { 21138, 0x00FD },   /* R21138 - VSS_XTS32_1 */
 784         { 21139, 0x8580 },   /* R21139 - VSS_XTS32_0 */
 785 };
 786
 787 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
 788 {
 789         switch (reg) {
 790         case WM8962_CLOCKING1:
 791         case WM8962_SOFTWARE_RESET:
 792         case WM8962_THERMAL_SHUTDOWN_STATUS:
 793         case WM8962_ADDITIONAL_CONTROL_4:
 794         case WM8962_DC_SERVO_6:
 795         case WM8962_INTERRUPT_STATUS_1:
 796         case WM8962_INTERRUPT_STATUS_2:
 797         case WM8962_DSP2_EXECCONTROL:
 798                 return true;
 799         default:
 800                 return false;
 801         }
 802 }
 803
 804 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
 805 {
 806         switch (reg) {
 807         case WM8962_LEFT_INPUT_VOLUME:
 808         case WM8962_RIGHT_INPUT_VOLUME:
 809         case WM8962_HPOUTL_VOLUME:
 810         case WM8962_HPOUTR_VOLUME:
 811         case WM8962_CLOCKING1:
 812         case WM8962_ADC_DAC_CONTROL_1:
 813         case WM8962_ADC_DAC_CONTROL_2:
 814         case WM8962_AUDIO_INTERFACE_0:
 815         case WM8962_CLOCKING2:
 816         case WM8962_AUDIO_INTERFACE_1:
 817         case WM8962_LEFT_DAC_VOLUME:
 818         case WM8962_RIGHT_DAC_VOLUME:
 819         case WM8962_AUDIO_INTERFACE_2:
 820         case WM8962_SOFTWARE_RESET:
 821         case WM8962_ALC1:
 822         case WM8962_ALC2:
 823         case WM8962_ALC3:
 824         case WM8962_NOISE_GATE:
 825         case WM8962_LEFT_ADC_VOLUME:
 826         case WM8962_RIGHT_ADC_VOLUME:
 827         case WM8962_ADDITIONAL_CONTROL_1:
 828         case WM8962_ADDITIONAL_CONTROL_2:
 829         case WM8962_PWR_MGMT_1:
 830         case WM8962_PWR_MGMT_2:
 831         case WM8962_ADDITIONAL_CONTROL_3:
 832         case WM8962_ANTI_POP:
 833         case WM8962_CLOCKING_3:
 834         case WM8962_INPUT_MIXER_CONTROL_1:
 835         case WM8962_LEFT_INPUT_MIXER_VOLUME:
 836         case WM8962_RIGHT_INPUT_MIXER_VOLUME:
 837         case WM8962_INPUT_MIXER_CONTROL_2:
 838         case WM8962_INPUT_BIAS_CONTROL:
 839         case WM8962_LEFT_INPUT_PGA_CONTROL:
 840         case WM8962_RIGHT_INPUT_PGA_CONTROL:
 841         case WM8962_SPKOUTL_VOLUME:
 842         case WM8962_SPKOUTR_VOLUME:
 843         case WM8962_THERMAL_SHUTDOWN_STATUS:
 844         case WM8962_ADDITIONAL_CONTROL_4:
 845         case WM8962_CLASS_D_CONTROL_1:
 846         case WM8962_CLASS_D_CONTROL_2:
 847         case WM8962_CLOCKING_4:
 848         case WM8962_DAC_DSP_MIXING_1:
 849         case WM8962_DAC_DSP_MIXING_2:
 850         case WM8962_DC_SERVO_0:
 851         case WM8962_DC_SERVO_1:
 852         case WM8962_DC_SERVO_4:
 853         case WM8962_DC_SERVO_6:
 854         case WM8962_ANALOGUE_PGA_BIAS:
 855         case WM8962_ANALOGUE_HP_0:
 856         case WM8962_ANALOGUE_HP_2:
 857         case WM8962_CHARGE_PUMP_1:
 858         case WM8962_CHARGE_PUMP_B:
 859         case WM8962_WRITE_SEQUENCER_CONTROL_1:
 860         case WM8962_WRITE_SEQUENCER_CONTROL_2:
 861         case WM8962_WRITE_SEQUENCER_CONTROL_3:
 862         case WM8962_CONTROL_INTERFACE:
 863         case WM8962_MIXER_ENABLES:
 864         case WM8962_HEADPHONE_MIXER_1:
 865         case WM8962_HEADPHONE_MIXER_2:
 866         case WM8962_HEADPHONE_MIXER_3:
 867         case WM8962_HEADPHONE_MIXER_4:
 868         case WM8962_SPEAKER_MIXER_1:
 869         case WM8962_SPEAKER_MIXER_2:
 870         case WM8962_SPEAKER_MIXER_3:
 871         case WM8962_SPEAKER_MIXER_4:
 872         case WM8962_SPEAKER_MIXER_5:
 873         case WM8962_BEEP_GENERATOR_1:
 874         case WM8962_OSCILLATOR_TRIM_3:
 875         case WM8962_OSCILLATOR_TRIM_4:
 876         case WM8962_OSCILLATOR_TRIM_7:
 877         case WM8962_ANALOGUE_CLOCKING1:
 878         case WM8962_ANALOGUE_CLOCKING2:
 879         case WM8962_ANALOGUE_CLOCKING3:
 880         case WM8962_PLL_SOFTWARE_RESET:
 881         case WM8962_PLL2:
 882         case WM8962_PLL_4:
 883         case WM8962_PLL_9:
 884         case WM8962_PLL_10:
 885         case WM8962_PLL_11:
 886         case WM8962_PLL_12:
 887         case WM8962_PLL_13:
 888         case WM8962_PLL_14:
 889         case WM8962_PLL_15:
 890         case WM8962_PLL_16:
 891         case WM8962_FLL_CONTROL_1:
 892         case WM8962_FLL_CONTROL_2:
 893         case WM8962_FLL_CONTROL_3:
 894         case WM8962_FLL_CONTROL_5:
 895         case WM8962_FLL_CONTROL_6:
 896         case WM8962_FLL_CONTROL_7:
 897         case WM8962_FLL_CONTROL_8:
 898         case WM8962_GENERAL_TEST_1:
 899         case WM8962_DF1:
 900         case WM8962_DF2:
 901         case WM8962_DF3:
 902         case WM8962_DF4:
 903         case WM8962_DF5:
 904         case WM8962_DF6:
 905         case WM8962_DF7:
 906         case WM8962_LHPF1:
 907         case WM8962_LHPF2:
 908         case WM8962_THREED1:
 909         case WM8962_THREED2:
 910         case WM8962_THREED3:
 911         case WM8962_THREED4:
 912         case WM8962_DRC_1:
 913         case WM8962_DRC_2:
 914         case WM8962_DRC_3:
 915         case WM8962_DRC_4:
 916         case WM8962_DRC_5:
 917         case WM8962_TLOOPBACK:
 918         case WM8962_EQ1:
 919         case WM8962_EQ2:
 920         case WM8962_EQ3:
 921         case WM8962_EQ4:
 922         case WM8962_EQ5:
 923         case WM8962_EQ6:
 924         case WM8962_EQ7:
 925         case WM8962_EQ8:
 926         case WM8962_EQ9:
 927         case WM8962_EQ10:
 928         case WM8962_EQ11:
 929         case WM8962_EQ12:
 930         case WM8962_EQ13:
 931         case WM8962_EQ14:
 932         case WM8962_EQ15:
 933         case WM8962_EQ16:
 934         case WM8962_EQ17:
 935         case WM8962_EQ18:
 936         case WM8962_EQ19:
 937         case WM8962_EQ20:
 938         case WM8962_EQ21:
 939         case WM8962_EQ22:
 940         case WM8962_EQ23:
 941         case WM8962_EQ24:
 942         case WM8962_EQ25:
 943         case WM8962_EQ26:
 944         case WM8962_EQ27:
 945         case WM8962_EQ28:
 946         case WM8962_EQ29:
 947         case WM8962_EQ30:
 948         case WM8962_EQ31:
 949         case WM8962_EQ32:
 950         case WM8962_EQ33:
 951         case WM8962_EQ34:
 952         case WM8962_EQ35:
 953         case WM8962_EQ36:
 954         case WM8962_EQ37:
 955         case WM8962_EQ38:
 956         case WM8962_EQ39:
 957         case WM8962_EQ40:
 958         case WM8962_EQ41:
 959         case WM8962_GPIO_2:
 960         case WM8962_GPIO_3:
 961         case WM8962_GPIO_5:
 962         case WM8962_GPIO_6:
 963         case WM8962_INTERRUPT_STATUS_1:
 964         case WM8962_INTERRUPT_STATUS_2:
 965         case WM8962_INTERRUPT_STATUS_1_MASK:
 966         case WM8962_INTERRUPT_STATUS_2_MASK:
 967         case WM8962_INTERRUPT_CONTROL:
 968         case WM8962_IRQ_DEBOUNCE:
 969         case WM8962_MICINT_SOURCE_POL:
 970         case WM8962_DSP2_POWER_MANAGEMENT:
 971         case WM8962_DSP2_EXECCONTROL:
 972         case WM8962_DSP2_INSTRUCTION_RAM_0:
 973         case WM8962_DSP2_ADDRESS_RAM_2:
 974         case WM8962_DSP2_ADDRESS_RAM_1:
 975         case WM8962_DSP2_ADDRESS_RAM_0:
 976         case WM8962_DSP2_DATA1_RAM_1:
 977         case WM8962_DSP2_DATA1_RAM_0:
 978         case WM8962_DSP2_DATA2_RAM_1:
 979         case WM8962_DSP2_DATA2_RAM_0:
 980         case WM8962_DSP2_DATA3_RAM_1:
 981         case WM8962_DSP2_DATA3_RAM_0:
 982         case WM8962_DSP2_COEFF_RAM_0:
 983         case WM8962_RETUNEADC_SHARED_COEFF_1:
 984         case WM8962_RETUNEADC_SHARED_COEFF_0:
 985         case WM8962_RETUNEDAC_SHARED_COEFF_1:
 986         case WM8962_RETUNEDAC_SHARED_COEFF_0:
 987         case WM8962_SOUNDSTAGE_ENABLES_1:
 988         case WM8962_SOUNDSTAGE_ENABLES_0:
 989         case WM8962_HDBASS_AI_1:
 990         case WM8962_HDBASS_AI_0:
 991         case WM8962_HDBASS_AR_1:
 992         case WM8962_HDBASS_AR_0:
 993         case WM8962_HDBASS_B_1:
 994         case WM8962_HDBASS_B_0:
 995         case WM8962_HDBASS_K_1:
 996         case WM8962_HDBASS_K_0:
 997         case WM8962_HDBASS_N1_1:
 998         case WM8962_HDBASS_N1_0:
 999         case WM8962_HDBASS_N2_1:
1000         case WM8962_HDBASS_N2_0:
1001         case WM8962_HDBASS_N3_1:
1002         case WM8962_HDBASS_N3_0:
1003         case WM8962_HDBASS_N4_1:
1004         case WM8962_HDBASS_N4_0:
1005         case WM8962_HDBASS_N5_1:
1006         case WM8962_HDBASS_N5_0:
1007         case WM8962_HDBASS_X1_1:
1008         case WM8962_HDBASS_X1_0:
1009         case WM8962_HDBASS_X2_1:
1010         case WM8962_HDBASS_X2_0:
1011         case WM8962_HDBASS_X3_1:
1012         case WM8962_HDBASS_X3_0:
1013         case WM8962_HDBASS_ATK_1:
1014         case WM8962_HDBASS_ATK_0:
1015         case WM8962_HDBASS_DCY_1:
1016         case WM8962_HDBASS_DCY_0:
1017         case WM8962_HDBASS_PG_1:
1018         case WM8962_HDBASS_PG_0:
1019         case WM8962_HPF_C_1:
1020         case WM8962_HPF_C_0:
1021         case WM8962_ADCL_RETUNE_C1_1:
1022         case WM8962_ADCL_RETUNE_C1_0:
1023         case WM8962_ADCL_RETUNE_C2_1:
1024         case WM8962_ADCL_RETUNE_C2_0:
1025         case WM8962_ADCL_RETUNE_C3_1:
1026         case WM8962_ADCL_RETUNE_C3_0:
1027         case WM8962_ADCL_RETUNE_C4_1:
1028         case WM8962_ADCL_RETUNE_C4_0:
1029         case WM8962_ADCL_RETUNE_C5_1:
1030         case WM8962_ADCL_RETUNE_C5_0:
1031         case WM8962_ADCL_RETUNE_C6_1:
1032         case WM8962_ADCL_RETUNE_C6_0:
1033         case WM8962_ADCL_RETUNE_C7_1:
1034         case WM8962_ADCL_RETUNE_C7_0:
1035         case WM8962_ADCL_RETUNE_C8_1:
1036         case WM8962_ADCL_RETUNE_C8_0:
1037         case WM8962_ADCL_RETUNE_C9_1:
1038         case WM8962_ADCL_RETUNE_C9_0:
1039         case WM8962_ADCL_RETUNE_C10_1:
1040         case WM8962_ADCL_RETUNE_C10_0:
1041         case WM8962_ADCL_RETUNE_C11_1:
1042         case WM8962_ADCL_RETUNE_C11_0:
1043         case WM8962_ADCL_RETUNE_C12_1:
1044         case WM8962_ADCL_RETUNE_C12_0:
1045         case WM8962_ADCL_RETUNE_C13_1:
1046         case WM8962_ADCL_RETUNE_C13_0:
1047         case WM8962_ADCL_RETUNE_C14_1:
1048         case WM8962_ADCL_RETUNE_C14_0:
1049         case WM8962_ADCL_RETUNE_C15_1:
1050         case WM8962_ADCL_RETUNE_C15_0:
1051         case WM8962_ADCL_RETUNE_C16_1:
1052         case WM8962_ADCL_RETUNE_C16_0:
1053         case WM8962_ADCL_RETUNE_C17_1:
1054         case WM8962_ADCL_RETUNE_C17_0:
1055         case WM8962_ADCL_RETUNE_C18_1:
1056         case WM8962_ADCL_RETUNE_C18_0:
1057         case WM8962_ADCL_RETUNE_C19_1:
1058         case WM8962_ADCL_RETUNE_C19_0:
1059         case WM8962_ADCL_RETUNE_C20_1:
1060         case WM8962_ADCL_RETUNE_C20_0:
1061         case WM8962_ADCL_RETUNE_C21_1:
1062         case WM8962_ADCL_RETUNE_C21_0:
1063         case WM8962_ADCL_RETUNE_C22_1:
1064         case WM8962_ADCL_RETUNE_C22_0:
1065         case WM8962_ADCL_RETUNE_C23_1:
1066         case WM8962_ADCL_RETUNE_C23_0:
1067         case WM8962_ADCL_RETUNE_C24_1:
1068         case WM8962_ADCL_RETUNE_C24_0:
1069         case WM8962_ADCL_RETUNE_C25_1:
1070         case WM8962_ADCL_RETUNE_C25_0:
1071         case WM8962_ADCL_RETUNE_C26_1:
1072         case WM8962_ADCL_RETUNE_C26_0:
1073         case WM8962_ADCL_RETUNE_C27_1:
1074         case WM8962_ADCL_RETUNE_C27_0:
1075         case WM8962_ADCL_RETUNE_C28_1:
1076         case WM8962_ADCL_RETUNE_C28_0:
1077         case WM8962_ADCL_RETUNE_C29_1:
1078         case WM8962_ADCL_RETUNE_C29_0:
1079         case WM8962_ADCL_RETUNE_C30_1:
1080         case WM8962_ADCL_RETUNE_C30_0:
1081         case WM8962_ADCL_RETUNE_C31_1:
1082         case WM8962_ADCL_RETUNE_C31_0:
1083         case WM8962_ADCL_RETUNE_C32_1:
1084         case WM8962_ADCL_RETUNE_C32_0:
1085         case WM8962_RETUNEADC_PG2_1:
1086         case WM8962_RETUNEADC_PG2_0:
1087         case WM8962_RETUNEADC_PG_1:
1088         case WM8962_RETUNEADC_PG_0:
1089         case WM8962_ADCR_RETUNE_C1_1:
1090         case WM8962_ADCR_RETUNE_C1_0:
1091         case WM8962_ADCR_RETUNE_C2_1:
1092         case WM8962_ADCR_RETUNE_C2_0:
1093         case WM8962_ADCR_RETUNE_C3_1:
1094         case WM8962_ADCR_RETUNE_C3_0:
1095         case WM8962_ADCR_RETUNE_C4_1:
1096         case WM8962_ADCR_RETUNE_C4_0:
1097         case WM8962_ADCR_RETUNE_C5_1:
1098         case WM8962_ADCR_RETUNE_C5_0:
1099         case WM8962_ADCR_RETUNE_C6_1:
1100         case WM8962_ADCR_RETUNE_C6_0:
1101         case WM8962_ADCR_RETUNE_C7_1:
1102         case WM8962_ADCR_RETUNE_C7_0:
1103         case WM8962_ADCR_RETUNE_C8_1:
1104         case WM8962_ADCR_RETUNE_C8_0:
1105         case WM8962_ADCR_RETUNE_C9_1:
1106         case WM8962_ADCR_RETUNE_C9_0:
1107         case WM8962_ADCR_RETUNE_C10_1:
1108         case WM8962_ADCR_RETUNE_C10_0:
1109         case WM8962_ADCR_RETUNE_C11_1:
1110         case WM8962_ADCR_RETUNE_C11_0:
1111         case WM8962_ADCR_RETUNE_C12_1:
1112         case WM8962_ADCR_RETUNE_C12_0:
1113         case WM8962_ADCR_RETUNE_C13_1:
1114         case WM8962_ADCR_RETUNE_C13_0:
1115         case WM8962_ADCR_RETUNE_C14_1:
1116         case WM8962_ADCR_RETUNE_C14_0:
1117         case WM8962_ADCR_RETUNE_C15_1:
1118         case WM8962_ADCR_RETUNE_C15_0:
1119         case WM8962_ADCR_RETUNE_C16_1:
1120         case WM8962_ADCR_RETUNE_C16_0:
1121         case WM8962_ADCR_RETUNE_C17_1:
1122         case WM8962_ADCR_RETUNE_C17_0:
1123         case WM8962_ADCR_RETUNE_C18_1:
1124         case WM8962_ADCR_RETUNE_C18_0:
1125         case WM8962_ADCR_RETUNE_C19_1:
1126         case WM8962_ADCR_RETUNE_C19_0:
1127         case WM8962_ADCR_RETUNE_C20_1:
1128         case WM8962_ADCR_RETUNE_C20_0:
1129         case WM8962_ADCR_RETUNE_C21_1:
1130         case WM8962_ADCR_RETUNE_C21_0:
1131         case WM8962_ADCR_RETUNE_C22_1:
1132         case WM8962_ADCR_RETUNE_C22_0:
1133         case WM8962_ADCR_RETUNE_C23_1:
1134         case WM8962_ADCR_RETUNE_C23_0:
1135         case WM8962_ADCR_RETUNE_C24_1:
1136         case WM8962_ADCR_RETUNE_C24_0:
1137         case WM8962_ADCR_RETUNE_C25_1:
1138         case WM8962_ADCR_RETUNE_C25_0:
1139         case WM8962_ADCR_RETUNE_C26_1:
1140         case WM8962_ADCR_RETUNE_C26_0:
1141         case WM8962_ADCR_RETUNE_C27_1:
1142         case WM8962_ADCR_RETUNE_C27_0:
1143         case WM8962_ADCR_RETUNE_C28_1:
1144         case WM8962_ADCR_RETUNE_C28_0:
1145         case WM8962_ADCR_RETUNE_C29_1:
1146         case WM8962_ADCR_RETUNE_C29_0:
1147         case WM8962_ADCR_RETUNE_C30_1:
1148         case WM8962_ADCR_RETUNE_C30_0:
1149         case WM8962_ADCR_RETUNE_C31_1:
1150         case WM8962_ADCR_RETUNE_C31_0:
1151         case WM8962_ADCR_RETUNE_C32_1:
1152         case WM8962_ADCR_RETUNE_C32_0:
1153         case WM8962_DACL_RETUNE_C1_1:
1154         case WM8962_DACL_RETUNE_C1_0:
1155         case WM8962_DACL_RETUNE_C2_1:
1156         case WM8962_DACL_RETUNE_C2_0:
1157         case WM8962_DACL_RETUNE_C3_1:
1158         case WM8962_DACL_RETUNE_C3_0:
1159         case WM8962_DACL_RETUNE_C4_1:
1160         case WM8962_DACL_RETUNE_C4_0:
1161         case WM8962_DACL_RETUNE_C5_1:
1162         case WM8962_DACL_RETUNE_C5_0:
1163         case WM8962_DACL_RETUNE_C6_1:
1164         case WM8962_DACL_RETUNE_C6_0:
1165         case WM8962_DACL_RETUNE_C7_1:
1166         case WM8962_DACL_RETUNE_C7_0:
1167         case WM8962_DACL_RETUNE_C8_1:
1168         case WM8962_DACL_RETUNE_C8_0:
1169         case WM8962_DACL_RETUNE_C9_1:
1170         case WM8962_DACL_RETUNE_C9_0:
1171         case WM8962_DACL_RETUNE_C10_1:
1172         case WM8962_DACL_RETUNE_C10_0:
1173         case WM8962_DACL_RETUNE_C11_1:
1174         case WM8962_DACL_RETUNE_C11_0:
1175         case WM8962_DACL_RETUNE_C12_1:
1176         case WM8962_DACL_RETUNE_C12_0:
1177         case WM8962_DACL_RETUNE_C13_1:
1178         case WM8962_DACL_RETUNE_C13_0:
1179         case WM8962_DACL_RETUNE_C14_1:
1180         case WM8962_DACL_RETUNE_C14_0:
1181         case WM8962_DACL_RETUNE_C15_1:
1182         case WM8962_DACL_RETUNE_C15_0:
1183         case WM8962_DACL_RETUNE_C16_1:
1184         case WM8962_DACL_RETUNE_C16_0:
1185         case WM8962_DACL_RETUNE_C17_1:
1186         case WM8962_DACL_RETUNE_C17_0:
1187         case WM8962_DACL_RETUNE_C18_1:
1188         case WM8962_DACL_RETUNE_C18_0:
1189         case WM8962_DACL_RETUNE_C19_1:
1190         case WM8962_DACL_RETUNE_C19_0:
1191         case WM8962_DACL_RETUNE_C20_1:
1192         case WM8962_DACL_RETUNE_C20_0:
1193         case WM8962_DACL_RETUNE_C21_1:
1194         case WM8962_DACL_RETUNE_C21_0:
1195         case WM8962_DACL_RETUNE_C22_1:
1196         case WM8962_DACL_RETUNE_C22_0:
1197         case WM8962_DACL_RETUNE_C23_1:
1198         case WM8962_DACL_RETUNE_C23_0:
1199         case WM8962_DACL_RETUNE_C24_1:
1200         case WM8962_DACL_RETUNE_C24_0:
1201         case WM8962_DACL_RETUNE_C25_1:
1202         case WM8962_DACL_RETUNE_C25_0:
1203         case WM8962_DACL_RETUNE_C26_1:
1204         case WM8962_DACL_RETUNE_C26_0:
1205         case WM8962_DACL_RETUNE_C27_1:
1206         case WM8962_DACL_RETUNE_C27_0:
1207         case WM8962_DACL_RETUNE_C28_1:
1208         case WM8962_DACL_RETUNE_C28_0:
1209         case WM8962_DACL_RETUNE_C29_1:
1210         case WM8962_DACL_RETUNE_C29_0:
1211         case WM8962_DACL_RETUNE_C30_1:
1212         case WM8962_DACL_RETUNE_C30_0:
1213         case WM8962_DACL_RETUNE_C31_1:
1214         case WM8962_DACL_RETUNE_C31_0:
1215         case WM8962_DACL_RETUNE_C32_1:
1216         case WM8962_DACL_RETUNE_C32_0:
1217         case WM8962_RETUNEDAC_PG2_1:
1218         case WM8962_RETUNEDAC_PG2_0:
1219         case WM8962_RETUNEDAC_PG_1:
1220         case WM8962_RETUNEDAC_PG_0:
1221         case WM8962_DACR_RETUNE_C1_1:
1222         case WM8962_DACR_RETUNE_C1_0:
1223         case WM8962_DACR_RETUNE_C2_1:
1224         case WM8962_DACR_RETUNE_C2_0:
1225         case WM8962_DACR_RETUNE_C3_1:
1226         case WM8962_DACR_RETUNE_C3_0:
1227         case WM8962_DACR_RETUNE_C4_1:
1228         case WM8962_DACR_RETUNE_C4_0:
1229         case WM8962_DACR_RETUNE_C5_1:
1230         case WM8962_DACR_RETUNE_C5_0:
1231         case WM8962_DACR_RETUNE_C6_1:
1232         case WM8962_DACR_RETUNE_C6_0:
1233         case WM8962_DACR_RETUNE_C7_1:
1234         case WM8962_DACR_RETUNE_C7_0:
1235         case WM8962_DACR_RETUNE_C8_1:
1236         case WM8962_DACR_RETUNE_C8_0:
1237         case WM8962_DACR_RETUNE_C9_1:
1238         case WM8962_DACR_RETUNE_C9_0:
1239         case WM8962_DACR_RETUNE_C10_1:
1240         case WM8962_DACR_RETUNE_C10_0:
1241         case WM8962_DACR_RETUNE_C11_1:
1242         case WM8962_DACR_RETUNE_C11_0:
1243         case WM8962_DACR_RETUNE_C12_1:
1244         case WM8962_DACR_RETUNE_C12_0:
1245         case WM8962_DACR_RETUNE_C13_1:
1246         case WM8962_DACR_RETUNE_C13_0:
1247         case WM8962_DACR_RETUNE_C14_1:
1248         case WM8962_DACR_RETUNE_C14_0:
1249         case WM8962_DACR_RETUNE_C15_1:
1250         case WM8962_DACR_RETUNE_C15_0:
1251         case WM8962_DACR_RETUNE_C16_1:
1252         case WM8962_DACR_RETUNE_C16_0:
1253         case WM8962_DACR_RETUNE_C17_1:
1254         case WM8962_DACR_RETUNE_C17_0:
1255         case WM8962_DACR_RETUNE_C18_1:
1256         case WM8962_DACR_RETUNE_C18_0:
1257         case WM8962_DACR_RETUNE_C19_1:
1258         case WM8962_DACR_RETUNE_C19_0:
1259         case WM8962_DACR_RETUNE_C20_1:
1260         case WM8962_DACR_RETUNE_C20_0:
1261         case WM8962_DACR_RETUNE_C21_1:
1262         case WM8962_DACR_RETUNE_C21_0:
1263         case WM8962_DACR_RETUNE_C22_1:
1264         case WM8962_DACR_RETUNE_C22_0:
1265         case WM8962_DACR_RETUNE_C23_1:
1266         case WM8962_DACR_RETUNE_C23_0:
1267         case WM8962_DACR_RETUNE_C24_1:
1268         case WM8962_DACR_RETUNE_C24_0:
1269         case WM8962_DACR_RETUNE_C25_1:
1270         case WM8962_DACR_RETUNE_C25_0:
1271         case WM8962_DACR_RETUNE_C26_1:
1272         case WM8962_DACR_RETUNE_C26_0:
1273         case WM8962_DACR_RETUNE_C27_1:
1274         case WM8962_DACR_RETUNE_C27_0:
1275         case WM8962_DACR_RETUNE_C28_1:
1276         case WM8962_DACR_RETUNE_C28_0:
1277         case WM8962_DACR_RETUNE_C29_1:
1278         case WM8962_DACR_RETUNE_C29_0:
1279         case WM8962_DACR_RETUNE_C30_1:
1280         case WM8962_DACR_RETUNE_C30_0:
1281         case WM8962_DACR_RETUNE_C31_1:
1282         case WM8962_DACR_RETUNE_C31_0:
1283         case WM8962_DACR_RETUNE_C32_1:
1284         case WM8962_DACR_RETUNE_C32_0:
1285         case WM8962_VSS_XHD2_1:
1286         case WM8962_VSS_XHD2_0:
1287         case WM8962_VSS_XHD3_1:
1288         case WM8962_VSS_XHD3_0:
1289         case WM8962_VSS_XHN1_1:
1290         case WM8962_VSS_XHN1_0:
1291         case WM8962_VSS_XHN2_1:
1292         case WM8962_VSS_XHN2_0:
1293         case WM8962_VSS_XHN3_1:
1294         case WM8962_VSS_XHN3_0:
1295         case WM8962_VSS_XLA_1:
1296         case WM8962_VSS_XLA_0:
1297         case WM8962_VSS_XLB_1:
1298         case WM8962_VSS_XLB_0:
1299         case WM8962_VSS_XLG_1:
1300         case WM8962_VSS_XLG_0:
1301         case WM8962_VSS_PG2_1:
1302         case WM8962_VSS_PG2_0:
1303         case WM8962_VSS_PG_1:
1304         case WM8962_VSS_PG_0:
1305         case WM8962_VSS_XTD1_1:
1306         case WM8962_VSS_XTD1_0:
1307         case WM8962_VSS_XTD2_1:
1308         case WM8962_VSS_XTD2_0:
1309         case WM8962_VSS_XTD3_1:
1310         case WM8962_VSS_XTD3_0:
1311         case WM8962_VSS_XTD4_1:
1312         case WM8962_VSS_XTD4_0:
1313         case WM8962_VSS_XTD5_1:
1314         case WM8962_VSS_XTD5_0:
1315         case WM8962_VSS_XTD6_1:
1316         case WM8962_VSS_XTD6_0:
1317         case WM8962_VSS_XTD7_1:
1318         case WM8962_VSS_XTD7_0:
1319         case WM8962_VSS_XTD8_1:
1320         case WM8962_VSS_XTD8_0:
1321         case WM8962_VSS_XTD9_1:
1322         case WM8962_VSS_XTD9_0:
1323         case WM8962_VSS_XTD10_1:
1324         case WM8962_VSS_XTD10_0:
1325         case WM8962_VSS_XTD11_1:
1326         case WM8962_VSS_XTD11_0:
1327         case WM8962_VSS_XTD12_1:
1328         case WM8962_VSS_XTD12_0:
1329         case WM8962_VSS_XTD13_1:
1330         case WM8962_VSS_XTD13_0:
1331         case WM8962_VSS_XTD14_1:
1332         case WM8962_VSS_XTD14_0:
1333         case WM8962_VSS_XTD15_1:
1334         case WM8962_VSS_XTD15_0:
1335         case WM8962_VSS_XTD16_1:
1336         case WM8962_VSS_XTD16_0:
1337         case WM8962_VSS_XTD17_1:
1338         case WM8962_VSS_XTD17_0:
1339         case WM8962_VSS_XTD18_1:
1340         case WM8962_VSS_XTD18_0:
1341         case WM8962_VSS_XTD19_1:
1342         case WM8962_VSS_XTD19_0:
1343         case WM8962_VSS_XTD20_1:
1344         case WM8962_VSS_XTD20_0:
1345         case WM8962_VSS_XTD21_1:
1346         case WM8962_VSS_XTD21_0:
1347         case WM8962_VSS_XTD22_1:
1348         case WM8962_VSS_XTD22_0:
1349         case WM8962_VSS_XTD23_1:
1350         case WM8962_VSS_XTD23_0:
1351         case WM8962_VSS_XTD24_1:
1352         case WM8962_VSS_XTD24_0:
1353         case WM8962_VSS_XTD25_1:
1354         case WM8962_VSS_XTD25_0:
1355         case WM8962_VSS_XTD26_1:
1356         case WM8962_VSS_XTD26_0:
1357         case WM8962_VSS_XTD27_1:
1358         case WM8962_VSS_XTD27_0:
1359         case WM8962_VSS_XTD28_1:
1360         case WM8962_VSS_XTD28_0:
1361         case WM8962_VSS_XTD29_1:
1362         case WM8962_VSS_XTD29_0:
1363         case WM8962_VSS_XTD30_1:
1364         case WM8962_VSS_XTD30_0:
1365         case WM8962_VSS_XTD31_1:
1366         case WM8962_VSS_XTD31_0:
1367         case WM8962_VSS_XTD32_1:
1368         case WM8962_VSS_XTD32_0:
1369         case WM8962_VSS_XTS1_1:
1370         case WM8962_VSS_XTS1_0:
1371         case WM8962_VSS_XTS2_1:
1372         case WM8962_VSS_XTS2_0:
1373         case WM8962_VSS_XTS3_1:
1374         case WM8962_VSS_XTS3_0:
1375         case WM8962_VSS_XTS4_1:
1376         case WM8962_VSS_XTS4_0:
1377         case WM8962_VSS_XTS5_1:
1378         case WM8962_VSS_XTS5_0:
1379         case WM8962_VSS_XTS6_1:
1380         case WM8962_VSS_XTS6_0:
1381         case WM8962_VSS_XTS7_1:
1382         case WM8962_VSS_XTS7_0:
1383         case WM8962_VSS_XTS8_1:
1384         case WM8962_VSS_XTS8_0:
1385         case WM8962_VSS_XTS9_1:
1386         case WM8962_VSS_XTS9_0:
1387         case WM8962_VSS_XTS10_1:
1388         case WM8962_VSS_XTS10_0:
1389         case WM8962_VSS_XTS11_1:
1390         case WM8962_VSS_XTS11_0:
1391         case WM8962_VSS_XTS12_1:
1392         case WM8962_VSS_XTS12_0:
1393         case WM8962_VSS_XTS13_1:
1394         case WM8962_VSS_XTS13_0:
1395         case WM8962_VSS_XTS14_1:
1396         case WM8962_VSS_XTS14_0:
1397         case WM8962_VSS_XTS15_1:
1398         case WM8962_VSS_XTS15_0:
1399         case WM8962_VSS_XTS16_1:
1400         case WM8962_VSS_XTS16_0:
1401         case WM8962_VSS_XTS17_1:
1402         case WM8962_VSS_XTS17_0:
1403         case WM8962_VSS_XTS18_1:
1404         case WM8962_VSS_XTS18_0:
1405         case WM8962_VSS_XTS19_1:
1406         case WM8962_VSS_XTS19_0:
1407         case WM8962_VSS_XTS20_1:
1408         case WM8962_VSS_XTS20_0:
1409         case WM8962_VSS_XTS21_1:
1410         case WM8962_VSS_XTS21_0:
1411         case WM8962_VSS_XTS22_1:
1412         case WM8962_VSS_XTS22_0:
1413         case WM8962_VSS_XTS23_1:
1414         case WM8962_VSS_XTS23_0:
1415         case WM8962_VSS_XTS24_1:
1416         case WM8962_VSS_XTS24_0:
1417         case WM8962_VSS_XTS25_1:
1418         case WM8962_VSS_XTS25_0:
1419         case WM8962_VSS_XTS26_1:
1420         case WM8962_VSS_XTS26_0:
1421         case WM8962_VSS_XTS27_1:
1422         case WM8962_VSS_XTS27_0:
1423         case WM8962_VSS_XTS28_1:
1424         case WM8962_VSS_XTS28_0:
1425         case WM8962_VSS_XTS29_1:
1426         case WM8962_VSS_XTS29_0:
1427         case WM8962_VSS_XTS30_1:
1428         case WM8962_VSS_XTS30_0:
1429         case WM8962_VSS_XTS31_1:
1430         case WM8962_VSS_XTS31_0:
1431         case WM8962_VSS_XTS32_1:
1432         case WM8962_VSS_XTS32_0:
1433                 return true;
1434         default:
1435                 return false;
1436         }
1437 }
1438
1439 static int wm8962_reset(struct wm8962_priv *wm8962)
1440 {
1441         int ret;
1442
1443         ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1444         if (ret != 0)
1445                 return ret;
1446
1447         return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1448 }
1449
1450 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1451 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1452 static const DECLARE_TLV_DB_RANGE(mixinpga_tlv,
1453         0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1454         2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1455         3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1456         5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1457         6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0)
1458 );
1459 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1460 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1461 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1462 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1463 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1464 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1465 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1466 static const DECLARE_TLV_DB_RANGE(classd_tlv,
1467         0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1468         7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
1469 );
1470 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1471
1472 static int wm8962_dsp2_write_config(struct snd_soc_component *component)
1473 {
1474         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1475
1476         return regcache_sync_region(wm8962->regmap,
1477                                     WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1478 }
1479
1480 static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val)
1481 {
1482         u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME);
1483         u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME);
1484         u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1);
1485
1486         /* Mute the ADCs and DACs */
1487         snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0);
1488         snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1489         snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1490                             WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1491
1492         snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val);
1493
1494         /* Restore the ADCs and DACs */
1495         snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl);
1496         snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr);
1497         snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1498                             WM8962_DAC_MUTE, dac);
1499
1500         return 0;
1501 }
1502
1503 static int wm8962_dsp2_start(struct snd_soc_component *component)
1504 {
1505         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1506
1507         wm8962_dsp2_write_config(component);
1508
1509         snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1510
1511         wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1512
1513         return 0;
1514 }
1515
1516 static int wm8962_dsp2_stop(struct snd_soc_component *component)
1517 {
1518         wm8962_dsp2_set_enable(component, 0);
1519
1520         snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1521
1522         return 0;
1523 }
1524
1525 #define WM8962_DSP2_ENABLE(xname, xshift) \
1526 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1527         .info = wm8962_dsp2_ena_info, \
1528         .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1529         .private_value = xshift }
1530
1531 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1532                                 struct snd_ctl_elem_info *uinfo)
1533 {
1534         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1535
1536         uinfo->count = 1;
1537         uinfo->value.integer.min = 0;
1538         uinfo->value.integer.max = 1;
1539
1540         return 0;
1541 }
1542
1543 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1544                                struct snd_ctl_elem_value *ucontrol)
1545 {
1546         int shift = kcontrol->private_value;
1547         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1548         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1549
1550         ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1551
1552         return 0;
1553 }
1554
1555 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1556                                struct snd_ctl_elem_value *ucontrol)
1557 {
1558         int shift = kcontrol->private_value;
1559         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1560         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1561         int old = wm8962->dsp2_ena;
1562         int ret = 0;
1563         int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) &
1564                 WM8962_DSP2_ENA;
1565
1566         mutex_lock(&wm8962->dsp2_ena_lock);
1567
1568         if (ucontrol->value.integer.value[0])
1569                 wm8962->dsp2_ena |= 1 << shift;
1570         else
1571                 wm8962->dsp2_ena &= ~(1 << shift);
1572
1573         if (wm8962->dsp2_ena == old)
1574                 goto out;
1575
1576         ret = 1;
1577
1578         if (dsp2_running) {
1579                 if (wm8962->dsp2_ena)
1580                         wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1581                 else
1582                         wm8962_dsp2_stop(component);
1583         }
1584
1585 out:
1586         mutex_unlock(&wm8962->dsp2_ena_lock);
1587
1588         return ret;
1589 }
1590
1591 /* The VU bits for the headphones are in a different register to the mute
1592  * bits and only take effect on the PGA if it is actually powered.
1593  */
1594 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1595                             struct snd_ctl_elem_value *ucontrol)
1596 {
1597         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1598         int ret;
1599
1600         /* Apply the update (if any) */
1601         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1602         if (ret == 0)
1603                 return 0;
1604
1605         /* If the left PGA is enabled hit that VU bit... */
1606         ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
1607         if (ret & WM8962_HPOUTL_PGA_ENA) {
1608                 snd_soc_component_write(component, WM8962_HPOUTL_VOLUME,
1609                               snd_soc_component_read(component, WM8962_HPOUTL_VOLUME));
1610                 return 1;
1611         }
1612
1613         /* ...otherwise the right.  The VU is stereo. */
1614         if (ret & WM8962_HPOUTR_PGA_ENA)
1615                 snd_soc_component_write(component, WM8962_HPOUTR_VOLUME,
1616                               snd_soc_component_read(component, WM8962_HPOUTR_VOLUME));
1617
1618         return 1;
1619 }
1620
1621 /* The VU bits for the speakers are in a different register to the mute
1622  * bits and only take effect on the PGA if it is actually powered.
1623  */
1624 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1625                             struct snd_ctl_elem_value *ucontrol)
1626 {
1627         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1628         int ret;
1629
1630         /* Apply the update (if any) */
1631         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1632         if (ret == 0)
1633                 return 0;
1634
1635         /* If the left PGA is enabled hit that VU bit... */
1636         ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
1637         if (ret & WM8962_SPKOUTL_PGA_ENA) {
1638                 snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME,
1639                               snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME));
1640                 return 1;
1641         }
1642
1643         /* ...otherwise the right.  The VU is stereo. */
1644         if (ret & WM8962_SPKOUTR_PGA_ENA)
1645                 snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME,
1646                               snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME));
1647
1648         return 1;
1649 }
1650
1651 static const char *cap_hpf_mode_text[] = {
1652         "Hi-fi", "Application"
1653 };
1654
1655 static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
1656                             WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
1657
1658
1659 static const char *cap_lhpf_mode_text[] = {
1660         "LPF", "HPF"
1661 };
1662
1663 static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
1664                             WM8962_LHPF1, 1, cap_lhpf_mode_text);
1665
1666 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1667 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1668
1669 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1670                mixin_tlv),
1671 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1672                mixinpga_tlv),
1673 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1674                mixin_tlv),
1675
1676 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1677                mixin_tlv),
1678 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1679                mixinpga_tlv),
1680 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1681                mixin_tlv),
1682
1683 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1684                  WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1685 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1686                  WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1687 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1688              WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1689 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1690              WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1691 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1692 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1693 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1694 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1695 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1696
1697 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1698                  WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1699
1700 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1701                  WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1702 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1703 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1704 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1705 SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0),
1706 SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0),
1707
1708 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1709            5, 1, 0),
1710
1711 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1712
1713 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1714                  WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1715 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1716                snd_soc_get_volsw, wm8962_put_hp_sw),
1717 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1718              7, 1, 0),
1719 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1720                hp_tlv),
1721
1722 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1723              WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1724
1725 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1726                3, 7, 0, bypass_tlv),
1727 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1728                0, 7, 0, bypass_tlv),
1729 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1730                7, 1, 1, inmix_tlv),
1731 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1732                6, 1, 1, inmix_tlv),
1733
1734 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1735                3, 7, 0, bypass_tlv),
1736 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1737                0, 7, 0, bypass_tlv),
1738 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1739                7, 1, 1, inmix_tlv),
1740 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1741                6, 1, 1, inmix_tlv),
1742
1743 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1744                classd_tlv),
1745
1746 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1747 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1748                  WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1749 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1750                  WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1751 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1752                  WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1753 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1754                  WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1755 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1756                  WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1757 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1758 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1759
1760
1761 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1762 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1763
1764 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1765 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1766
1767 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1768 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1769
1770 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1771 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1772 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1773 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1774 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1775 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1776 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1777
1778 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1779                 WM8962_ALCR_ENA_SHIFT, 1, 0),
1780 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1781                 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
1782 };
1783
1784 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1785 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1786 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1787                snd_soc_get_volsw, wm8962_put_spk_sw),
1788 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1789
1790 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1791 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1792                3, 7, 0, bypass_tlv),
1793 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1794                0, 7, 0, bypass_tlv),
1795 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1796                7, 1, 1, inmix_tlv),
1797 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1798                6, 1, 1, inmix_tlv),
1799 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1800                7, 1, 0, inmix_tlv),
1801 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1802                6, 1, 0, inmix_tlv),
1803 };
1804
1805 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1806 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1807                  WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1808 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1809                snd_soc_get_volsw, wm8962_put_spk_sw),
1810 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1811              7, 1, 0),
1812
1813 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1814              WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1815
1816 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1817                3, 7, 0, bypass_tlv),
1818 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1819                0, 7, 0, bypass_tlv),
1820 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1821                7, 1, 1, inmix_tlv),
1822 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1823                6, 1, 1, inmix_tlv),
1824 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1825                7, 1, 0, inmix_tlv),
1826 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1827                6, 1, 0, inmix_tlv),
1828
1829 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1830                3, 7, 0, bypass_tlv),
1831 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1832                0, 7, 0, bypass_tlv),
1833 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1834                7, 1, 1, inmix_tlv),
1835 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1836                6, 1, 1, inmix_tlv),
1837 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1838                5, 1, 0, inmix_tlv),
1839 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1840                4, 1, 0, inmix_tlv),
1841 };
1842
1843 static int tp_event(struct snd_soc_dapm_widget *w,
1844                     struct snd_kcontrol *kcontrol, int event)
1845 {
1846         int ret, reg, val, mask;
1847         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1848
1849         ret = pm_runtime_resume_and_get(component->dev);
1850         if (ret < 0) {
1851                 dev_err(component->dev, "Failed to resume device: %d\n", ret);
1852                 return ret;
1853         }
1854
1855         reg = WM8962_ADDITIONAL_CONTROL_4;
1856
1857         if (!strcmp(w->name, "TEMP_HP")) {
1858                 mask = WM8962_TEMP_ENA_HP_MASK;
1859                 val = WM8962_TEMP_ENA_HP;
1860         } else if (!strcmp(w->name, "TEMP_SPK")) {
1861                 mask = WM8962_TEMP_ENA_SPK_MASK;
1862                 val = WM8962_TEMP_ENA_SPK;
1863         } else {
1864                 pm_runtime_put(component->dev);
1865                 return -EINVAL;
1866         }
1867
1868         switch (event) {
1869         case SND_SOC_DAPM_POST_PMD:
1870                 val = 0;
1871                 fallthrough;
1872         case SND_SOC_DAPM_POST_PMU:
1873                 ret = snd_soc_component_update_bits(component, reg, mask, val);
1874                 break;
1875         default:
1876                 WARN(1, "Invalid event %d\n", event);
1877                 pm_runtime_put(component->dev);
1878                 return -EINVAL;
1879         }
1880
1881         pm_runtime_put(component->dev);
1882
1883         return 0;
1884 }
1885
1886 static int cp_event(struct snd_soc_dapm_widget *w,
1887                     struct snd_kcontrol *kcontrol, int event)
1888 {
1889         switch (event) {
1890         case SND_SOC_DAPM_POST_PMU:
1891                 msleep(5);
1892                 break;
1893
1894         default:
1895                 WARN(1, "Invalid event %d\n", event);
1896                 return -EINVAL;
1897         }
1898
1899         return 0;
1900 }
1901
1902 static int hp_event(struct snd_soc_dapm_widget *w,
1903                     struct snd_kcontrol *kcontrol, int event)
1904 {
1905         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1906         int timeout;
1907         int reg;
1908         int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1909                         WM8962_DCS_STARTUP_DONE_HP1R);
1910
1911         switch (event) {
1912         case SND_SOC_DAPM_POST_PMU:
1913                 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1914                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1915                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1916                 udelay(20);
1917
1918                 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1919                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1920                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1921
1922                 /* Start the DC servo */
1923                 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1924                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1925                                     WM8962_HP1L_DCS_STARTUP |
1926                                     WM8962_HP1R_DCS_STARTUP,
1927                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1928                                     WM8962_HP1L_DCS_STARTUP |
1929                                     WM8962_HP1R_DCS_STARTUP);
1930
1931                 /* Wait for it to complete, should be well under 100ms */
1932                 timeout = 0;
1933                 do {
1934                         msleep(1);
1935                         reg = snd_soc_component_read(component, WM8962_DC_SERVO_6);
1936                         if (reg < 0) {
1937                                 dev_err(component->dev,
1938                                         "Failed to read DCS status: %d\n",
1939                                         reg);
1940                                 continue;
1941                         }
1942                         dev_dbg(component->dev, "DCS status: %x\n", reg);
1943                 } while (++timeout < 200 && (reg & expected) != expected);
1944
1945                 if ((reg & expected) != expected)
1946                         dev_err(component->dev, "DC servo timed out\n");
1947                 else
1948                         dev_dbg(component->dev, "DC servo complete after %dms\n",
1949                                 timeout);
1950
1951                 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1952                                     WM8962_HP1L_ENA_OUTP |
1953                                     WM8962_HP1R_ENA_OUTP,
1954                                     WM8962_HP1L_ENA_OUTP |
1955                                     WM8962_HP1R_ENA_OUTP);
1956                 udelay(20);
1957
1958                 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1959                                     WM8962_HP1L_RMV_SHORT |
1960                                     WM8962_HP1R_RMV_SHORT,
1961                                     WM8962_HP1L_RMV_SHORT |
1962                                     WM8962_HP1R_RMV_SHORT);
1963                 break;
1964
1965         case SND_SOC_DAPM_PRE_PMD:
1966                 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1967                                     WM8962_HP1L_RMV_SHORT |
1968                                     WM8962_HP1R_RMV_SHORT, 0);
1969
1970                 udelay(20);
1971
1972                 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1973                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1974                                     WM8962_HP1L_DCS_STARTUP |
1975                                     WM8962_HP1R_DCS_STARTUP,
1976                                     0);
1977
1978                 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1979                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1980                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1981                                     WM8962_HP1L_ENA_OUTP |
1982                                     WM8962_HP1R_ENA_OUTP, 0);
1983
1984                 break;
1985
1986         default:
1987                 WARN(1, "Invalid event %d\n", event);
1988                 return -EINVAL;
1989
1990         }
1991
1992         return 0;
1993 }
1994
1995 /* VU bits for the output PGAs only take effect while the PGA is powered */
1996 static int out_pga_event(struct snd_soc_dapm_widget *w,
1997                          struct snd_kcontrol *kcontrol, int event)
1998 {
1999         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2000         int reg;
2001
2002         switch (w->shift) {
2003         case WM8962_HPOUTR_PGA_ENA_SHIFT:
2004                 reg = WM8962_HPOUTR_VOLUME;
2005                 break;
2006         case WM8962_HPOUTL_PGA_ENA_SHIFT:
2007                 reg = WM8962_HPOUTL_VOLUME;
2008                 break;
2009         case WM8962_SPKOUTR_PGA_ENA_SHIFT:
2010                 reg = WM8962_SPKOUTR_VOLUME;
2011                 break;
2012         case WM8962_SPKOUTL_PGA_ENA_SHIFT:
2013                 reg = WM8962_SPKOUTL_VOLUME;
2014                 break;
2015         default:
2016                 WARN(1, "Invalid shift %d\n", w->shift);
2017                 return -EINVAL;
2018         }
2019
2020         switch (event) {
2021         case SND_SOC_DAPM_POST_PMU:
2022                 return snd_soc_component_write(component, reg,
2023                         snd_soc_component_read(component, reg));
2024         default:
2025                 WARN(1, "Invalid event %d\n", event);
2026                 return -EINVAL;
2027         }
2028 }
2029
2030 static int dsp2_event(struct snd_soc_dapm_widget *w,
2031                       struct snd_kcontrol *kcontrol, int event)
2032 {
2033         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2034         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2035
2036         switch (event) {
2037         case SND_SOC_DAPM_POST_PMU:
2038                 if (wm8962->dsp2_ena)
2039                         wm8962_dsp2_start(component);
2040                 break;
2041
2042         case SND_SOC_DAPM_PRE_PMD:
2043                 if (wm8962->dsp2_ena)
2044                         wm8962_dsp2_stop(component);
2045                 break;
2046
2047         default:
2048                 WARN(1, "Invalid event %d\n", event);
2049                 return -EINVAL;
2050         }
2051
2052         return 0;
2053 }
2054
2055 static const char *st_text[] = { "None", "Left", "Right" };
2056
2057 static SOC_ENUM_SINGLE_DECL(str_enum,
2058                             WM8962_DAC_DSP_MIXING_1, 2, st_text);
2059
2060 static const struct snd_kcontrol_new str_mux =
2061         SOC_DAPM_ENUM("Right Sidetone", str_enum);
2062
2063 static SOC_ENUM_SINGLE_DECL(stl_enum,
2064                             WM8962_DAC_DSP_MIXING_2, 2, st_text);
2065
2066 static const struct snd_kcontrol_new stl_mux =
2067         SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2068
2069 static const char *outmux_text[] = { "DAC", "Mixer" };
2070
2071 static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
2072                             WM8962_SPEAKER_MIXER_2, 7, outmux_text);
2073
2074 static const struct snd_kcontrol_new spkoutr_mux =
2075         SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2076
2077 static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
2078                             WM8962_SPEAKER_MIXER_1, 7, outmux_text);
2079
2080 static const struct snd_kcontrol_new spkoutl_mux =
2081         SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2082
2083 static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
2084                             WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
2085
2086 static const struct snd_kcontrol_new hpoutr_mux =
2087         SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2088
2089 static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
2090                             WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
2091
2092 static const struct snd_kcontrol_new hpoutl_mux =
2093         SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2094
2095 static const char * const input_mode_text[] = { "Analog", "Digital" };
2096
2097 static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text);
2098
2099 static const struct snd_kcontrol_new input_mode_mux =
2100         SOC_DAPM_ENUM("Input Mode", input_mode_enum);
2101
2102 static const struct snd_kcontrol_new inpgal[] = {
2103 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2104 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2105 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2106 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2107 };
2108
2109 static const struct snd_kcontrol_new inpgar[] = {
2110 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2111 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2112 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2113 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2114 };
2115
2116 static const struct snd_kcontrol_new mixinl[] = {
2117 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2118 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2119 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2120 };
2121
2122 static const struct snd_kcontrol_new mixinr[] = {
2123 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2124 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2125 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2126 };
2127
2128 static const struct snd_kcontrol_new hpmixl[] = {
2129 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2130 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2131 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2132 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2133 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2134 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2135 };
2136
2137 static const struct snd_kcontrol_new hpmixr[] = {
2138 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2139 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2140 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2141 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2142 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2143 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2144 };
2145
2146 static const struct snd_kcontrol_new spkmixl[] = {
2147 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2148 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2149 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2150 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2151 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2152 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2153 };
2154
2155 static const struct snd_kcontrol_new spkmixr[] = {
2156 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2157 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2158 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2159 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2160 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2161 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2162 };
2163
2164 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2165 SND_SOC_DAPM_INPUT("IN1L"),
2166 SND_SOC_DAPM_INPUT("IN1R"),
2167 SND_SOC_DAPM_INPUT("IN2L"),
2168 SND_SOC_DAPM_INPUT("IN2R"),
2169 SND_SOC_DAPM_INPUT("IN3L"),
2170 SND_SOC_DAPM_INPUT("IN3R"),
2171 SND_SOC_DAPM_INPUT("IN4L"),
2172 SND_SOC_DAPM_INPUT("IN4R"),
2173 SND_SOC_DAPM_SIGGEN("Beep"),
2174 SND_SOC_DAPM_INPUT("DMICDAT"),
2175
2176 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2177
2178 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2179 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2180 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2181                     SND_SOC_DAPM_POST_PMU),
2182 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2183 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2184                       WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2185                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2186 SND_SOC_DAPM_SUPPLY("TEMP_HP", SND_SOC_NOPM, 0, 0, tp_event,
2187                 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2188 SND_SOC_DAPM_SUPPLY("TEMP_SPK", SND_SOC_NOPM, 0, 0, tp_event,
2189                 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2190
2191 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2192                    inpgal, ARRAY_SIZE(inpgal)),
2193 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2194                    inpgar, ARRAY_SIZE(inpgar)),
2195 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2196                    mixinl, ARRAY_SIZE(mixinl)),
2197 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2198                    mixinr, ARRAY_SIZE(mixinr)),
2199
2200 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2201
2202 SND_SOC_DAPM_MUX("Input Mode L", SND_SOC_NOPM, 0, 0, &input_mode_mux),
2203 SND_SOC_DAPM_MUX("Input Mode R", SND_SOC_NOPM, 0, 0, &input_mode_mux),
2204
2205 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2206 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2207
2208 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2209 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2210
2211 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2212 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2213
2214 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2215 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2216
2217 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2218                    hpmixl, ARRAY_SIZE(hpmixl)),
2219 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2220                    hpmixr, ARRAY_SIZE(hpmixr)),
2221
2222 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2223                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2224 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2225                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2226
2227 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2228                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2229
2230 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2231 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2232 };
2233
2234 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2235 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2236                    spkmixl, ARRAY_SIZE(spkmixl)),
2237 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2238                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2239 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2240 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2241 };
2242
2243 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2244 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2245                    spkmixl, ARRAY_SIZE(spkmixl)),
2246 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2247                    spkmixr, ARRAY_SIZE(spkmixr)),
2248
2249 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2250                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2251 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2252                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2253
2254 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2255 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2256
2257 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2258 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2259 };
2260
2261 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2262         { "INPGAL", "IN1L Switch", "IN1L" },
2263         { "INPGAL", "IN2L Switch", "IN2L" },
2264         { "INPGAL", "IN3L Switch", "IN3L" },
2265         { "INPGAL", "IN4L Switch", "IN4L" },
2266
2267         { "INPGAR", "IN1R Switch", "IN1R" },
2268         { "INPGAR", "IN2R Switch", "IN2R" },
2269         { "INPGAR", "IN3R Switch", "IN3R" },
2270         { "INPGAR", "IN4R Switch", "IN4R" },
2271
2272         { "MIXINL", "IN2L Switch", "IN2L" },
2273         { "MIXINL", "IN3L Switch", "IN3L" },
2274         { "MIXINL", "PGA Switch", "INPGAL" },
2275
2276         { "MIXINR", "IN2R Switch", "IN2R" },
2277         { "MIXINR", "IN3R Switch", "IN3R" },
2278         { "MIXINR", "PGA Switch", "INPGAR" },
2279
2280         { "MICBIAS", NULL, "SYSCLK" },
2281
2282         { "DMIC_ENA", NULL, "DMICDAT" },
2283
2284         { "Input Mode L", "Analog", "MIXINL" },
2285         { "Input Mode L", "Digital", "DMIC_ENA" },
2286         { "Input Mode R", "Analog", "MIXINR" },
2287         { "Input Mode R", "Digital", "DMIC_ENA" },
2288
2289         { "ADCL", NULL, "SYSCLK" },
2290         { "ADCL", NULL, "TOCLK" },
2291         { "ADCL", NULL, "Input Mode L" },
2292         { "ADCL", NULL, "DSP2" },
2293
2294         { "ADCR", NULL, "SYSCLK" },
2295         { "ADCR", NULL, "TOCLK" },
2296         { "ADCR", NULL, "Input Mode R" },
2297         { "ADCR", NULL, "DSP2" },
2298
2299         { "STL", "Left", "ADCL" },
2300         { "STL", "Right", "ADCR" },
2301         { "STL", NULL, "Class G" },
2302
2303         { "STR", "Left", "ADCL" },
2304         { "STR", "Right", "ADCR" },
2305         { "STR", NULL, "Class G" },
2306
2307         { "DACL", NULL, "SYSCLK" },
2308         { "DACL", NULL, "TOCLK" },
2309         { "DACL", NULL, "Beep" },
2310         { "DACL", NULL, "STL" },
2311         { "DACL", NULL, "DSP2" },
2312
2313         { "DACR", NULL, "SYSCLK" },
2314         { "DACR", NULL, "TOCLK" },
2315         { "DACR", NULL, "Beep" },
2316         { "DACR", NULL, "STR" },
2317         { "DACR", NULL, "DSP2" },
2318
2319         { "HPMIXL", "IN4L Switch", "IN4L" },
2320         { "HPMIXL", "IN4R Switch", "IN4R" },
2321         { "HPMIXL", "DACL Switch", "DACL" },
2322         { "HPMIXL", "DACR Switch", "DACR" },
2323         { "HPMIXL", "MIXINL Switch", "MIXINL" },
2324         { "HPMIXL", "MIXINR Switch", "MIXINR" },
2325
2326         { "HPMIXR", "IN4L Switch", "IN4L" },
2327         { "HPMIXR", "IN4R Switch", "IN4R" },
2328         { "HPMIXR", "DACL Switch", "DACL" },
2329         { "HPMIXR", "DACR Switch", "DACR" },
2330         { "HPMIXR", "MIXINL Switch", "MIXINL" },
2331         { "HPMIXR", "MIXINR Switch", "MIXINR" },
2332
2333         { "Left Bypass", NULL, "HPMIXL" },
2334         { "Left Bypass", NULL, "Class G" },
2335
2336         { "Right Bypass", NULL, "HPMIXR" },
2337         { "Right Bypass", NULL, "Class G" },
2338
2339         { "HPOUTL PGA", "Mixer", "Left Bypass" },
2340         { "HPOUTL PGA", "DAC", "DACL" },
2341
2342         { "HPOUTR PGA", "Mixer", "Right Bypass" },
2343         { "HPOUTR PGA", "DAC", "DACR" },
2344
2345         { "HPOUT", NULL, "HPOUTL PGA" },
2346         { "HPOUT", NULL, "HPOUTR PGA" },
2347         { "HPOUT", NULL, "Charge Pump" },
2348         { "HPOUT", NULL, "SYSCLK" },
2349         { "HPOUT", NULL, "TOCLK" },
2350
2351         { "HPOUTL", NULL, "HPOUT" },
2352         { "HPOUTR", NULL, "HPOUT" },
2353
2354         { "HPOUTL", NULL, "TEMP_HP" },
2355         { "HPOUTR", NULL, "TEMP_HP" },
2356 };
2357
2358 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2359         { "Speaker Mixer", "IN4L Switch", "IN4L" },
2360         { "Speaker Mixer", "IN4R Switch", "IN4R" },
2361         { "Speaker Mixer", "DACL Switch", "DACL" },
2362         { "Speaker Mixer", "DACR Switch", "DACR" },
2363         { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2364         { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2365
2366         { "Speaker PGA", "Mixer", "Speaker Mixer" },
2367         { "Speaker PGA", "DAC", "DACL" },
2368
2369         { "Speaker Output", NULL, "Speaker PGA" },
2370         { "Speaker Output", NULL, "SYSCLK" },
2371         { "Speaker Output", NULL, "TOCLK" },
2372         { "Speaker Output", NULL, "TEMP_SPK" },
2373
2374         { "SPKOUT", NULL, "Speaker Output" },
2375 };
2376
2377 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2378         { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2379         { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2380         { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2381         { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2382         { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2383         { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2384
2385         { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2386         { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2387         { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2388         { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2389         { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2390         { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2391
2392         { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2393         { "SPKOUTL PGA", "DAC", "DACL" },
2394
2395         { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2396         { "SPKOUTR PGA", "DAC", "DACR" },
2397
2398         { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2399         { "SPKOUTL Output", NULL, "SYSCLK" },
2400         { "SPKOUTL Output", NULL, "TOCLK" },
2401         { "SPKOUTL Output", NULL, "TEMP_SPK" },
2402
2403         { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2404         { "SPKOUTR Output", NULL, "SYSCLK" },
2405         { "SPKOUTR Output", NULL, "TOCLK" },
2406         { "SPKOUTR Output", NULL, "TEMP_SPK" },
2407
2408         { "SPKOUTL", NULL, "SPKOUTL Output" },
2409         { "SPKOUTR", NULL, "SPKOUTR Output" },
2410 };
2411
2412 static int wm8962_add_widgets(struct snd_soc_component *component)
2413 {
2414         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2415         struct wm8962_pdata *pdata = &wm8962->pdata;
2416         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2417
2418         snd_soc_add_component_controls(component, wm8962_snd_controls,
2419                              ARRAY_SIZE(wm8962_snd_controls));
2420         if (pdata->spk_mono)
2421                 snd_soc_add_component_controls(component, wm8962_spk_mono_controls,
2422                                      ARRAY_SIZE(wm8962_spk_mono_controls));
2423         else
2424                 snd_soc_add_component_controls(component, wm8962_spk_stereo_controls,
2425                                      ARRAY_SIZE(wm8962_spk_stereo_controls));
2426
2427
2428         snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2429                                   ARRAY_SIZE(wm8962_dapm_widgets));
2430         if (pdata->spk_mono)
2431                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2432                                           ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2433         else
2434                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2435                                           ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2436
2437         snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2438                                 ARRAY_SIZE(wm8962_intercon));
2439         if (pdata->spk_mono)
2440                 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2441                                         ARRAY_SIZE(wm8962_spk_mono_intercon));
2442         else
2443                 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2444                                         ARRAY_SIZE(wm8962_spk_stereo_intercon));
2445
2446
2447         snd_soc_dapm_disable_pin(dapm, "Beep");
2448
2449         return 0;
2450 }
2451
2452 /* -1 for reserved values */
2453 static const int bclk_divs[] = {
2454         1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2455 };
2456
2457 static const int sysclk_rates[] = {
2458         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2459 };
2460
2461 static void wm8962_configure_bclk(struct snd_soc_component *component)
2462 {
2463         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2464         int best, min_diff, diff;
2465         int dspclk, i;
2466         int clocking2 = 0;
2467         int clocking4 = 0;
2468         int aif2 = 0;
2469
2470         if (!wm8962->sysclk_rate) {
2471                 dev_dbg(component->dev, "No SYSCLK configured\n");
2472                 return;
2473         }
2474
2475         if (!wm8962->bclk || !wm8962->lrclk) {
2476                 dev_dbg(component->dev, "No audio clocks configured\n");
2477                 return;
2478         }
2479
2480         for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2481                 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2482                         clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2483                         break;
2484                 }
2485         }
2486
2487         if (i == ARRAY_SIZE(sysclk_rates)) {
2488                 dev_err(component->dev, "Unsupported sysclk ratio %d\n",
2489                         wm8962->sysclk_rate / wm8962->lrclk);
2490                 return;
2491         }
2492
2493         dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2494
2495         snd_soc_component_update_bits(component, WM8962_CLOCKING_4,
2496                             WM8962_SYSCLK_RATE_MASK, clocking4);
2497
2498         /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
2499          * So we here provisionally enable it and then disable it afterward
2500          * if current bias_level hasn't reached SND_SOC_BIAS_ON.
2501          */
2502         if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2503                 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2504                                 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2505
2506         dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
2507
2508         if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2509                 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2510                                 WM8962_SYSCLK_ENA_MASK, 0);
2511
2512         if (dspclk < 0) {
2513                 dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk);
2514                 return;
2515         }
2516
2517         dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2518         switch (dspclk) {
2519         case 0:
2520                 dspclk = wm8962->sysclk_rate;
2521                 break;
2522         case 1:
2523                 dspclk = wm8962->sysclk_rate / 2;
2524                 break;
2525         case 2:
2526                 dspclk = wm8962->sysclk_rate / 4;
2527                 break;
2528         default:
2529                 dev_warn(component->dev, "Unknown DSPCLK divisor read back\n");
2530                 dspclk = wm8962->sysclk_rate;
2531         }
2532
2533         dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2534
2535         /* Search a proper bclk, not exact match. */
2536         best = 0;
2537         min_diff = INT_MAX;
2538         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2539                 if (bclk_divs[i] < 0)
2540                         continue;
2541
2542                 diff = (dspclk / bclk_divs[i]) - wm8962->bclk;
2543                 if (diff < 0) /* Table is sorted */
2544                         break;
2545                 if (diff < min_diff) {
2546                         best = i;
2547                         min_diff = diff;
2548                 }
2549         }
2550         wm8962->bclk = dspclk / bclk_divs[best];
2551         clocking2 |= best;
2552         dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",
2553                 bclk_divs[best], wm8962->bclk);
2554
2555         aif2 |= wm8962->bclk / wm8962->lrclk;
2556         dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",
2557                 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2558
2559         snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2560                             WM8962_BCLK_DIV_MASK, clocking2);
2561         snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2,
2562                             WM8962_AIF_RATE_MASK, aif2);
2563 }
2564
2565 static int wm8962_set_bias_level(struct snd_soc_component *component,
2566                                  enum snd_soc_bias_level level)
2567 {
2568         switch (level) {
2569         case SND_SOC_BIAS_ON:
2570                 break;
2571
2572         case SND_SOC_BIAS_PREPARE:
2573                 /* VMID 2*50k */
2574                 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2575                                     WM8962_VMID_SEL_MASK, 0x80);
2576
2577                 wm8962_configure_bclk(component);
2578                 break;
2579
2580         case SND_SOC_BIAS_STANDBY:
2581                 /* VMID 2*250k */
2582                 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2583                                     WM8962_VMID_SEL_MASK, 0x100);
2584
2585                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
2586                         msleep(100);
2587                 break;
2588
2589         case SND_SOC_BIAS_OFF:
2590                 break;
2591         }
2592
2593         return 0;
2594 }
2595
2596 static const struct {
2597         int rate;
2598         int reg;
2599 } sr_vals[] = {
2600         { 48000, 0 },
2601         { 44100, 0 },
2602         { 32000, 1 },
2603         { 22050, 2 },
2604         { 24000, 2 },
2605         { 16000, 3 },
2606         { 11025, 4 },
2607         { 12000, 4 },
2608         { 8000,  5 },
2609         { 88200, 6 },
2610         { 96000, 6 },
2611 };
2612
2613 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2614                             struct snd_pcm_hw_params *params,
2615                             struct snd_soc_dai *dai)
2616 {
2617         struct snd_soc_component *component = dai->component;
2618         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2619         int i;
2620         int aif0 = 0;
2621         int adctl3 = 0;
2622
2623         wm8962->bclk = snd_soc_params_to_bclk(params);
2624         if (params_channels(params) == 1)
2625                 wm8962->bclk *= 2;
2626
2627         wm8962->lrclk = params_rate(params);
2628
2629         for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2630                 if (sr_vals[i].rate == wm8962->lrclk) {
2631                         adctl3 |= sr_vals[i].reg;
2632                         break;
2633                 }
2634         }
2635         if (i == ARRAY_SIZE(sr_vals)) {
2636                 dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2637                 return -EINVAL;
2638         }
2639
2640         if (wm8962->lrclk % 8000 == 0)
2641                 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2642
2643         switch (params_width(params)) {
2644         case 16:
2645                 break;
2646         case 20:
2647                 aif0 |= 0x4;
2648                 break;
2649         case 24:
2650                 aif0 |= 0x8;
2651                 break;
2652         case 32:
2653                 aif0 |= 0xc;
2654                 break;
2655         default:
2656                 return -EINVAL;
2657         }
2658
2659         snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2660                             WM8962_WL_MASK, aif0);
2661         snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3,
2662                             WM8962_SAMPLE_RATE_INT_MODE |
2663                             WM8962_SAMPLE_RATE_MASK, adctl3);
2664
2665         dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2666                 wm8962->bclk, wm8962->lrclk);
2667
2668         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON)
2669                 wm8962_configure_bclk(component);
2670
2671         return 0;
2672 }
2673
2674 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2675                                  unsigned int freq, int dir)
2676 {
2677         struct snd_soc_component *component = dai->component;
2678         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2679         int src;
2680
2681         switch (clk_id) {
2682         case WM8962_SYSCLK_MCLK:
2683                 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2684                 src = 0;
2685                 break;
2686         case WM8962_SYSCLK_FLL:
2687                 wm8962->sysclk = WM8962_SYSCLK_FLL;
2688                 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2689                 break;
2690         default:
2691                 return -EINVAL;
2692         }
2693
2694         snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2695                             src);
2696
2697         wm8962->sysclk_rate = freq;
2698
2699         return 0;
2700 }
2701
2702 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2703 {
2704         struct snd_soc_component *component = dai->component;
2705         int aif0 = 0;
2706
2707         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2708         case SND_SOC_DAIFMT_DSP_B:
2709                 aif0 |= WM8962_LRCLK_INV | 3;
2710                 fallthrough;
2711         case SND_SOC_DAIFMT_DSP_A:
2712                 aif0 |= 3;
2713
2714                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2715                 case SND_SOC_DAIFMT_NB_NF:
2716                 case SND_SOC_DAIFMT_IB_NF:
2717                         break;
2718                 default:
2719                         return -EINVAL;
2720                 }
2721                 break;
2722
2723         case SND_SOC_DAIFMT_RIGHT_J:
2724                 break;
2725         case SND_SOC_DAIFMT_LEFT_J:
2726                 aif0 |= 1;
2727                 break;
2728         case SND_SOC_DAIFMT_I2S:
2729                 aif0 |= 2;
2730                 break;
2731         default:
2732                 return -EINVAL;
2733         }
2734
2735         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2736         case SND_SOC_DAIFMT_NB_NF:
2737                 break;
2738         case SND_SOC_DAIFMT_IB_NF:
2739                 aif0 |= WM8962_BCLK_INV;
2740                 break;
2741         case SND_SOC_DAIFMT_NB_IF:
2742                 aif0 |= WM8962_LRCLK_INV;
2743                 break;
2744         case SND_SOC_DAIFMT_IB_IF:
2745                 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2746                 break;
2747         default:
2748                 return -EINVAL;
2749         }
2750
2751         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2752         case SND_SOC_DAIFMT_CBM_CFM:
2753                 aif0 |= WM8962_MSTR;
2754                 break;
2755         case SND_SOC_DAIFMT_CBS_CFS:
2756                 break;
2757         default:
2758                 return -EINVAL;
2759         }
2760
2761         snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2762                             WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2763                             WM8962_LRCLK_INV, aif0);
2764
2765         return 0;
2766 }
2767
2768 struct _fll_div {
2769         u16 fll_fratio;
2770         u16 fll_outdiv;
2771         u16 fll_refclk_div;
2772         u16 n;
2773         u16 theta;
2774         u16 lambda;
2775 };
2776
2777 /* The size in bits of the FLL divide multiplied by 10
2778  * to allow rounding later */
2779 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2780
2781 static struct {
2782         unsigned int min;
2783         unsigned int max;
2784         u16 fll_fratio;
2785         int ratio;
2786 } fll_fratios[] = {
2787         {       0,    64000, 4, 16 },
2788         {   64000,   128000, 3,  8 },
2789         {  128000,   256000, 2,  4 },
2790         {  256000,  1000000, 1,  2 },
2791         { 1000000, 13500000, 0,  1 },
2792 };
2793
2794 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2795                        unsigned int Fout)
2796 {
2797         unsigned int target;
2798         unsigned int div;
2799         unsigned int fratio, gcd_fll;
2800         int i;
2801
2802         /* Fref must be <=13.5MHz */
2803         div = 1;
2804         fll_div->fll_refclk_div = 0;
2805         while ((Fref / div) > 13500000) {
2806                 div *= 2;
2807                 fll_div->fll_refclk_div++;
2808
2809                 if (div > 4) {
2810                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2811                                Fref);
2812                         return -EINVAL;
2813                 }
2814         }
2815
2816         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2817
2818         /* Apply the division for our remaining calculations */
2819         Fref /= div;
2820
2821         /* Fvco should be 90-100MHz; don't check the upper bound */
2822         div = 2;
2823         while (Fout * div < 90000000) {
2824                 div++;
2825                 if (div > 64) {
2826                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2827                                Fout);
2828                         return -EINVAL;
2829                 }
2830         }
2831         target = Fout * div;
2832         fll_div->fll_outdiv = div - 1;
2833
2834         pr_debug("FLL Fvco=%dHz\n", target);
2835
2836         /* Find an appropriate FLL_FRATIO and factor it out of the target */
2837         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2838                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2839                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2840                         fratio = fll_fratios[i].ratio;
2841                         break;
2842                 }
2843         }
2844         if (i == ARRAY_SIZE(fll_fratios)) {
2845                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2846                 return -EINVAL;
2847         }
2848
2849         fll_div->n = target / (fratio * Fref);
2850
2851         if (target % Fref == 0) {
2852                 fll_div->theta = 0;
2853                 fll_div->lambda = 1;
2854         } else {
2855                 gcd_fll = gcd(target, fratio * Fref);
2856
2857                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2858                         / gcd_fll;
2859                 fll_div->lambda = (fratio * Fref) / gcd_fll;
2860         }
2861
2862         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2863                  fll_div->n, fll_div->theta, fll_div->lambda);
2864         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2865                  fll_div->fll_fratio, fll_div->fll_outdiv,
2866                  fll_div->fll_refclk_div);
2867
2868         return 0;
2869 }
2870
2871 static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source,
2872                           unsigned int Fref, unsigned int Fout)
2873 {
2874         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2875         struct _fll_div fll_div;
2876         unsigned long timeout;
2877         int ret;
2878         int fll1 = 0;
2879
2880         /* Any change? */
2881         if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2882             Fout == wm8962->fll_fout)
2883                 return 0;
2884
2885         if (Fout == 0) {
2886                 dev_dbg(component->dev, "FLL disabled\n");
2887
2888                 wm8962->fll_fref = 0;
2889                 wm8962->fll_fout = 0;
2890
2891                 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2892                                     WM8962_FLL_ENA, 0);
2893
2894                 pm_runtime_put(component->dev);
2895
2896                 return 0;
2897         }
2898
2899         ret = fll_factors(&fll_div, Fref, Fout);
2900         if (ret != 0)
2901                 return ret;
2902
2903         /* Parameters good, disable so we can reprogram */
2904         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2905
2906         switch (fll_id) {
2907         case WM8962_FLL_MCLK:
2908         case WM8962_FLL_BCLK:
2909         case WM8962_FLL_OSC:
2910                 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2911                 break;
2912         case WM8962_FLL_INT:
2913                 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2914                                     WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2915                 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5,
2916                                     WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2917                 break;
2918         default:
2919                 dev_err(component->dev, "Unknown FLL source %d\n", ret);
2920                 return -EINVAL;
2921         }
2922
2923         if (fll_div.theta)
2924                 fll1 |= WM8962_FLL_FRAC;
2925
2926         /* Stop the FLL while we reconfigure */
2927         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2928
2929         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2,
2930                             WM8962_FLL_OUTDIV_MASK |
2931                             WM8962_FLL_REFCLK_DIV_MASK,
2932                             (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2933                             (fll_div.fll_refclk_div));
2934
2935         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3,
2936                             WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2937
2938         snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta);
2939         snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda);
2940         snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n);
2941
2942         reinit_completion(&wm8962->fll_lock);
2943
2944         ret = pm_runtime_resume_and_get(component->dev);
2945         if (ret < 0) {
2946                 dev_err(component->dev, "Failed to resume device: %d\n", ret);
2947                 return ret;
2948         }
2949
2950         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2951                             WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2952                             WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2953
2954         dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2955
2956         /* This should be a massive overestimate but go even
2957          * higher if we'll error out
2958          */
2959         if (wm8962->irq)
2960                 timeout = msecs_to_jiffies(5);
2961         else
2962                 timeout = msecs_to_jiffies(1);
2963
2964         timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2965                                               timeout);
2966
2967         if (timeout == 0 && wm8962->irq) {
2968                 dev_err(component->dev, "FLL lock timed out");
2969                 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2970                                     WM8962_FLL_ENA, 0);
2971                 pm_runtime_put(component->dev);
2972                 return -ETIMEDOUT;
2973         }
2974
2975         wm8962->fll_fref = Fref;
2976         wm8962->fll_fout = Fout;
2977         wm8962->fll_src = source;
2978
2979         return 0;
2980 }
2981
2982 static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction)
2983 {
2984         struct snd_soc_component *component = dai->component;
2985         int val, ret;
2986
2987         if (mute)
2988                 val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
2989         else
2990                 val = 0;
2991
2992         /**
2993          * The DAC mute bit is mirrored in two registers, update both to keep
2994          * the register cache consistent.
2995          */
2996         ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1,
2997                                   WM8962_DAC_MUTE_ALT, val);
2998         if (ret < 0)
2999                 return ret;
3000
3001         return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
3002                                    WM8962_DAC_MUTE, val);
3003 }
3004
3005 #define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
3006                 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
3007
3008 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3009                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3010
3011 static const struct snd_soc_dai_ops wm8962_dai_ops = {
3012         .hw_params = wm8962_hw_params,
3013         .set_sysclk = wm8962_set_dai_sysclk,
3014         .set_fmt = wm8962_set_dai_fmt,
3015         .mute_stream = wm8962_mute,
3016         .no_capture_mute = 1,
3017 };
3018
3019 static struct snd_soc_dai_driver wm8962_dai = {
3020         .name = "wm8962",
3021         .playback = {
3022                 .stream_name = "Playback",
3023                 .channels_min = 1,
3024                 .channels_max = 2,
3025                 .rates = WM8962_RATES,
3026                 .formats = WM8962_FORMATS,
3027         },
3028         .capture = {
3029                 .stream_name = "Capture",
3030                 .channels_min = 1,
3031                 .channels_max = 2,
3032                 .rates = WM8962_RATES,
3033                 .formats = WM8962_FORMATS,
3034         },
3035         .ops = &wm8962_dai_ops,
3036         .symmetric_rate = 1,
3037 };
3038
3039 static void wm8962_mic_work(struct work_struct *work)
3040 {
3041         struct wm8962_priv *wm8962 = container_of(work,
3042                                                   struct wm8962_priv,
3043                                                   mic_work.work);
3044         struct snd_soc_component *component = wm8962->component;
3045         int status = 0;
3046         int irq_pol = 0;
3047         int reg;
3048
3049         reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4);
3050
3051         if (reg & WM8962_MICDET_STS) {
3052                 status |= SND_JACK_MICROPHONE;
3053                 irq_pol |= WM8962_MICD_IRQ_POL;
3054         }
3055
3056         if (reg & WM8962_MICSHORT_STS) {
3057                 status |= SND_JACK_BTN_0;
3058                 irq_pol |= WM8962_MICSCD_IRQ_POL;
3059         }
3060
3061         snd_soc_jack_report(wm8962->jack, status,
3062                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3063
3064         snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL,
3065                             WM8962_MICSCD_IRQ_POL |
3066                             WM8962_MICD_IRQ_POL, irq_pol);
3067 }
3068
3069 static irqreturn_t wm8962_irq(int irq, void *data)
3070 {
3071         struct device *dev = data;
3072         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3073         unsigned int mask;
3074         unsigned int active;
3075         int reg, ret;
3076
3077         ret = pm_runtime_resume_and_get(dev);
3078         if (ret < 0) {
3079                 dev_err(dev, "Failed to resume: %d\n", ret);
3080                 return IRQ_NONE;
3081         }
3082
3083         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3084                           &mask);
3085         if (ret != 0) {
3086                 pm_runtime_put(dev);
3087                 dev_err(dev, "Failed to read interrupt mask: %d\n",
3088                         ret);
3089                 return IRQ_NONE;
3090         }
3091
3092         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3093         if (ret != 0) {
3094                 pm_runtime_put(dev);
3095                 dev_err(dev, "Failed to read interrupt: %d\n", ret);
3096                 return IRQ_NONE;
3097         }
3098
3099         active &= ~mask;
3100
3101         if (!active) {
3102                 pm_runtime_put(dev);
3103                 return IRQ_NONE;
3104         }
3105
3106         /* Acknowledge the interrupts */
3107         ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3108         if (ret != 0)
3109                 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3110
3111         if (active & WM8962_FLL_LOCK_EINT) {
3112                 dev_dbg(dev, "FLL locked\n");
3113                 complete(&wm8962->fll_lock);
3114         }
3115
3116         if (active & WM8962_FIFOS_ERR_EINT)
3117                 dev_err(dev, "FIFO error\n");
3118
3119         if (active & WM8962_TEMP_SHUT_EINT) {
3120                 dev_crit(dev, "Thermal shutdown\n");
3121
3122                 ret = regmap_read(wm8962->regmap,
3123                                   WM8962_THERMAL_SHUTDOWN_STATUS,  &reg);
3124                 if (ret != 0) {
3125                         dev_warn(dev, "Failed to read thermal status: %d\n",
3126                                  ret);
3127                         reg = 0;
3128                 }
3129
3130                 if (reg & WM8962_TEMP_ERR_HP)
3131                         dev_crit(dev, "Headphone thermal error\n");
3132                 if (reg & WM8962_TEMP_WARN_HP)
3133                         dev_crit(dev, "Headphone thermal warning\n");
3134                 if (reg & WM8962_TEMP_ERR_SPK)
3135                         dev_crit(dev, "Speaker thermal error\n");
3136                 if (reg & WM8962_TEMP_WARN_SPK)
3137                         dev_crit(dev, "Speaker thermal warning\n");
3138         }
3139
3140         if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3141                 dev_dbg(dev, "Microphone event detected\n");
3142
3143 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3144                 trace_snd_soc_jack_irq(dev_name(dev));
3145 #endif
3146
3147                 pm_wakeup_event(dev, 300);
3148
3149                 queue_delayed_work(system_power_efficient_wq,
3150                                    &wm8962->mic_work,
3151                                    msecs_to_jiffies(250));
3152         }
3153
3154         pm_runtime_put(dev);
3155
3156         return IRQ_HANDLED;
3157 }
3158
3159 /**
3160  * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3161  *
3162  * @component:  WM8962 component
3163  * @jack:   jack to report detection events on
3164  *
3165  * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
3166  * being used to bring out signals to the processor then only platform
3167  * data configuration is needed for WM8962 and processor GPIOs should
3168  * be configured using snd_soc_jack_add_gpios() instead.
3169  *
3170  * If no jack is supplied detection will be disabled.
3171  */
3172 int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
3173 {
3174         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3175         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3176         int irq_mask, enable;
3177
3178         wm8962->jack = jack;
3179         if (jack) {
3180                 irq_mask = 0;
3181                 enable = WM8962_MICDET_ENA;
3182         } else {
3183                 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3184                 enable = 0;
3185         }
3186
3187         snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK,
3188                             WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3189         snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4,
3190                             WM8962_MICDET_ENA, enable);
3191
3192         /* Send an initial empty report */
3193         snd_soc_jack_report(wm8962->jack, 0,
3194                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3195
3196         snd_soc_dapm_mutex_lock(dapm);
3197
3198         if (jack) {
3199                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
3200                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
3201         } else {
3202                 snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
3203                 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
3204         }
3205
3206         snd_soc_dapm_mutex_unlock(dapm);
3207
3208         return 0;
3209 }
3210 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3211
3212 static int beep_rates[] = {
3213         500, 1000, 2000, 4000,
3214 };
3215
3216 static void wm8962_beep_work(struct work_struct *work)
3217 {
3218         struct wm8962_priv *wm8962 =
3219                 container_of(work, struct wm8962_priv, beep_work);
3220         struct snd_soc_component *component = wm8962->component;
3221         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3222         int i;
3223         int reg = 0;
3224         int best = 0;
3225
3226         if (wm8962->beep_rate) {
3227                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3228                         if (abs(wm8962->beep_rate - beep_rates[i]) <
3229                             abs(wm8962->beep_rate - beep_rates[best]))
3230                                 best = i;
3231                 }
3232
3233                 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
3234                         beep_rates[best], wm8962->beep_rate);
3235
3236                 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3237
3238                 snd_soc_dapm_enable_pin(dapm, "Beep");
3239         } else {
3240                 dev_dbg(component->dev, "Disabling beep\n");
3241                 snd_soc_dapm_disable_pin(dapm, "Beep");
3242         }
3243
3244         snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1,
3245                             WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3246
3247         snd_soc_dapm_sync(dapm);
3248 }
3249
3250 /* For usability define a way of injecting beep events for the device -
3251  * many systems will not have a keyboard.
3252  */
3253 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3254                              unsigned int code, int hz)
3255 {
3256         struct snd_soc_component *component = input_get_drvdata(dev);
3257         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3258
3259         dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
3260
3261         switch (code) {
3262         case SND_BELL:
3263                 if (hz)
3264                         hz = 1000;
3265                 fallthrough;
3266         case SND_TONE:
3267                 break;
3268         default:
3269                 return -1;
3270         }
3271
3272         /* Kick the beep from a workqueue */
3273         wm8962->beep_rate = hz;
3274         schedule_work(&wm8962->beep_work);
3275         return 0;
3276 }
3277
3278 static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
3279                           const char *buf, size_t count)
3280 {
3281         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3282         long int time;
3283         int ret;
3284
3285         ret = kstrtol(buf, 10, &time);
3286         if (ret != 0)
3287                 return ret;
3288
3289         input_event(wm8962->beep, EV_SND, SND_TONE, time);
3290
3291         return count;
3292 }
3293
3294 static DEVICE_ATTR_WO(beep);
3295
3296 static void wm8962_init_beep(struct snd_soc_component *component)
3297 {
3298         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3299         int ret;
3300
3301         wm8962->beep = devm_input_allocate_device(component->dev);
3302         if (!wm8962->beep) {
3303                 dev_err(component->dev, "Failed to allocate beep device\n");
3304                 return;
3305         }
3306
3307         INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3308         wm8962->beep_rate = 0;
3309
3310         wm8962->beep->name = "WM8962 Beep Generator";
3311         wm8962->beep->phys = dev_name(component->dev);
3312         wm8962->beep->id.bustype = BUS_I2C;
3313
3314         wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3315         wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3316         wm8962->beep->event = wm8962_beep_event;
3317         wm8962->beep->dev.parent = component->dev;
3318         input_set_drvdata(wm8962->beep, component);
3319
3320         ret = input_register_device(wm8962->beep);
3321         if (ret != 0) {
3322                 wm8962->beep = NULL;
3323                 dev_err(component->dev, "Failed to register beep device\n");
3324         }
3325
3326         ret = device_create_file(component->dev, &dev_attr_beep);
3327         if (ret != 0) {
3328                 dev_err(component->dev, "Failed to create keyclick file: %d\n",
3329                         ret);
3330         }
3331 }
3332
3333 static void wm8962_free_beep(struct snd_soc_component *component)
3334 {
3335         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3336
3337         device_remove_file(component->dev, &dev_attr_beep);
3338         cancel_work_sync(&wm8962->beep_work);
3339         wm8962->beep = NULL;
3340
3341         snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3342 }
3343
3344 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3345 {
3346         int mask = 0;
3347         int val = 0;
3348
3349         /* Some of the GPIOs are behind MFP configuration and need to
3350          * be put into GPIO mode. */
3351         switch (gpio) {
3352         case 2:
3353                 mask = WM8962_CLKOUT2_SEL_MASK;
3354                 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3355                 break;
3356         case 3:
3357                 mask = WM8962_CLKOUT3_SEL_MASK;
3358                 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3359                 break;
3360         default:
3361                 break;
3362         }
3363
3364         if (mask)
3365                 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3366                                    mask, val);
3367 }
3368
3369 #ifdef CONFIG_GPIOLIB
3370 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3371 {
3372         struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3373
3374         /* The WM8962 GPIOs aren't linearly numbered.  For simplicity
3375          * we export linear numbers and error out if the unsupported
3376          * ones are requsted.
3377          */
3378         switch (offset + 1) {
3379         case 2:
3380         case 3:
3381         case 5:
3382         case 6:
3383                 break;
3384         default:
3385                 return -EINVAL;
3386         }
3387
3388         wm8962_set_gpio_mode(wm8962, offset + 1);
3389
3390         return 0;
3391 }
3392
3393 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3394 {
3395         struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3396         struct snd_soc_component *component = wm8962->component;
3397
3398         snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3399                             WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3400 }
3401
3402 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3403                                      unsigned offset, int value)
3404 {
3405         struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3406         struct snd_soc_component *component = wm8962->component;
3407         int ret, val;
3408
3409         /* Force function 1 (logic output) */
3410         val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3411
3412         ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3413                                   WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3414         if (ret < 0)
3415                 return ret;
3416
3417         return 0;
3418 }
3419
3420 static const struct gpio_chip wm8962_template_chip = {
3421         .label                  = "wm8962",
3422         .owner                  = THIS_MODULE,
3423         .request                = wm8962_gpio_request,
3424         .direction_output       = wm8962_gpio_direction_out,
3425         .set                    = wm8962_gpio_set,
3426         .can_sleep              = 1,
3427 };
3428
3429 static void wm8962_init_gpio(struct snd_soc_component *component)
3430 {
3431         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3432         struct wm8962_pdata *pdata = &wm8962->pdata;
3433         int ret;
3434
3435         wm8962->gpio_chip = wm8962_template_chip;
3436         wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3437         wm8962->gpio_chip.parent = component->dev;
3438
3439         if (pdata->gpio_base)
3440                 wm8962->gpio_chip.base = pdata->gpio_base;
3441         else
3442                 wm8962->gpio_chip.base = -1;
3443
3444         ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962);
3445         if (ret != 0)
3446                 dev_err(component->dev, "Failed to add GPIOs: %d\n", ret);
3447 }
3448
3449 static void wm8962_free_gpio(struct snd_soc_component *component)
3450 {
3451         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3452
3453         gpiochip_remove(&wm8962->gpio_chip);
3454 }
3455 #else
3456 static void wm8962_init_gpio(struct snd_soc_component *component)
3457 {
3458 }
3459
3460 static void wm8962_free_gpio(struct snd_soc_component *component)
3461 {
3462 }
3463 #endif
3464
3465 static int wm8962_probe(struct snd_soc_component *component)
3466 {
3467         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3468         int ret;
3469         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3470         int i;
3471         bool dmicclk, dmicdat;
3472
3473         wm8962->component = component;
3474
3475         wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3476         wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3477         wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3478         wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3479         wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3480         wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3481         wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3482         wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3483
3484         /* This should really be moved into the regulator core */
3485         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3486                 ret = devm_regulator_register_notifier(
3487                                                 wm8962->supplies[i].consumer,
3488                                                 &wm8962->disable_nb[i]);
3489                 if (ret != 0) {
3490                         dev_err(component->dev,
3491                                 "Failed to register regulator notifier: %d\n",
3492                                 ret);
3493                 }
3494         }
3495
3496         wm8962_add_widgets(component);
3497
3498         /* Save boards having to disable DMIC when not in use */
3499         dmicclk = false;
3500         dmicdat = false;
3501         for (i = 1; i < WM8962_MAX_GPIO; i++) {
3502                 /*
3503                  * Register 515 (WM8962_GPIO_BASE + 3) does not exist,
3504                  * so skip its access
3505                  */
3506                 if (i == 3)
3507                         continue;
3508                 switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i)
3509                         & WM8962_GP2_FN_MASK) {
3510                 case WM8962_GPIO_FN_DMICCLK:
3511                         dmicclk = true;
3512                         break;
3513                 case WM8962_GPIO_FN_DMICDAT:
3514                         dmicdat = true;
3515                         break;
3516                 default:
3517                         break;
3518                 }
3519         }
3520         if (!dmicclk || !dmicdat) {
3521                 dev_dbg(component->dev, "DMIC not in use, disabling\n");
3522                 snd_soc_dapm_nc_pin(dapm, "DMICDAT");
3523         }
3524         if (dmicclk != dmicdat)
3525                 dev_warn(component->dev, "DMIC GPIOs partially configured\n");
3526
3527         wm8962_init_beep(component);
3528         wm8962_init_gpio(component);
3529
3530         return 0;
3531 }
3532
3533 static void wm8962_remove(struct snd_soc_component *component)
3534 {
3535         struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3536
3537         cancel_delayed_work_sync(&wm8962->mic_work);
3538
3539         wm8962_free_gpio(component);
3540         wm8962_free_beep(component);
3541 }
3542
3543 static const struct snd_soc_component_driver soc_component_dev_wm8962 = {
3544         .probe                  = wm8962_probe,
3545         .remove                 = wm8962_remove,
3546         .set_bias_level         = wm8962_set_bias_level,
3547         .set_pll                = wm8962_set_fll,
3548         .use_pmdown_time        = 1,
3549         .endianness             = 1,
3550 };
3551
3552 /* Improve power consumption for IN4 DC measurement mode */
3553 static const struct reg_sequence wm8962_dc_measure[] = {
3554         { 0xfd, 0x1 },
3555         { 0xcc, 0x40 },
3556         { 0xfd, 0 },
3557 };
3558
3559 static const struct regmap_config wm8962_regmap = {
3560         .reg_bits = 16,
3561         .val_bits = 16,
3562
3563         .max_register = WM8962_MAX_REGISTER,
3564         .reg_defaults = wm8962_reg,
3565         .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3566         .volatile_reg = wm8962_volatile_register,
3567         .readable_reg = wm8962_readable_register,
3568         .cache_type = REGCACHE_RBTREE,
3569 };
3570
3571 static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3572                                     struct wm8962_pdata *pdata)
3573 {
3574         const struct device_node *np = i2c->dev.of_node;
3575         u32 val32;
3576         int i;
3577
3578         if (of_property_read_bool(np, "spk-mono"))
3579                 pdata->spk_mono = true;
3580
3581         if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3582                 pdata->mic_cfg = val32;
3583
3584         if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3585                                        ARRAY_SIZE(pdata->gpio_init)) >= 0)
3586                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3587                         /*
3588                          * The range of GPIO register value is [0x0, 0xffff]
3589                          * While the default value of each register is 0x0
3590                          * Any other value will be regarded as default value
3591                          */
3592                         if (pdata->gpio_init[i] > 0xffff)
3593                                 pdata->gpio_init[i] = 0x0;
3594                 }
3595
3596         pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL);
3597         return PTR_ERR_OR_ZERO(pdata->mclk);
3598 }
3599
3600 static int wm8962_i2c_probe(struct i2c_client *i2c)
3601 {
3602         struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3603         struct wm8962_priv *wm8962;
3604         unsigned int reg;
3605         int ret, i, irq_pol, trigger;
3606
3607         wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL);
3608         if (wm8962 == NULL)
3609                 return -ENOMEM;
3610
3611         mutex_init(&wm8962->dsp2_ena_lock);
3612
3613         i2c_set_clientdata(i2c, wm8962);
3614
3615         INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3616         init_completion(&wm8962->fll_lock);
3617         wm8962->irq = i2c->irq;
3618
3619         /* If platform data was supplied, update the default data in priv */
3620         if (pdata) {
3621                 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
3622         } else if (i2c->dev.of_node) {
3623                 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3624                 if (ret != 0)
3625                         return ret;
3626         }
3627
3628         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3629                 wm8962->supplies[i].supply = wm8962_supply_names[i];
3630
3631         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3632                                  wm8962->supplies);
3633         if (ret != 0) {
3634                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3635                 goto err;
3636         }
3637
3638         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3639                                     wm8962->supplies);
3640         if (ret != 0) {
3641                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3642                 return ret;
3643         }
3644
3645         wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3646         if (IS_ERR(wm8962->regmap)) {
3647                 ret = PTR_ERR(wm8962->regmap);
3648                 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3649                 goto err_enable;
3650         }
3651
3652         /*
3653          * We haven't marked the chip revision as volatile due to
3654          * sharing a register with the right input volume; explicitly
3655          * bypass the cache to read it.
3656          */
3657         regcache_cache_bypass(wm8962->regmap, true);
3658
3659         ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3660         if (ret < 0) {
3661                 dev_err(&i2c->dev, "Failed to read ID register\n");
3662                 goto err_enable;
3663         }
3664         if (reg != 0x6243) {
3665                 dev_err(&i2c->dev,
3666                         "Device is not a WM8962, ID %x != 0x6243\n", reg);
3667                 ret = -EINVAL;
3668                 goto err_enable;
3669         }
3670
3671         ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3672         if (ret < 0) {
3673                 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3674                         ret);
3675                 goto err_enable;
3676         }
3677
3678         dev_info(&i2c->dev, "customer id %x revision %c\n",
3679                  (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3680                  ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3681                  + 'A');
3682
3683         regcache_cache_bypass(wm8962->regmap, false);
3684
3685         ret = wm8962_reset(wm8962);
3686         if (ret < 0) {
3687                 dev_err(&i2c->dev, "Failed to issue reset\n");
3688                 goto err_enable;
3689         }
3690
3691         /* SYSCLK defaults to on; make sure it is off so we can safely
3692          * write to registers if the device is declocked.
3693          */
3694         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3695                            WM8962_SYSCLK_ENA, 0);
3696
3697         /* Ensure we have soft control over all registers */
3698         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3699                            WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3700
3701         /* Ensure that the oscillator and PLLs are disabled */
3702         regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3703                            WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3704                            0);
3705
3706         /* Apply static configuration for GPIOs */
3707         for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3708                 if (wm8962->pdata.gpio_init[i]) {
3709                         wm8962_set_gpio_mode(wm8962, i + 1);
3710                         regmap_write(wm8962->regmap, 0x200 + i,
3711                                      wm8962->pdata.gpio_init[i] & 0xffff);
3712                 }
3713
3714
3715         /* Put the speakers into mono mode? */
3716         if (wm8962->pdata.spk_mono)
3717                 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3718                                    WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3719
3720         /* Micbias setup, detection enable and detection
3721          * threasholds. */
3722         if (wm8962->pdata.mic_cfg)
3723                 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3724                                    WM8962_MICDET_ENA |
3725                                    WM8962_MICDET_THR_MASK |
3726                                    WM8962_MICSHORT_THR_MASK |
3727                                    WM8962_MICBIAS_LVL,
3728                                    wm8962->pdata.mic_cfg);
3729
3730         /* Latch volume update bits */
3731         regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3732                            WM8962_IN_VU, WM8962_IN_VU);
3733         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3734                            WM8962_IN_VU, WM8962_IN_VU);
3735         regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3736                            WM8962_ADC_VU, WM8962_ADC_VU);
3737         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3738                            WM8962_ADC_VU, WM8962_ADC_VU);
3739         regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3740                            WM8962_DAC_VU, WM8962_DAC_VU);
3741         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3742                            WM8962_DAC_VU, WM8962_DAC_VU);
3743         regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3744                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3745         regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3746                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3747         regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3748                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3749         regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3750                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3751
3752         /* Stereo control for EQ */
3753         regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3754                            WM8962_EQ_SHARED_COEFF, 0);
3755
3756         /* Don't debouce interrupts so we don't need SYSCLK */
3757         regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3758                            WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3759                            WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3760                            0);
3761
3762         if (wm8962->pdata.in4_dc_measure) {
3763                 ret = regmap_register_patch(wm8962->regmap,
3764                                             wm8962_dc_measure,
3765                                             ARRAY_SIZE(wm8962_dc_measure));
3766                 if (ret != 0)
3767                         dev_err(&i2c->dev,
3768                                 "Failed to configure for DC measurement: %d\n",
3769                                 ret);
3770         }
3771
3772         if (wm8962->irq) {
3773                 if (wm8962->pdata.irq_active_low) {
3774                         trigger = IRQF_TRIGGER_LOW;
3775                         irq_pol = WM8962_IRQ_POL;
3776                 } else {
3777                         trigger = IRQF_TRIGGER_HIGH;
3778                         irq_pol = 0;
3779                 }
3780
3781                 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3782                                    WM8962_IRQ_POL, irq_pol);
3783
3784                 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3785                                                 wm8962_irq,
3786                                                 trigger | IRQF_ONESHOT,
3787                                                 "wm8962", &i2c->dev);
3788                 if (ret != 0) {
3789                         dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3790                                 wm8962->irq, ret);
3791                         wm8962->irq = 0;
3792                         /* Non-fatal */
3793                 } else {
3794                         /* Enable some IRQs by default */
3795                         regmap_update_bits(wm8962->regmap,
3796                                            WM8962_INTERRUPT_STATUS_2_MASK,
3797                                            WM8962_FLL_LOCK_EINT |
3798                                            WM8962_TEMP_SHUT_EINT |
3799                                            WM8962_FIFOS_ERR_EINT, 0);
3800                 }
3801         }
3802
3803         pm_runtime_enable(&i2c->dev);
3804         pm_request_idle(&i2c->dev);
3805
3806         ret = devm_snd_soc_register_component(&i2c->dev,
3807                                      &soc_component_dev_wm8962, &wm8962_dai, 1);
3808         if (ret < 0)
3809                 goto err_pm_runtime;
3810
3811         regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3812                             WM8962_TEMP_ENA_HP_MASK, 0);
3813         regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3814                             WM8962_TEMP_ENA_SPK_MASK, 0);
3815
3816         regcache_cache_only(wm8962->regmap, true);
3817
3818         /* The drivers should power up as needed */
3819         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3820
3821         return 0;
3822
3823 err_pm_runtime:
3824         pm_runtime_disable(&i2c->dev);
3825 err_enable:
3826         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3827 err:
3828         return ret;
3829 }
3830
3831 static void wm8962_i2c_remove(struct i2c_client *client)
3832 {
3833         pm_runtime_disable(&client->dev);
3834 }
3835
3836 #ifdef CONFIG_PM
3837 static int wm8962_runtime_resume(struct device *dev)
3838 {
3839         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3840         int ret;
3841
3842         ret = clk_prepare_enable(wm8962->pdata.mclk);
3843         if (ret) {
3844                 dev_err(dev, "Failed to enable MCLK: %d\n", ret);
3845                 return ret;
3846         }
3847
3848         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3849                                     wm8962->supplies);
3850         if (ret != 0) {
3851                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
3852                 goto disable_clock;
3853         }
3854
3855         regcache_cache_only(wm8962->regmap, false);
3856
3857         wm8962_reset(wm8962);
3858
3859         regcache_mark_dirty(wm8962->regmap);
3860
3861         /* SYSCLK defaults to on; make sure it is off so we can safely
3862          * write to registers if the device is declocked.
3863          */
3864         regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2,
3865                           WM8962_SYSCLK_ENA, 0);
3866
3867         /* Ensure we have soft control over all registers */
3868         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3869                            WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3870
3871         /* Ensure that the oscillator and PLLs are disabled */
3872         regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3873                            WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3874                            0);
3875
3876         regcache_sync(wm8962->regmap);
3877
3878         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3879                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3880                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3881
3882         /* Bias enable at 2*5k (fast start-up) */
3883         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3884                            WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3885                            WM8962_BIAS_ENA | 0x180);
3886
3887         msleep(5);
3888
3889         return 0;
3890
3891 disable_clock:
3892         clk_disable_unprepare(wm8962->pdata.mclk);
3893         return ret;
3894 }
3895
3896 static int wm8962_runtime_suspend(struct device *dev)
3897 {
3898         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3899
3900         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3901                            WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3902
3903         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3904                            WM8962_STARTUP_BIAS_ENA |
3905                            WM8962_VMID_BUF_ENA, 0);
3906
3907         regcache_cache_only(wm8962->regmap, true);
3908
3909         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3910                                wm8962->supplies);
3911
3912         clk_disable_unprepare(wm8962->pdata.mclk);
3913
3914         return 0;
3915 }
3916 #endif
3917
3918 static const struct dev_pm_ops wm8962_pm = {
3919         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3920         SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3921 };
3922
3923 static const struct i2c_device_id wm8962_i2c_id[] = {
3924         { "wm8962", 0 },
3925         { }
3926 };
3927 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3928
3929 static const struct of_device_id wm8962_of_match[] = {
3930         { .compatible = "wlf,wm8962", },
3931         { }
3932 };
3933 MODULE_DEVICE_TABLE(of, wm8962_of_match);
3934
3935 static struct i2c_driver wm8962_i2c_driver = {
3936         .driver = {
3937                 .name = "wm8962",
3938                 .of_match_table = wm8962_of_match,
3939                 .pm = &wm8962_pm,
3940         },
3941         .probe_new = wm8962_i2c_probe,
3942         .remove =   wm8962_i2c_remove,
3943         .id_table = wm8962_i2c_id,
3944 };
3945
3946 module_i2c_driver(wm8962_i2c_driver);
3947
3948 MODULE_DESCRIPTION("ASoC WM8962 driver");
3949 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3950 MODULE_LICENSE("GPL");