sound/soc/codecs/rt5682.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * rt5682.c  --  RT5682 ALSA SoC audio component driver
   4  *
   5  * Copyright 2018 Realtek Semiconductor Corp.
   6  * Author: Bard Liao <bardliao@realtek.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/i2c.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/acpi.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/mutex.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/jack.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30 #include <sound/rt5682.h>
  31
  32 #include "rl6231.h"
  33 #include "rt5682.h"
  34
  35 #define RT5682_NUM_SUPPLIES 3
  36
  37 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  38         "AVDD",
  39         "MICVDD",
  40         "VBAT",
  41 };
  42
  43 static const struct rt5682_platform_data i2s_default_platform_data = {
  44         .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2,
  45         .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
  46         .jd_src = RT5682_JD1,
  47         .btndet_delay = 16,
  48 };
  49
  50 struct rt5682_priv {
  51         struct snd_soc_component *component;
  52         struct rt5682_platform_data pdata;
  53         struct regmap *regmap;
  54         struct snd_soc_jack *hs_jack;
  55         struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
  56         struct delayed_work jack_detect_work;
  57         struct delayed_work jd_check_work;
  58         struct mutex calibrate_mutex;
  59
  60         int sysclk;
  61         int sysclk_src;
  62         int lrck[RT5682_AIFS];
  63         int bclk[RT5682_AIFS];
  64         int master[RT5682_AIFS];
  65
  66         int pll_src;
  67         int pll_in;
  68         int pll_out;
  69
  70         int jack_type;
  71 };
  72
  73 static const struct reg_sequence patch_list[] = {
  74         {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  75         {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  76         {RT5682_I2C_CTRL, 0x000f},
  77 };
  78
  79 static const struct reg_default rt5682_reg[] = {
  80         {0x0002, 0x8080},
  81         {0x0003, 0x8000},
  82         {0x0005, 0x0000},
  83         {0x0006, 0x0000},
  84         {0x0008, 0x800f},
  85         {0x000b, 0x0000},
  86         {0x0010, 0x4040},
  87         {0x0011, 0x0000},
  88         {0x0012, 0x1404},
  89         {0x0013, 0x1000},
  90         {0x0014, 0xa00a},
  91         {0x0015, 0x0404},
  92         {0x0016, 0x0404},
  93         {0x0019, 0xafaf},
  94         {0x001c, 0x2f2f},
  95         {0x001f, 0x0000},
  96         {0x0022, 0x5757},
  97         {0x0023, 0x0039},
  98         {0x0024, 0x000b},
  99         {0x0026, 0xc0c4},
 100         {0x0029, 0x8080},
 101         {0x002a, 0xa0a0},
 102         {0x002b, 0x0300},
 103         {0x0030, 0x0000},
 104         {0x003c, 0x0080},
 105         {0x0044, 0x0c0c},
 106         {0x0049, 0x0000},
 107         {0x0061, 0x0000},
 108         {0x0062, 0x0000},
 109         {0x0063, 0x003f},
 110         {0x0064, 0x0000},
 111         {0x0065, 0x0000},
 112         {0x0066, 0x0030},
 113         {0x0067, 0x0000},
 114         {0x006b, 0x0000},
 115         {0x006c, 0x0000},
 116         {0x006d, 0x2200},
 117         {0x006e, 0x0a10},
 118         {0x0070, 0x8000},
 119         {0x0071, 0x8000},
 120         {0x0073, 0x0000},
 121         {0x0074, 0x0000},
 122         {0x0075, 0x0002},
 123         {0x0076, 0x0001},
 124         {0x0079, 0x0000},
 125         {0x007a, 0x0000},
 126         {0x007b, 0x0000},
 127         {0x007c, 0x0100},
 128         {0x007e, 0x0000},
 129         {0x0080, 0x0000},
 130         {0x0081, 0x0000},
 131         {0x0082, 0x0000},
 132         {0x0083, 0x0000},
 133         {0x0084, 0x0000},
 134         {0x0085, 0x0000},
 135         {0x0086, 0x0005},
 136         {0x0087, 0x0000},
 137         {0x0088, 0x0000},
 138         {0x008c, 0x0003},
 139         {0x008d, 0x0000},
 140         {0x008e, 0x0060},
 141         {0x008f, 0x1000},
 142         {0x0091, 0x0c26},
 143         {0x0092, 0x0073},
 144         {0x0093, 0x0000},
 145         {0x0094, 0x0080},
 146         {0x0098, 0x0000},
 147         {0x009a, 0x0000},
 148         {0x009b, 0x0000},
 149         {0x009c, 0x0000},
 150         {0x009d, 0x0000},
 151         {0x009e, 0x100c},
 152         {0x009f, 0x0000},
 153         {0x00a0, 0x0000},
 154         {0x00a3, 0x0002},
 155         {0x00a4, 0x0001},
 156         {0x00ae, 0x2040},
 157         {0x00af, 0x0000},
 158         {0x00b6, 0x0000},
 159         {0x00b7, 0x0000},
 160         {0x00b8, 0x0000},
 161         {0x00b9, 0x0002},
 162         {0x00be, 0x0000},
 163         {0x00c0, 0x0160},
 164         {0x00c1, 0x82a0},
 165         {0x00c2, 0x0000},
 166         {0x00d0, 0x0000},
 167         {0x00d1, 0x2244},
 168         {0x00d2, 0x3300},
 169         {0x00d3, 0x2200},
 170         {0x00d4, 0x0000},
 171         {0x00d9, 0x0009},
 172         {0x00da, 0x0000},
 173         {0x00db, 0x0000},
 174         {0x00dc, 0x00c0},
 175         {0x00dd, 0x2220},
 176         {0x00de, 0x3131},
 177         {0x00df, 0x3131},
 178         {0x00e0, 0x3131},
 179         {0x00e2, 0x0000},
 180         {0x00e3, 0x4000},
 181         {0x00e4, 0x0aa0},
 182         {0x00e5, 0x3131},
 183         {0x00e6, 0x3131},
 184         {0x00e7, 0x3131},
 185         {0x00e8, 0x3131},
 186         {0x00ea, 0xb320},
 187         {0x00eb, 0x0000},
 188         {0x00f0, 0x0000},
 189         {0x00f1, 0x00d0},
 190         {0x00f2, 0x00d0},
 191         {0x00f6, 0x0000},
 192         {0x00fa, 0x0000},
 193         {0x00fb, 0x0000},
 194         {0x00fc, 0x0000},
 195         {0x00fd, 0x0000},
 196         {0x00fe, 0x10ec},
 197         {0x00ff, 0x6530},
 198         {0x0100, 0xa0a0},
 199         {0x010b, 0x0000},
 200         {0x010c, 0xae00},
 201         {0x010d, 0xaaa0},
 202         {0x010e, 0x8aa2},
 203         {0x010f, 0x02a2},
 204         {0x0110, 0xc000},
 205         {0x0111, 0x04a2},
 206         {0x0112, 0x2800},
 207         {0x0113, 0x0000},
 208         {0x0117, 0x0100},
 209         {0x0125, 0x0410},
 210         {0x0132, 0x6026},
 211         {0x0136, 0x5555},
 212         {0x0138, 0x3700},
 213         {0x013a, 0x2000},
 214         {0x013b, 0x2000},
 215         {0x013c, 0x2005},
 216         {0x013f, 0x0000},
 217         {0x0142, 0x0000},
 218         {0x0145, 0x0002},
 219         {0x0146, 0x0000},
 220         {0x0147, 0x0000},
 221         {0x0148, 0x0000},
 222         {0x0149, 0x0000},
 223         {0x0150, 0x79a1},
 224         {0x0151, 0x0000},
 225         {0x0160, 0x4ec0},
 226         {0x0161, 0x0080},
 227         {0x0162, 0x0200},
 228         {0x0163, 0x0800},
 229         {0x0164, 0x0000},
 230         {0x0165, 0x0000},
 231         {0x0166, 0x0000},
 232         {0x0167, 0x000f},
 233         {0x0168, 0x000f},
 234         {0x0169, 0x0021},
 235         {0x0190, 0x413d},
 236         {0x0194, 0x0000},
 237         {0x0195, 0x0000},
 238         {0x0197, 0x0022},
 239         {0x0198, 0x0000},
 240         {0x0199, 0x0000},
 241         {0x01af, 0x0000},
 242         {0x01b0, 0x0400},
 243         {0x01b1, 0x0000},
 244         {0x01b2, 0x0000},
 245         {0x01b3, 0x0000},
 246         {0x01b4, 0x0000},
 247         {0x01b5, 0x0000},
 248         {0x01b6, 0x01c3},
 249         {0x01b7, 0x02a0},
 250         {0x01b8, 0x03e9},
 251         {0x01b9, 0x1389},
 252         {0x01ba, 0xc351},
 253         {0x01bb, 0x0009},
 254         {0x01bc, 0x0018},
 255         {0x01bd, 0x002a},
 256         {0x01be, 0x004c},
 257         {0x01bf, 0x0097},
 258         {0x01c0, 0x433d},
 259         {0x01c2, 0x0000},
 260         {0x01c3, 0x0000},
 261         {0x01c4, 0x0000},
 262         {0x01c5, 0x0000},
 263         {0x01c6, 0x0000},
 264         {0x01c7, 0x0000},
 265         {0x01c8, 0x40af},
 266         {0x01c9, 0x0702},
 267         {0x01ca, 0x0000},
 268         {0x01cb, 0x0000},
 269         {0x01cc, 0x5757},
 270         {0x01cd, 0x5757},
 271         {0x01ce, 0x5757},
 272         {0x01cf, 0x5757},
 273         {0x01d0, 0x5757},
 274         {0x01d1, 0x5757},
 275         {0x01d2, 0x5757},
 276         {0x01d3, 0x5757},
 277         {0x01d4, 0x5757},
 278         {0x01d5, 0x5757},
 279         {0x01d6, 0x0000},
 280         {0x01d7, 0x0008},
 281         {0x01d8, 0x0029},
 282         {0x01d9, 0x3333},
 283         {0x01da, 0x0000},
 284         {0x01db, 0x0004},
 285         {0x01dc, 0x0000},
 286         {0x01de, 0x7c00},
 287         {0x01df, 0x0320},
 288         {0x01e0, 0x06a1},
 289         {0x01e1, 0x0000},
 290         {0x01e2, 0x0000},
 291         {0x01e3, 0x0000},
 292         {0x01e4, 0x0000},
 293         {0x01e6, 0x0001},
 294         {0x01e7, 0x0000},
 295         {0x01e8, 0x0000},
 296         {0x01ea, 0x0000},
 297         {0x01eb, 0x0000},
 298         {0x01ec, 0x0000},
 299         {0x01ed, 0x0000},
 300         {0x01ee, 0x0000},
 301         {0x01ef, 0x0000},
 302         {0x01f0, 0x0000},
 303         {0x01f1, 0x0000},
 304         {0x01f2, 0x0000},
 305         {0x01f3, 0x0000},
 306         {0x01f4, 0x0000},
 307         {0x0210, 0x6297},
 308         {0x0211, 0xa005},
 309         {0x0212, 0x824c},
 310         {0x0213, 0xf7ff},
 311         {0x0214, 0xf24c},
 312         {0x0215, 0x0102},
 313         {0x0216, 0x00a3},
 314         {0x0217, 0x0048},
 315         {0x0218, 0xa2c0},
 316         {0x0219, 0x0400},
 317         {0x021a, 0x00c8},
 318         {0x021b, 0x00c0},
 319         {0x021c, 0x0000},
 320         {0x0250, 0x4500},
 321         {0x0251, 0x40b3},
 322         {0x0252, 0x0000},
 323         {0x0253, 0x0000},
 324         {0x0254, 0x0000},
 325         {0x0255, 0x0000},
 326         {0x0256, 0x0000},
 327         {0x0257, 0x0000},
 328         {0x0258, 0x0000},
 329         {0x0259, 0x0000},
 330         {0x025a, 0x0005},
 331         {0x0270, 0x0000},
 332         {0x02ff, 0x0110},
 333         {0x0300, 0x001f},
 334         {0x0301, 0x032c},
 335         {0x0302, 0x5f21},
 336         {0x0303, 0x4000},
 337         {0x0304, 0x4000},
 338         {0x0305, 0x06d5},
 339         {0x0306, 0x8000},
 340         {0x0307, 0x0700},
 341         {0x0310, 0x4560},
 342         {0x0311, 0xa4a8},
 343         {0x0312, 0x7418},
 344         {0x0313, 0x0000},
 345         {0x0314, 0x0006},
 346         {0x0315, 0xffff},
 347         {0x0316, 0xc400},
 348         {0x0317, 0x0000},
 349         {0x03c0, 0x7e00},
 350         {0x03c1, 0x8000},
 351         {0x03c2, 0x8000},
 352         {0x03c3, 0x8000},
 353         {0x03c4, 0x8000},
 354         {0x03c5, 0x8000},
 355         {0x03c6, 0x8000},
 356         {0x03c7, 0x8000},
 357         {0x03c8, 0x8000},
 358         {0x03c9, 0x8000},
 359         {0x03ca, 0x8000},
 360         {0x03cb, 0x8000},
 361         {0x03cc, 0x8000},
 362         {0x03d0, 0x0000},
 363         {0x03d1, 0x0000},
 364         {0x03d2, 0x0000},
 365         {0x03d3, 0x0000},
 366         {0x03d4, 0x2000},
 367         {0x03d5, 0x2000},
 368         {0x03d6, 0x0000},
 369         {0x03d7, 0x0000},
 370         {0x03d8, 0x2000},
 371         {0x03d9, 0x2000},
 372         {0x03da, 0x2000},
 373         {0x03db, 0x2000},
 374         {0x03dc, 0x0000},
 375         {0x03dd, 0x0000},
 376         {0x03de, 0x0000},
 377         {0x03df, 0x2000},
 378         {0x03e0, 0x0000},
 379         {0x03e1, 0x0000},
 380         {0x03e2, 0x0000},
 381         {0x03e3, 0x0000},
 382         {0x03e4, 0x0000},
 383         {0x03e5, 0x0000},
 384         {0x03e6, 0x0000},
 385         {0x03e7, 0x0000},
 386         {0x03e8, 0x0000},
 387         {0x03e9, 0x0000},
 388         {0x03ea, 0x0000},
 389         {0x03eb, 0x0000},
 390         {0x03ec, 0x0000},
 391         {0x03ed, 0x0000},
 392         {0x03ee, 0x0000},
 393         {0x03ef, 0x0000},
 394         {0x03f0, 0x0800},
 395         {0x03f1, 0x0800},
 396         {0x03f2, 0x0800},
 397         {0x03f3, 0x0800},
 398 };
 399
 400 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
 401 {
 402         switch (reg) {
 403         case RT5682_RESET:
 404         case RT5682_CBJ_CTRL_2:
 405         case RT5682_INT_ST_1:
 406         case RT5682_4BTN_IL_CMD_1:
 407         case RT5682_AJD1_CTRL:
 408         case RT5682_HP_CALIB_CTRL_1:
 409         case RT5682_DEVICE_ID:
 410         case RT5682_I2C_MODE:
 411         case RT5682_HP_CALIB_CTRL_10:
 412         case RT5682_EFUSE_CTRL_2:
 413         case RT5682_JD_TOP_VC_VTRL:
 414         case RT5682_HP_IMP_SENS_CTRL_19:
 415         case RT5682_IL_CMD_1:
 416         case RT5682_SAR_IL_CMD_2:
 417         case RT5682_SAR_IL_CMD_4:
 418         case RT5682_SAR_IL_CMD_10:
 419         case RT5682_SAR_IL_CMD_11:
 420         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
 421         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
 422                 return true;
 423         default:
 424                 return false;
 425         }
 426 }
 427
 428 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
 429 {
 430         switch (reg) {
 431         case RT5682_RESET:
 432         case RT5682_VERSION_ID:
 433         case RT5682_VENDOR_ID:
 434         case RT5682_DEVICE_ID:
 435         case RT5682_HP_CTRL_1:
 436         case RT5682_HP_CTRL_2:
 437         case RT5682_HPL_GAIN:
 438         case RT5682_HPR_GAIN:
 439         case RT5682_I2C_CTRL:
 440         case RT5682_CBJ_BST_CTRL:
 441         case RT5682_CBJ_CTRL_1:
 442         case RT5682_CBJ_CTRL_2:
 443         case RT5682_CBJ_CTRL_3:
 444         case RT5682_CBJ_CTRL_4:
 445         case RT5682_CBJ_CTRL_5:
 446         case RT5682_CBJ_CTRL_6:
 447         case RT5682_CBJ_CTRL_7:
 448         case RT5682_DAC1_DIG_VOL:
 449         case RT5682_STO1_ADC_DIG_VOL:
 450         case RT5682_STO1_ADC_BOOST:
 451         case RT5682_HP_IMP_GAIN_1:
 452         case RT5682_HP_IMP_GAIN_2:
 453         case RT5682_SIDETONE_CTRL:
 454         case RT5682_STO1_ADC_MIXER:
 455         case RT5682_AD_DA_MIXER:
 456         case RT5682_STO1_DAC_MIXER:
 457         case RT5682_A_DAC1_MUX:
 458         case RT5682_DIG_INF2_DATA:
 459         case RT5682_REC_MIXER:
 460         case RT5682_CAL_REC:
 461         case RT5682_ALC_BACK_GAIN:
 462         case RT5682_PWR_DIG_1:
 463         case RT5682_PWR_DIG_2:
 464         case RT5682_PWR_ANLG_1:
 465         case RT5682_PWR_ANLG_2:
 466         case RT5682_PWR_ANLG_3:
 467         case RT5682_PWR_MIXER:
 468         case RT5682_PWR_VOL:
 469         case RT5682_CLK_DET:
 470         case RT5682_RESET_LPF_CTRL:
 471         case RT5682_RESET_HPF_CTRL:
 472         case RT5682_DMIC_CTRL_1:
 473         case RT5682_I2S1_SDP:
 474         case RT5682_I2S2_SDP:
 475         case RT5682_ADDA_CLK_1:
 476         case RT5682_ADDA_CLK_2:
 477         case RT5682_I2S1_F_DIV_CTRL_1:
 478         case RT5682_I2S1_F_DIV_CTRL_2:
 479         case RT5682_TDM_CTRL:
 480         case RT5682_TDM_ADDA_CTRL_1:
 481         case RT5682_TDM_ADDA_CTRL_2:
 482         case RT5682_DATA_SEL_CTRL_1:
 483         case RT5682_TDM_TCON_CTRL:
 484         case RT5682_GLB_CLK:
 485         case RT5682_PLL_CTRL_1:
 486         case RT5682_PLL_CTRL_2:
 487         case RT5682_PLL_TRACK_1:
 488         case RT5682_PLL_TRACK_2:
 489         case RT5682_PLL_TRACK_3:
 490         case RT5682_PLL_TRACK_4:
 491         case RT5682_PLL_TRACK_5:
 492         case RT5682_PLL_TRACK_6:
 493         case RT5682_PLL_TRACK_11:
 494         case RT5682_SDW_REF_CLK:
 495         case RT5682_DEPOP_1:
 496         case RT5682_DEPOP_2:
 497         case RT5682_HP_CHARGE_PUMP_1:
 498         case RT5682_HP_CHARGE_PUMP_2:
 499         case RT5682_MICBIAS_1:
 500         case RT5682_MICBIAS_2:
 501         case RT5682_PLL_TRACK_12:
 502         case RT5682_PLL_TRACK_14:
 503         case RT5682_PLL2_CTRL_1:
 504         case RT5682_PLL2_CTRL_2:
 505         case RT5682_PLL2_CTRL_3:
 506         case RT5682_PLL2_CTRL_4:
 507         case RT5682_RC_CLK_CTRL:
 508         case RT5682_I2S_M_CLK_CTRL_1:
 509         case RT5682_I2S2_F_DIV_CTRL_1:
 510         case RT5682_I2S2_F_DIV_CTRL_2:
 511         case RT5682_EQ_CTRL_1:
 512         case RT5682_EQ_CTRL_2:
 513         case RT5682_IRQ_CTRL_1:
 514         case RT5682_IRQ_CTRL_2:
 515         case RT5682_IRQ_CTRL_3:
 516         case RT5682_IRQ_CTRL_4:
 517         case RT5682_INT_ST_1:
 518         case RT5682_GPIO_CTRL_1:
 519         case RT5682_GPIO_CTRL_2:
 520         case RT5682_GPIO_CTRL_3:
 521         case RT5682_HP_AMP_DET_CTRL_1:
 522         case RT5682_HP_AMP_DET_CTRL_2:
 523         case RT5682_MID_HP_AMP_DET:
 524         case RT5682_LOW_HP_AMP_DET:
 525         case RT5682_DELAY_BUF_CTRL:
 526         case RT5682_SV_ZCD_1:
 527         case RT5682_SV_ZCD_2:
 528         case RT5682_IL_CMD_1:
 529         case RT5682_IL_CMD_2:
 530         case RT5682_IL_CMD_3:
 531         case RT5682_IL_CMD_4:
 532         case RT5682_IL_CMD_5:
 533         case RT5682_IL_CMD_6:
 534         case RT5682_4BTN_IL_CMD_1:
 535         case RT5682_4BTN_IL_CMD_2:
 536         case RT5682_4BTN_IL_CMD_3:
 537         case RT5682_4BTN_IL_CMD_4:
 538         case RT5682_4BTN_IL_CMD_5:
 539         case RT5682_4BTN_IL_CMD_6:
 540         case RT5682_4BTN_IL_CMD_7:
 541         case RT5682_ADC_STO1_HP_CTRL_1:
 542         case RT5682_ADC_STO1_HP_CTRL_2:
 543         case RT5682_AJD1_CTRL:
 544         case RT5682_JD1_THD:
 545         case RT5682_JD2_THD:
 546         case RT5682_JD_CTRL_1:
 547         case RT5682_DUMMY_1:
 548         case RT5682_DUMMY_2:
 549         case RT5682_DUMMY_3:
 550         case RT5682_DAC_ADC_DIG_VOL1:
 551         case RT5682_BIAS_CUR_CTRL_2:
 552         case RT5682_BIAS_CUR_CTRL_3:
 553         case RT5682_BIAS_CUR_CTRL_4:
 554         case RT5682_BIAS_CUR_CTRL_5:
 555         case RT5682_BIAS_CUR_CTRL_6:
 556         case RT5682_BIAS_CUR_CTRL_7:
 557         case RT5682_BIAS_CUR_CTRL_8:
 558         case RT5682_BIAS_CUR_CTRL_9:
 559         case RT5682_BIAS_CUR_CTRL_10:
 560         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
 561         case RT5682_CHARGE_PUMP_1:
 562         case RT5682_DIG_IN_CTRL_1:
 563         case RT5682_PAD_DRIVING_CTRL:
 564         case RT5682_SOFT_RAMP_DEPOP:
 565         case RT5682_CHOP_DAC:
 566         case RT5682_CHOP_ADC:
 567         case RT5682_CALIB_ADC_CTRL:
 568         case RT5682_VOL_TEST:
 569         case RT5682_SPKVDD_DET_STA:
 570         case RT5682_TEST_MODE_CTRL_1:
 571         case RT5682_TEST_MODE_CTRL_2:
 572         case RT5682_TEST_MODE_CTRL_3:
 573         case RT5682_TEST_MODE_CTRL_4:
 574         case RT5682_TEST_MODE_CTRL_5:
 575         case RT5682_PLL1_INTERNAL:
 576         case RT5682_PLL2_INTERNAL:
 577         case RT5682_STO_NG2_CTRL_1:
 578         case RT5682_STO_NG2_CTRL_2:
 579         case RT5682_STO_NG2_CTRL_3:
 580         case RT5682_STO_NG2_CTRL_4:
 581         case RT5682_STO_NG2_CTRL_5:
 582         case RT5682_STO_NG2_CTRL_6:
 583         case RT5682_STO_NG2_CTRL_7:
 584         case RT5682_STO_NG2_CTRL_8:
 585         case RT5682_STO_NG2_CTRL_9:
 586         case RT5682_STO_NG2_CTRL_10:
 587         case RT5682_STO1_DAC_SIL_DET:
 588         case RT5682_SIL_PSV_CTRL1:
 589         case RT5682_SIL_PSV_CTRL2:
 590         case RT5682_SIL_PSV_CTRL3:
 591         case RT5682_SIL_PSV_CTRL4:
 592         case RT5682_SIL_PSV_CTRL5:
 593         case RT5682_HP_IMP_SENS_CTRL_01:
 594         case RT5682_HP_IMP_SENS_CTRL_02:
 595         case RT5682_HP_IMP_SENS_CTRL_03:
 596         case RT5682_HP_IMP_SENS_CTRL_04:
 597         case RT5682_HP_IMP_SENS_CTRL_05:
 598         case RT5682_HP_IMP_SENS_CTRL_06:
 599         case RT5682_HP_IMP_SENS_CTRL_07:
 600         case RT5682_HP_IMP_SENS_CTRL_08:
 601         case RT5682_HP_IMP_SENS_CTRL_09:
 602         case RT5682_HP_IMP_SENS_CTRL_10:
 603         case RT5682_HP_IMP_SENS_CTRL_11:
 604         case RT5682_HP_IMP_SENS_CTRL_12:
 605         case RT5682_HP_IMP_SENS_CTRL_13:
 606         case RT5682_HP_IMP_SENS_CTRL_14:
 607         case RT5682_HP_IMP_SENS_CTRL_15:
 608         case RT5682_HP_IMP_SENS_CTRL_16:
 609         case RT5682_HP_IMP_SENS_CTRL_17:
 610         case RT5682_HP_IMP_SENS_CTRL_18:
 611         case RT5682_HP_IMP_SENS_CTRL_19:
 612         case RT5682_HP_IMP_SENS_CTRL_20:
 613         case RT5682_HP_IMP_SENS_CTRL_21:
 614         case RT5682_HP_IMP_SENS_CTRL_22:
 615         case RT5682_HP_IMP_SENS_CTRL_23:
 616         case RT5682_HP_IMP_SENS_CTRL_24:
 617         case RT5682_HP_IMP_SENS_CTRL_25:
 618         case RT5682_HP_IMP_SENS_CTRL_26:
 619         case RT5682_HP_IMP_SENS_CTRL_27:
 620         case RT5682_HP_IMP_SENS_CTRL_28:
 621         case RT5682_HP_IMP_SENS_CTRL_29:
 622         case RT5682_HP_IMP_SENS_CTRL_30:
 623         case RT5682_HP_IMP_SENS_CTRL_31:
 624         case RT5682_HP_IMP_SENS_CTRL_32:
 625         case RT5682_HP_IMP_SENS_CTRL_33:
 626         case RT5682_HP_IMP_SENS_CTRL_34:
 627         case RT5682_HP_IMP_SENS_CTRL_35:
 628         case RT5682_HP_IMP_SENS_CTRL_36:
 629         case RT5682_HP_IMP_SENS_CTRL_37:
 630         case RT5682_HP_IMP_SENS_CTRL_38:
 631         case RT5682_HP_IMP_SENS_CTRL_39:
 632         case RT5682_HP_IMP_SENS_CTRL_40:
 633         case RT5682_HP_IMP_SENS_CTRL_41:
 634         case RT5682_HP_IMP_SENS_CTRL_42:
 635         case RT5682_HP_IMP_SENS_CTRL_43:
 636         case RT5682_HP_LOGIC_CTRL_1:
 637         case RT5682_HP_LOGIC_CTRL_2:
 638         case RT5682_HP_LOGIC_CTRL_3:
 639         case RT5682_HP_CALIB_CTRL_1:
 640         case RT5682_HP_CALIB_CTRL_2:
 641         case RT5682_HP_CALIB_CTRL_3:
 642         case RT5682_HP_CALIB_CTRL_4:
 643         case RT5682_HP_CALIB_CTRL_5:
 644         case RT5682_HP_CALIB_CTRL_6:
 645         case RT5682_HP_CALIB_CTRL_7:
 646         case RT5682_HP_CALIB_CTRL_9:
 647         case RT5682_HP_CALIB_CTRL_10:
 648         case RT5682_HP_CALIB_CTRL_11:
 649         case RT5682_HP_CALIB_STA_1:
 650         case RT5682_HP_CALIB_STA_2:
 651         case RT5682_HP_CALIB_STA_3:
 652         case RT5682_HP_CALIB_STA_4:
 653         case RT5682_HP_CALIB_STA_5:
 654         case RT5682_HP_CALIB_STA_6:
 655         case RT5682_HP_CALIB_STA_7:
 656         case RT5682_HP_CALIB_STA_8:
 657         case RT5682_HP_CALIB_STA_9:
 658         case RT5682_HP_CALIB_STA_10:
 659         case RT5682_HP_CALIB_STA_11:
 660         case RT5682_SAR_IL_CMD_1:
 661         case RT5682_SAR_IL_CMD_2:
 662         case RT5682_SAR_IL_CMD_3:
 663         case RT5682_SAR_IL_CMD_4:
 664         case RT5682_SAR_IL_CMD_5:
 665         case RT5682_SAR_IL_CMD_6:
 666         case RT5682_SAR_IL_CMD_7:
 667         case RT5682_SAR_IL_CMD_8:
 668         case RT5682_SAR_IL_CMD_9:
 669         case RT5682_SAR_IL_CMD_10:
 670         case RT5682_SAR_IL_CMD_11:
 671         case RT5682_SAR_IL_CMD_12:
 672         case RT5682_SAR_IL_CMD_13:
 673         case RT5682_EFUSE_CTRL_1:
 674         case RT5682_EFUSE_CTRL_2:
 675         case RT5682_EFUSE_CTRL_3:
 676         case RT5682_EFUSE_CTRL_4:
 677         case RT5682_EFUSE_CTRL_5:
 678         case RT5682_EFUSE_CTRL_6:
 679         case RT5682_EFUSE_CTRL_7:
 680         case RT5682_EFUSE_CTRL_8:
 681         case RT5682_EFUSE_CTRL_9:
 682         case RT5682_EFUSE_CTRL_10:
 683         case RT5682_EFUSE_CTRL_11:
 684         case RT5682_JD_TOP_VC_VTRL:
 685         case RT5682_DRC1_CTRL_0:
 686         case RT5682_DRC1_CTRL_1:
 687         case RT5682_DRC1_CTRL_2:
 688         case RT5682_DRC1_CTRL_3:
 689         case RT5682_DRC1_CTRL_4:
 690         case RT5682_DRC1_CTRL_5:
 691         case RT5682_DRC1_CTRL_6:
 692         case RT5682_DRC1_HARD_LMT_CTRL_1:
 693         case RT5682_DRC1_HARD_LMT_CTRL_2:
 694         case RT5682_DRC1_PRIV_1:
 695         case RT5682_DRC1_PRIV_2:
 696         case RT5682_DRC1_PRIV_3:
 697         case RT5682_DRC1_PRIV_4:
 698         case RT5682_DRC1_PRIV_5:
 699         case RT5682_DRC1_PRIV_6:
 700         case RT5682_DRC1_PRIV_7:
 701         case RT5682_DRC1_PRIV_8:
 702         case RT5682_EQ_AUTO_RCV_CTRL1:
 703         case RT5682_EQ_AUTO_RCV_CTRL2:
 704         case RT5682_EQ_AUTO_RCV_CTRL3:
 705         case RT5682_EQ_AUTO_RCV_CTRL4:
 706         case RT5682_EQ_AUTO_RCV_CTRL5:
 707         case RT5682_EQ_AUTO_RCV_CTRL6:
 708         case RT5682_EQ_AUTO_RCV_CTRL7:
 709         case RT5682_EQ_AUTO_RCV_CTRL8:
 710         case RT5682_EQ_AUTO_RCV_CTRL9:
 711         case RT5682_EQ_AUTO_RCV_CTRL10:
 712         case RT5682_EQ_AUTO_RCV_CTRL11:
 713         case RT5682_EQ_AUTO_RCV_CTRL12:
 714         case RT5682_EQ_AUTO_RCV_CTRL13:
 715         case RT5682_ADC_L_EQ_LPF1_A1:
 716         case RT5682_R_EQ_LPF1_A1:
 717         case RT5682_L_EQ_LPF1_H0:
 718         case RT5682_R_EQ_LPF1_H0:
 719         case RT5682_L_EQ_BPF1_A1:
 720         case RT5682_R_EQ_BPF1_A1:
 721         case RT5682_L_EQ_BPF1_A2:
 722         case RT5682_R_EQ_BPF1_A2:
 723         case RT5682_L_EQ_BPF1_H0:
 724         case RT5682_R_EQ_BPF1_H0:
 725         case RT5682_L_EQ_BPF2_A1:
 726         case RT5682_R_EQ_BPF2_A1:
 727         case RT5682_L_EQ_BPF2_A2:
 728         case RT5682_R_EQ_BPF2_A2:
 729         case RT5682_L_EQ_BPF2_H0:
 730         case RT5682_R_EQ_BPF2_H0:
 731         case RT5682_L_EQ_BPF3_A1:
 732         case RT5682_R_EQ_BPF3_A1:
 733         case RT5682_L_EQ_BPF3_A2:
 734         case RT5682_R_EQ_BPF3_A2:
 735         case RT5682_L_EQ_BPF3_H0:
 736         case RT5682_R_EQ_BPF3_H0:
 737         case RT5682_L_EQ_BPF4_A1:
 738         case RT5682_R_EQ_BPF4_A1:
 739         case RT5682_L_EQ_BPF4_A2:
 740         case RT5682_R_EQ_BPF4_A2:
 741         case RT5682_L_EQ_BPF4_H0:
 742         case RT5682_R_EQ_BPF4_H0:
 743         case RT5682_L_EQ_HPF1_A1:
 744         case RT5682_R_EQ_HPF1_A1:
 745         case RT5682_L_EQ_HPF1_H0:
 746         case RT5682_R_EQ_HPF1_H0:
 747         case RT5682_L_EQ_PRE_VOL:
 748         case RT5682_R_EQ_PRE_VOL:
 749         case RT5682_L_EQ_POST_VOL:
 750         case RT5682_R_EQ_POST_VOL:
 751         case RT5682_I2C_MODE:
 752                 return true;
 753         default:
 754                 return false;
 755         }
 756 }
 757
 758 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 759 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 760 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 761
 762 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 763 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 764         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 765         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 766         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 767         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 768         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 769         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 770         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 771 );
 772
 773 /* Interface data select */
 774 static const char * const rt5682_data_select[] = {
 775         "L/R", "R/L", "L/L", "R/R"
 776 };
 777
 778 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
 779         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
 780
 781 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
 782         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
 783
 784 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
 785         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
 786
 787 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
 788         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
 789
 790 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
 791         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
 792
 793 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
 794         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
 795
 796 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
 797         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
 798
 799 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
 800         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
 801
 802 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
 803         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
 804
 805 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
 806         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
 807
 808 static void rt5682_reset(struct regmap *regmap)
 809 {
 810         regmap_write(regmap, RT5682_RESET, 0);
 811         regmap_write(regmap, RT5682_I2C_MODE, 1);
 812 }
 813 /**
 814  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
 815  * @component: SoC audio component device.
 816  * @filter_mask: mask of filters.
 817  * @clk_src: clock source
 818  *
 819  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
 820  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 821  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 822  * ASRC function will track i2s clock and generate a corresponding system clock
 823  * for codec. This function provides an API to select the clock source for a
 824  * set of filters specified by the mask. And the component driver will turn on
 825  * ASRC for these filters if ASRC is selected as their clock source.
 826  */
 827 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
 828                 unsigned int filter_mask, unsigned int clk_src)
 829 {
 830
 831         switch (clk_src) {
 832         case RT5682_CLK_SEL_SYS:
 833         case RT5682_CLK_SEL_I2S1_ASRC:
 834         case RT5682_CLK_SEL_I2S2_ASRC:
 835                 break;
 836
 837         default:
 838                 return -EINVAL;
 839         }
 840
 841         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
 842                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
 843                         RT5682_FILTER_CLK_SEL_MASK,
 844                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 845         }
 846
 847         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
 848                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
 849                         RT5682_FILTER_CLK_SEL_MASK,
 850                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 851         }
 852
 853         return 0;
 854 }
 855 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
 856
 857 static int rt5682_button_detect(struct snd_soc_component *component)
 858 {
 859         int btn_type, val;
 860
 861         val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
 862         btn_type = val & 0xfff0;
 863         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
 864         pr_debug("%s btn_type=%x\n", __func__, btn_type);
 865         snd_soc_component_update_bits(component,
 866                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
 867
 868         return btn_type;
 869 }
 870
 871 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
 872                 bool enable)
 873 {
 874         if (enable) {
 875                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 876                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
 877                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 878                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
 879                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
 880                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 881                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
 882                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
 883                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 884                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
 885         } else {
 886                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 887                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
 888                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 889                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
 890                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 891                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
 892                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 893                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
 894                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 895                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
 896         }
 897 }
 898
 899 /**
 900  * rt5682_headset_detect - Detect headset.
 901  * @component: SoC audio component device.
 902  * @jack_insert: Jack insert or not.
 903  *
 904  * Detect whether is headset or not when jack inserted.
 905  *
 906  * Returns detect status.
 907  */
 908 static int rt5682_headset_detect(struct snd_soc_component *component,
 909                 int jack_insert)
 910 {
 911         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 912         unsigned int val, count;
 913
 914         if (jack_insert) {
 915
 916                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 917                         RT5682_PWR_VREF2 | RT5682_PWR_MB,
 918                         RT5682_PWR_VREF2 | RT5682_PWR_MB);
 919                 snd_soc_component_update_bits(component,
 920                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
 921                 usleep_range(15000, 20000);
 922                 snd_soc_component_update_bits(component,
 923                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
 924                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 925                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
 926
 927                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 928                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
 929
 930                 count = 0;
 931                 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
 932                         & RT5682_JACK_TYPE_MASK;
 933                 while (val == 0 && count < 50) {
 934                         usleep_range(10000, 15000);
 935                         val = snd_soc_component_read32(component,
 936                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
 937                         count++;
 938                 }
 939
 940                 switch (val) {
 941                 case 0x1:
 942                 case 0x2:
 943                         rt5682->jack_type = SND_JACK_HEADSET;
 944                         rt5682_enable_push_button_irq(component, true);
 945                         break;
 946                 default:
 947                         rt5682->jack_type = SND_JACK_HEADPHONE;
 948                 }
 949
 950         } else {
 951                 rt5682_enable_push_button_irq(component, false);
 952                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 953                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 954                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 955                         RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
 956                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 957                         RT5682_PWR_CBJ, 0);
 958
 959                 rt5682->jack_type = 0;
 960         }
 961
 962         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
 963         return rt5682->jack_type;
 964 }
 965
 966 static irqreturn_t rt5682_irq(int irq, void *data)
 967 {
 968         struct rt5682_priv *rt5682 = data;
 969
 970         mod_delayed_work(system_power_efficient_wq,
 971                         &rt5682->jack_detect_work, msecs_to_jiffies(250));
 972
 973         return IRQ_HANDLED;
 974 }
 975
 976 static void rt5682_jd_check_handler(struct work_struct *work)
 977 {
 978         struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
 979                 jd_check_work.work);
 980
 981         if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
 982                 & RT5682_JDH_RS_MASK) {
 983                 /* jack out */
 984                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
 985
 986                 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
 987                                 SND_JACK_HEADSET |
 988                                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
 989                                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
 990         } else {
 991                 schedule_delayed_work(&rt5682->jd_check_work, 500);
 992         }
 993 }
 994
 995 static int rt5682_set_jack_detect(struct snd_soc_component *component,
 996         struct snd_soc_jack *hs_jack, void *data)
 997 {
 998         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 999
1000         rt5682->hs_jack = hs_jack;
1001
1002         if (!hs_jack) {
1003                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1004                                    RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1005                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1006                                    RT5682_POW_JDH | RT5682_POW_JDL, 0);
1007                 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1008                 return 0;
1009         }
1010
1011         switch (rt5682->pdata.jd_src) {
1012         case RT5682_JD1:
1013                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
1014                         RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
1015                 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
1016                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
1017                         RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
1018                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
1019                         RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
1020                 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1021                         RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1022                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1023                                 RT5682_POW_IRQ | RT5682_POW_JDH |
1024                                 RT5682_POW_ANA, RT5682_POW_IRQ |
1025                                 RT5682_POW_JDH | RT5682_POW_ANA);
1026                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1027                         RT5682_PWR_JDH | RT5682_PWR_JDL,
1028                         RT5682_PWR_JDH | RT5682_PWR_JDL);
1029                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1030                         RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1031                         RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1032                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1033                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1034                         rt5682->pdata.btndet_delay));
1035                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1036                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1037                         rt5682->pdata.btndet_delay));
1038                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1039                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1040                         rt5682->pdata.btndet_delay));
1041                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1042                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1043                         rt5682->pdata.btndet_delay));
1044                 mod_delayed_work(system_power_efficient_wq,
1045                            &rt5682->jack_detect_work, msecs_to_jiffies(250));
1046                 break;
1047
1048         case RT5682_JD_NULL:
1049                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1050                         RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1051                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1052                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1053                 break;
1054
1055         default:
1056                 dev_warn(component->dev, "Wrong JD source\n");
1057                 break;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static void rt5682_jack_detect_handler(struct work_struct *work)
1064 {
1065         struct rt5682_priv *rt5682 =
1066                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1067         int val, btn_type;
1068
1069         while (!rt5682->component)
1070                 usleep_range(10000, 15000);
1071
1072         while (!rt5682->component->card->instantiated)
1073                 usleep_range(10000, 15000);
1074
1075         mutex_lock(&rt5682->calibrate_mutex);
1076
1077         val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1078                 & RT5682_JDH_RS_MASK;
1079         if (!val) {
1080                 /* jack in */
1081                 if (rt5682->jack_type == 0) {
1082                         /* jack was out, report jack type */
1083                         rt5682->jack_type =
1084                                 rt5682_headset_detect(rt5682->component, 1);
1085                 } else {
1086                         /* jack is already in, report button event */
1087                         rt5682->jack_type = SND_JACK_HEADSET;
1088                         btn_type = rt5682_button_detect(rt5682->component);
1089                         /**
1090                          * rt5682 can report three kinds of button behavior,
1091                          * one click, double click and hold. However,
1092                          * currently we will report button pressed/released
1093                          * event. So all the three button behaviors are
1094                          * treated as button pressed.
1095                          */
1096                         switch (btn_type) {
1097                         case 0x8000:
1098                         case 0x4000:
1099                         case 0x2000:
1100                                 rt5682->jack_type |= SND_JACK_BTN_0;
1101                                 break;
1102                         case 0x1000:
1103                         case 0x0800:
1104                         case 0x0400:
1105                                 rt5682->jack_type |= SND_JACK_BTN_1;
1106                                 break;
1107                         case 0x0200:
1108                         case 0x0100:
1109                         case 0x0080:
1110                                 rt5682->jack_type |= SND_JACK_BTN_2;
1111                                 break;
1112                         case 0x0040:
1113                         case 0x0020:
1114                         case 0x0010:
1115                                 rt5682->jack_type |= SND_JACK_BTN_3;
1116                                 break;
1117                         case 0x0000: /* unpressed */
1118                                 break;
1119                         default:
1120                                 btn_type = 0;
1121                                 dev_err(rt5682->component->dev,
1122                                         "Unexpected button code 0x%04x\n",
1123                                         btn_type);
1124                                 break;
1125                         }
1126                 }
1127         } else {
1128                 /* jack out */
1129                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1130         }
1131
1132         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1133                         SND_JACK_HEADSET |
1134                             SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1135                             SND_JACK_BTN_2 | SND_JACK_BTN_3);
1136
1137         if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1138                 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1139                 schedule_delayed_work(&rt5682->jd_check_work, 0);
1140         else
1141                 cancel_delayed_work_sync(&rt5682->jd_check_work);
1142
1143         mutex_unlock(&rt5682->calibrate_mutex);
1144 }
1145
1146 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1147         /* DAC Digital Volume */
1148         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1149                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1150
1151         /* IN Boost Volume */
1152         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1153                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1154
1155         /* ADC Digital Volume Control */
1156         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1157                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1158         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1159                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1160
1161         /* ADC Boost Volume Control */
1162         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1163                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1164                 3, 0, adc_bst_tlv),
1165 };
1166
1167
1168 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1169                           int target, const int div[], int size)
1170 {
1171         int i;
1172
1173         if (rt5682->sysclk < target) {
1174                 pr_err("sysclk rate %d is too low\n",
1175                         rt5682->sysclk);
1176                 return 0;
1177         }
1178
1179         for (i = 0; i < size - 1; i++) {
1180                 pr_info("div[%d]=%d\n", i, div[i]);
1181                 if (target * div[i] == rt5682->sysclk)
1182                         return i;
1183                 if (target * div[i + 1] > rt5682->sysclk) {
1184                         pr_err("can't find div for sysclk %d\n",
1185                                 rt5682->sysclk);
1186                         return i;
1187                 }
1188         }
1189
1190         if (target * div[i] < rt5682->sysclk)
1191                 pr_err("sysclk rate %d is too high\n",
1192                         rt5682->sysclk);
1193
1194         return size - 1;
1195
1196 }
1197
1198 /**
1199  * set_dmic_clk - Set parameter of dmic.
1200  *
1201  * @w: DAPM widget.
1202  * @kcontrol: The kcontrol of this widget.
1203  * @event: Event id.
1204  *
1205  * Choose dmic clock between 1MHz and 3MHz.
1206  * It is better for clock to approximate 3MHz.
1207  */
1208 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1209         struct snd_kcontrol *kcontrol, int event)
1210 {
1211         struct snd_soc_component *component =
1212                 snd_soc_dapm_to_component(w->dapm);
1213         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1214         int idx = -EINVAL;
1215         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1216
1217         idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1218
1219         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1220                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1221
1222         return 0;
1223 }
1224
1225 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1226         struct snd_kcontrol *kcontrol, int event)
1227 {
1228         struct snd_soc_component *component =
1229                 snd_soc_dapm_to_component(w->dapm);
1230         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1231         int ref, val, reg, idx = -EINVAL;
1232         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1233         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1234
1235         val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1236                 RT5682_GP4_PIN_MASK;
1237         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1238                 val == RT5682_GP4_PIN_ADCDAT2)
1239                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1240         else
1241                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1242
1243         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1244
1245         if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1246                 reg = RT5682_PLL_TRACK_3;
1247         else
1248                 reg = RT5682_PLL_TRACK_2;
1249
1250         snd_soc_component_update_bits(component, reg,
1251                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1252
1253         /* select over sample rate */
1254         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1255                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1256                         break;
1257         }
1258
1259         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1260                 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1261                 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1262
1263         return 0;
1264 }
1265
1266 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1267                          struct snd_soc_dapm_widget *sink)
1268 {
1269         unsigned int val;
1270         struct snd_soc_component *component =
1271                 snd_soc_dapm_to_component(w->dapm);
1272
1273         val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1274         val &= RT5682_SCLK_SRC_MASK;
1275         if (val == RT5682_SCLK_SRC_PLL1)
1276                 return 1;
1277         else
1278                 return 0;
1279 }
1280
1281 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1282                          struct snd_soc_dapm_widget *sink)
1283 {
1284         unsigned int reg, shift, val;
1285         struct snd_soc_component *component =
1286                 snd_soc_dapm_to_component(w->dapm);
1287
1288         switch (w->shift) {
1289         case RT5682_ADC_STO1_ASRC_SFT:
1290                 reg = RT5682_PLL_TRACK_3;
1291                 shift = RT5682_FILTER_CLK_SEL_SFT;
1292                 break;
1293         case RT5682_DAC_STO1_ASRC_SFT:
1294                 reg = RT5682_PLL_TRACK_2;
1295                 shift = RT5682_FILTER_CLK_SEL_SFT;
1296                 break;
1297         default:
1298                 return 0;
1299         }
1300
1301         val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1302         switch (val) {
1303         case RT5682_CLK_SEL_I2S1_ASRC:
1304         case RT5682_CLK_SEL_I2S2_ASRC:
1305                 return 1;
1306         default:
1307                 return 0;
1308         }
1309
1310 }
1311
1312 /* Digital Mixer */
1313 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1314         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1315                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1316         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1317                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1318 };
1319
1320 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1321         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1322                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1323         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1324                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1325 };
1326
1327 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1328         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1329                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1330         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1331                         RT5682_M_DAC1_L_SFT, 1, 1),
1332 };
1333
1334 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1335         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1336                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1337         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1338                         RT5682_M_DAC1_R_SFT, 1, 1),
1339 };
1340
1341 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1342         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1343                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1344         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1345                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1346 };
1347
1348 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1349         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1350                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1351         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1352                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1353 };
1354
1355 /* Analog Input Mixer */
1356 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1357         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1358                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1359 };
1360
1361 /* STO1 ADC1 Source */
1362 /* MX-26 [13] [5] */
1363 static const char * const rt5682_sto1_adc1_src[] = {
1364         "DAC MIX", "ADC"
1365 };
1366
1367 static SOC_ENUM_SINGLE_DECL(
1368         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1369         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1370
1371 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1372         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1373
1374 static SOC_ENUM_SINGLE_DECL(
1375         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1376         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1377
1378 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1379         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1380
1381 /* STO1 ADC Source */
1382 /* MX-26 [11:10] [3:2] */
1383 static const char * const rt5682_sto1_adc_src[] = {
1384         "ADC1 L", "ADC1 R"
1385 };
1386
1387 static SOC_ENUM_SINGLE_DECL(
1388         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1389         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1390
1391 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1392         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1393
1394 static SOC_ENUM_SINGLE_DECL(
1395         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1396         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1397
1398 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1399         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1400
1401 /* STO1 ADC2 Source */
1402 /* MX-26 [12] [4] */
1403 static const char * const rt5682_sto1_adc2_src[] = {
1404         "DAC MIX", "DMIC"
1405 };
1406
1407 static SOC_ENUM_SINGLE_DECL(
1408         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1409         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1410
1411 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1412         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1413
1414 static SOC_ENUM_SINGLE_DECL(
1415         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1416         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1417
1418 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1419         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1420
1421 /* MX-79 [6:4] I2S1 ADC data location */
1422 static const unsigned int rt5682_if1_adc_slot_values[] = {
1423         0,
1424         2,
1425         4,
1426         6,
1427 };
1428
1429 static const char * const rt5682_if1_adc_slot_src[] = {
1430         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1431 };
1432
1433 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1434         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1435         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1436
1437 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1438         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1439
1440 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1441 /* MX-2B [4], MX-2B [0]*/
1442 static const char * const rt5682_alg_dac1_src[] = {
1443         "Stereo1 DAC Mixer", "DAC1"
1444 };
1445
1446 static SOC_ENUM_SINGLE_DECL(
1447         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1448         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1449
1450 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1451         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1452
1453 static SOC_ENUM_SINGLE_DECL(
1454         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1455         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1456
1457 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1458         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1459
1460 /* Out Switch */
1461 static const struct snd_kcontrol_new hpol_switch =
1462         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1463                                         RT5682_L_MUTE_SFT, 1, 1);
1464 static const struct snd_kcontrol_new hpor_switch =
1465         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1466                                         RT5682_R_MUTE_SFT, 1, 1);
1467
1468 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1469         struct snd_kcontrol *kcontrol, int event)
1470 {
1471         struct snd_soc_component *component =
1472                 snd_soc_dapm_to_component(w->dapm);
1473
1474         switch (event) {
1475         case SND_SOC_DAPM_PRE_PMU:
1476                 snd_soc_component_write(component,
1477                         RT5682_HP_LOGIC_CTRL_2, 0x0012);
1478                 snd_soc_component_write(component,
1479                         RT5682_HP_CTRL_2, 0x6000);
1480                 snd_soc_component_update_bits(component,
1481                         RT5682_DEPOP_1, 0x60, 0x60);
1482                 snd_soc_component_update_bits(component,
1483                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1484                 break;
1485
1486         case SND_SOC_DAPM_POST_PMD:
1487                 snd_soc_component_update_bits(component,
1488                         RT5682_DEPOP_1, 0x60, 0x0);
1489                 snd_soc_component_write(component,
1490                         RT5682_HP_CTRL_2, 0x0000);
1491                 snd_soc_component_update_bits(component,
1492                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1493                 break;
1494
1495         default:
1496                 return 0;
1497         }
1498
1499         return 0;
1500
1501 }
1502
1503 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1504         struct snd_kcontrol *kcontrol, int event)
1505 {
1506         switch (event) {
1507         case SND_SOC_DAPM_POST_PMU:
1508                 /*Add delay to avoid pop noise*/
1509                 msleep(150);
1510                 break;
1511
1512         default:
1513                 return 0;
1514         }
1515
1516         return 0;
1517 }
1518
1519 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1520         struct snd_kcontrol *kcontrol, int event)
1521 {
1522         struct snd_soc_component *component =
1523                 snd_soc_dapm_to_component(w->dapm);
1524
1525         switch (event) {
1526         case SND_SOC_DAPM_PRE_PMU:
1527                 switch (w->shift) {
1528                 case RT5682_PWR_VREF1_BIT:
1529                         snd_soc_component_update_bits(component,
1530                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1531                         break;
1532
1533                 case RT5682_PWR_VREF2_BIT:
1534                         snd_soc_component_update_bits(component,
1535                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1536                         break;
1537
1538                 default:
1539                         break;
1540                 }
1541                 break;
1542
1543         case SND_SOC_DAPM_POST_PMU:
1544                 usleep_range(15000, 20000);
1545                 switch (w->shift) {
1546                 case RT5682_PWR_VREF1_BIT:
1547                         snd_soc_component_update_bits(component,
1548                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1549                                 RT5682_PWR_FV1);
1550                         break;
1551
1552                 case RT5682_PWR_VREF2_BIT:
1553                         snd_soc_component_update_bits(component,
1554                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1555                                 RT5682_PWR_FV2);
1556                         break;
1557
1558                 default:
1559                         break;
1560                 }
1561                 break;
1562
1563         default:
1564                 return 0;
1565         }
1566
1567         return 0;
1568 }
1569
1570 static const unsigned int rt5682_adcdat_pin_values[] = {
1571         1,
1572         3,
1573 };
1574
1575 static const char * const rt5682_adcdat_pin_select[] = {
1576         "ADCDAT1",
1577         "ADCDAT2",
1578 };
1579
1580 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1581         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1582         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1583
1584 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1585         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1586
1587 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1588         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1589                 0, NULL, 0),
1590         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1591                 0, NULL, 0),
1592         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1593                 0, NULL, 0),
1594         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1595                 0, NULL, 0),
1596         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1597                 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1598
1599         /* ASRC */
1600         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1601                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1602         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1603                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1604         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1605                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1606         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1607                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1608         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1609                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1610
1611         /* Input Side */
1612         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1613                 0, NULL, 0),
1614         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1615                 0, NULL, 0),
1616
1617         /* Input Lines */
1618         SND_SOC_DAPM_INPUT("DMIC L1"),
1619         SND_SOC_DAPM_INPUT("DMIC R1"),
1620
1621         SND_SOC_DAPM_INPUT("IN1P"),
1622
1623         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1624                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1625         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1626                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1627
1628         /* Boost */
1629         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1630                 0, 0, NULL, 0),
1631
1632         /* REC Mixer */
1633         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1634                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1635         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1636                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1637
1638         /* ADCs */
1639         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1640         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1641
1642         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1643                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1644         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1645                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1646         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1647                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1648
1649         /* ADC Mux */
1650         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1651                 &rt5682_sto1_adc1l_mux),
1652         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1653                 &rt5682_sto1_adc1r_mux),
1654         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1655                 &rt5682_sto1_adc2l_mux),
1656         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1657                 &rt5682_sto1_adc2r_mux),
1658         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1659                 &rt5682_sto1_adcl_mux),
1660         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1661                 &rt5682_sto1_adcr_mux),
1662         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1663                 &rt5682_if1_adc_slot_mux),
1664
1665         /* ADC Mixer */
1666         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1667                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1668                 SND_SOC_DAPM_PRE_PMU),
1669         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1670                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1671                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1672         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1673                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1674                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1675         SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1676                 14, 1, NULL, 0),
1677
1678         /* ADC PGA */
1679         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1680
1681         /* Digital Interface */
1682         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1683                 0, NULL, 0),
1684         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1685                 0, NULL, 0),
1686         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1687         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1688         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1689
1690         /* Digital Interface Select */
1691         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1692                         &rt5682_if1_01_adc_swap_mux),
1693         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1694                         &rt5682_if1_23_adc_swap_mux),
1695         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1696                         &rt5682_if1_45_adc_swap_mux),
1697         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1698                         &rt5682_if1_67_adc_swap_mux),
1699         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1700                         &rt5682_if2_adc_swap_mux),
1701
1702         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1703                         &rt5682_adcdat_pin_ctrl),
1704
1705         /* Audio Interface */
1706         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1707                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1708         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1709                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1710         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1711
1712         /* Output Side */
1713         /* DAC mixer before sound effect  */
1714         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1715                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1716         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1717                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1718
1719         /* DAC channel Mux */
1720         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1721                 &rt5682_alg_dac_l1_mux),
1722         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1723                 &rt5682_alg_dac_r1_mux),
1724
1725         /* DAC Mixer */
1726         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1727                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1728                 SND_SOC_DAPM_PRE_PMU),
1729         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1730                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1731         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1732                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1733
1734         /* DACs */
1735         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1736                 RT5682_PWR_DAC_L1_BIT, 0),
1737         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1738                 RT5682_PWR_DAC_R1_BIT, 0),
1739         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1740                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1741
1742         /* HPO */
1743         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1744                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1745
1746         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1747                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1748         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1749                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1750         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1751                 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1752         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1753                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1754
1755         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1756                 &hpol_switch),
1757         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1758                 &hpor_switch),
1759
1760         /* CLK DET */
1761         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1762                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1763         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1764                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1765         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1766                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1767         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1768                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1769
1770         /* Output Lines */
1771         SND_SOC_DAPM_OUTPUT("HPOL"),
1772         SND_SOC_DAPM_OUTPUT("HPOR"),
1773
1774 };
1775
1776 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1777         /*PLL*/
1778         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1779         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1780
1781         /*ASRC*/
1782         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1783         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1784         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1785         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1786         {"ADC STO1 ASRC", NULL, "CLKDET"},
1787         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1788         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1789         {"DAC STO1 ASRC", NULL, "CLKDET"},
1790
1791         /*Vref*/
1792         {"MICBIAS1", NULL, "Vref1"},
1793         {"MICBIAS2", NULL, "Vref1"},
1794
1795         {"CLKDET SYS", NULL, "CLKDET"},
1796
1797         {"IN1P", NULL, "LDO2"},
1798
1799         {"BST1 CBJ", NULL, "IN1P"},
1800
1801         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1802         {"RECMIX1L", NULL, "RECMIX1L Power"},
1803
1804         {"ADC1 L", NULL, "RECMIX1L"},
1805         {"ADC1 L", NULL, "ADC1 L Power"},
1806         {"ADC1 L", NULL, "ADC1 clock"},
1807
1808         {"DMIC L1", NULL, "DMIC CLK"},
1809         {"DMIC L1", NULL, "DMIC1 Power"},
1810         {"DMIC R1", NULL, "DMIC CLK"},
1811         {"DMIC R1", NULL, "DMIC1 Power"},
1812         {"DMIC CLK", NULL, "DMIC ASRC"},
1813
1814         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1815         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1816         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1817         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1818
1819         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1820         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1821         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1822         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1823
1824         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1825         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1826         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1827         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1828
1829         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1830         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1831         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1832
1833         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1834         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1835         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1836
1837         {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1838
1839         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1840         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1841
1842         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1843         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1844         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1845         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1846         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1847         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1848         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1849         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1850         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1851         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1852         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1853         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1854         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1855         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1856         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1857         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1858
1859         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1860         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1861         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1862         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1863         {"IF1_ADC Mux", NULL, "I2S1"},
1864         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1865         {"AIF1TX", NULL, "ADCDAT Mux"},
1866         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1867         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1868         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1869         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1870         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1871         {"AIF2TX", NULL, "ADCDAT Mux"},
1872
1873         {"IF1 DAC1 L", NULL, "AIF1RX"},
1874         {"IF1 DAC1 L", NULL, "I2S1"},
1875         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1876         {"IF1 DAC1 R", NULL, "AIF1RX"},
1877         {"IF1 DAC1 R", NULL, "I2S1"},
1878         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1879
1880         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1881         {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1882         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1883         {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1884
1885         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1886         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1887
1888         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1889         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1890
1891         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1892         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1893         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1894         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1895
1896         {"DAC L1", NULL, "DAC L1 Source"},
1897         {"DAC R1", NULL, "DAC R1 Source"},
1898
1899         {"DAC L1", NULL, "DAC 1 Clock"},
1900         {"DAC R1", NULL, "DAC 1 Clock"},
1901
1902         {"HP Amp", NULL, "DAC L1"},
1903         {"HP Amp", NULL, "DAC R1"},
1904         {"HP Amp", NULL, "HP Amp L"},
1905         {"HP Amp", NULL, "HP Amp R"},
1906         {"HP Amp", NULL, "Capless"},
1907         {"HP Amp", NULL, "Charge Pump"},
1908         {"HP Amp", NULL, "CLKDET SYS"},
1909         {"HP Amp", NULL, "Vref1"},
1910         {"HPOL Playback", "Switch", "HP Amp"},
1911         {"HPOR Playback", "Switch", "HP Amp"},
1912         {"HPOL", NULL, "HPOL Playback"},
1913         {"HPOR", NULL, "HPOR Playback"},
1914 };
1915
1916 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1917                         unsigned int rx_mask, int slots, int slot_width)
1918 {
1919         struct snd_soc_component *component = dai->component;
1920         unsigned int cl, val = 0;
1921
1922         if (tx_mask || rx_mask)
1923                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1924                         RT5682_TDM_EN, RT5682_TDM_EN);
1925         else
1926                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1927                         RT5682_TDM_EN, 0);
1928
1929         switch (slots) {
1930         case 4:
1931                 val |= RT5682_TDM_TX_CH_4;
1932                 val |= RT5682_TDM_RX_CH_4;
1933                 break;
1934         case 6:
1935                 val |= RT5682_TDM_TX_CH_6;
1936                 val |= RT5682_TDM_RX_CH_6;
1937                 break;
1938         case 8:
1939                 val |= RT5682_TDM_TX_CH_8;
1940                 val |= RT5682_TDM_RX_CH_8;
1941                 break;
1942         case 2:
1943                 break;
1944         default:
1945                 return -EINVAL;
1946         }
1947
1948         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1949                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1950
1951         switch (slot_width) {
1952         case 8:
1953                 if (tx_mask || rx_mask)
1954                         return -EINVAL;
1955                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1956                 break;
1957         case 16:
1958                 val = RT5682_TDM_CL_16;
1959                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1960                 break;
1961         case 20:
1962                 val = RT5682_TDM_CL_20;
1963                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1964                 break;
1965         case 24:
1966                 val = RT5682_TDM_CL_24;
1967                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1968                 break;
1969         case 32:
1970                 val = RT5682_TDM_CL_32;
1971                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1972                 break;
1973         default:
1974                 return -EINVAL;
1975         }
1976
1977         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1978                 RT5682_TDM_CL_MASK, val);
1979         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1980                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1981
1982         return 0;
1983 }
1984
1985
1986 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1987         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1988 {
1989         struct snd_soc_component *component = dai->component;
1990         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1991         unsigned int len_1 = 0, len_2 = 0;
1992         int pre_div, frame_size;
1993
1994         rt5682->lrck[dai->id] = params_rate(params);
1995         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
1996
1997         frame_size = snd_soc_params_to_frame_size(params);
1998         if (frame_size < 0) {
1999                 dev_err(component->dev, "Unsupported frame size: %d\n",
2000                         frame_size);
2001                 return -EINVAL;
2002         }
2003
2004         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2005                                 rt5682->lrck[dai->id], pre_div, dai->id);
2006
2007         switch (params_width(params)) {
2008         case 16:
2009                 break;
2010         case 20:
2011                 len_1 |= RT5682_I2S1_DL_20;
2012                 len_2 |= RT5682_I2S2_DL_20;
2013                 break;
2014         case 24:
2015                 len_1 |= RT5682_I2S1_DL_24;
2016                 len_2 |= RT5682_I2S2_DL_24;
2017                 break;
2018         case 32:
2019                 len_1 |= RT5682_I2S1_DL_32;
2020                 len_2 |= RT5682_I2S2_DL_24;
2021                 break;
2022         case 8:
2023                 len_1 |= RT5682_I2S2_DL_8;
2024                 len_2 |= RT5682_I2S2_DL_8;
2025                 break;
2026         default:
2027                 return -EINVAL;
2028         }
2029
2030         switch (dai->id) {
2031         case RT5682_AIF1:
2032                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2033                         RT5682_I2S1_DL_MASK, len_1);
2034                 if (rt5682->master[RT5682_AIF1]) {
2035                         snd_soc_component_update_bits(component,
2036                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2037                                 pre_div << RT5682_I2S_M_DIV_SFT);
2038                 }
2039                 if (params_channels(params) == 1) /* mono mode */
2040                         snd_soc_component_update_bits(component,
2041                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2042                                 RT5682_I2S1_MONO_EN);
2043                 else
2044                         snd_soc_component_update_bits(component,
2045                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2046                                 RT5682_I2S1_MONO_DIS);
2047                 break;
2048         case RT5682_AIF2:
2049                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2050                         RT5682_I2S2_DL_MASK, len_2);
2051                 if (rt5682->master[RT5682_AIF2]) {
2052                         snd_soc_component_update_bits(component,
2053                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2054                                 pre_div << RT5682_I2S2_M_PD_SFT);
2055                 }
2056                 if (params_channels(params) == 1) /* mono mode */
2057                         snd_soc_component_update_bits(component,
2058                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2059                                 RT5682_I2S2_MONO_EN);
2060                 else
2061                         snd_soc_component_update_bits(component,
2062                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2063                                 RT5682_I2S2_MONO_DIS);
2064                 break;
2065         default:
2066                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2067                 return -EINVAL;
2068         }
2069
2070         return 0;
2071 }
2072
2073 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2074 {
2075         struct snd_soc_component *component = dai->component;
2076         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2077         unsigned int reg_val = 0, tdm_ctrl = 0;
2078
2079         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2080         case SND_SOC_DAIFMT_CBM_CFM:
2081                 rt5682->master[dai->id] = 1;
2082                 break;
2083         case SND_SOC_DAIFMT_CBS_CFS:
2084                 rt5682->master[dai->id] = 0;
2085                 break;
2086         default:
2087                 return -EINVAL;
2088         }
2089
2090         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2091         case SND_SOC_DAIFMT_NB_NF:
2092                 break;
2093         case SND_SOC_DAIFMT_IB_NF:
2094                 reg_val |= RT5682_I2S_BP_INV;
2095                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2096                 break;
2097         case SND_SOC_DAIFMT_NB_IF:
2098                 if (dai->id == RT5682_AIF1)
2099                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2100                 else
2101                         return -EINVAL;
2102                 break;
2103         case SND_SOC_DAIFMT_IB_IF:
2104                 if (dai->id == RT5682_AIF1)
2105                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2106                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2107                 else
2108                         return -EINVAL;
2109                 break;
2110         default:
2111                 return -EINVAL;
2112         }
2113
2114         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2115         case SND_SOC_DAIFMT_I2S:
2116                 break;
2117         case SND_SOC_DAIFMT_LEFT_J:
2118                 reg_val |= RT5682_I2S_DF_LEFT;
2119                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2120                 break;
2121         case SND_SOC_DAIFMT_DSP_A:
2122                 reg_val |= RT5682_I2S_DF_PCM_A;
2123                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2124                 break;
2125         case SND_SOC_DAIFMT_DSP_B:
2126                 reg_val |= RT5682_I2S_DF_PCM_B;
2127                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2128                 break;
2129         default:
2130                 return -EINVAL;
2131         }
2132
2133         switch (dai->id) {
2134         case RT5682_AIF1:
2135                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2136                         RT5682_I2S_DF_MASK, reg_val);
2137                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2138                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2139                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2140                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2141                         tdm_ctrl | rt5682->master[dai->id]);
2142                 break;
2143         case RT5682_AIF2:
2144                 if (rt5682->master[dai->id] == 0)
2145                         reg_val |= RT5682_I2S2_MS_S;
2146                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2147                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2148                         RT5682_I2S_DF_MASK, reg_val);
2149                 break;
2150         default:
2151                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2152                 return -EINVAL;
2153         }
2154         return 0;
2155 }
2156
2157 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2158                 int clk_id, int source, unsigned int freq, int dir)
2159 {
2160         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2161         unsigned int reg_val = 0, src = 0;
2162
2163         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2164                 return 0;
2165
2166         switch (clk_id) {
2167         case RT5682_SCLK_S_MCLK:
2168                 reg_val |= RT5682_SCLK_SRC_MCLK;
2169                 src = RT5682_CLK_SRC_MCLK;
2170                 break;
2171         case RT5682_SCLK_S_PLL1:
2172                 reg_val |= RT5682_SCLK_SRC_PLL1;
2173                 src = RT5682_CLK_SRC_PLL1;
2174                 break;
2175         case RT5682_SCLK_S_PLL2:
2176                 reg_val |= RT5682_SCLK_SRC_PLL2;
2177                 src = RT5682_CLK_SRC_PLL2;
2178                 break;
2179         case RT5682_SCLK_S_RCCLK:
2180                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2181                 src = RT5682_CLK_SRC_RCCLK;
2182                 break;
2183         default:
2184                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2185                 return -EINVAL;
2186         }
2187         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2188                 RT5682_SCLK_SRC_MASK, reg_val);
2189
2190         if (rt5682->master[RT5682_AIF2]) {
2191                 snd_soc_component_update_bits(component,
2192                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2193                         src << RT5682_I2S2_SRC_SFT);
2194         }
2195
2196         rt5682->sysclk = freq;
2197         rt5682->sysclk_src = clk_id;
2198
2199         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2200                 freq, clk_id);
2201
2202         return 0;
2203 }
2204
2205 static int rt5682_set_component_pll(struct snd_soc_component *component,
2206                 int pll_id, int source, unsigned int freq_in,
2207                 unsigned int freq_out)
2208 {
2209         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2210         struct rl6231_pll_code pll_code;
2211         int ret;
2212
2213         if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2214             freq_out == rt5682->pll_out)
2215                 return 0;
2216
2217         if (!freq_in || !freq_out) {
2218                 dev_dbg(component->dev, "PLL disabled\n");
2219
2220                 rt5682->pll_in = 0;
2221                 rt5682->pll_out = 0;
2222                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2223                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2224                 return 0;
2225         }
2226
2227         switch (source) {
2228         case RT5682_PLL1_S_MCLK:
2229                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2230                         RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2231                 break;
2232         case RT5682_PLL1_S_BCLK1:
2233                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2234                                 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2235                 break;
2236         default:
2237                 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2238                 return -EINVAL;
2239         }
2240
2241         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2242         if (ret < 0) {
2243                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2244                 return ret;
2245         }
2246
2247         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2248                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2249                 pll_code.n_code, pll_code.k_code);
2250
2251         snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2252                 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2253         snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2254                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2255                 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2256
2257         rt5682->pll_in = freq_in;
2258         rt5682->pll_out = freq_out;
2259         rt5682->pll_src = source;
2260
2261         return 0;
2262 }
2263
2264 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2265 {
2266         struct snd_soc_component *component = dai->component;
2267         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2268
2269         rt5682->bclk[dai->id] = ratio;
2270
2271         switch (ratio) {
2272         case 64:
2273                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2274                         RT5682_I2S2_BCLK_MS2_MASK,
2275                         RT5682_I2S2_BCLK_MS2_64);
2276                 break;
2277         case 32:
2278                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2279                         RT5682_I2S2_BCLK_MS2_MASK,
2280                         RT5682_I2S2_BCLK_MS2_32);
2281                 break;
2282         default:
2283                 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2284                 return -EINVAL;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int rt5682_set_bias_level(struct snd_soc_component *component,
2291                         enum snd_soc_bias_level level)
2292 {
2293         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2294
2295         switch (level) {
2296         case SND_SOC_BIAS_PREPARE:
2297                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2298                         RT5682_PWR_BG, RT5682_PWR_BG);
2299                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2300                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2301                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2302                 break;
2303
2304         case SND_SOC_BIAS_STANDBY:
2305                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2306                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2307                 break;
2308         case SND_SOC_BIAS_OFF:
2309                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2310                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2311                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2312                         RT5682_PWR_BG, 0);
2313                 break;
2314
2315         default:
2316                 break;
2317         }
2318
2319         return 0;
2320 }
2321
2322 static int rt5682_probe(struct snd_soc_component *component)
2323 {
2324         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2325
2326         rt5682->component = component;
2327
2328         return 0;
2329 }
2330
2331 static void rt5682_remove(struct snd_soc_component *component)
2332 {
2333         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2334
2335         rt5682_reset(rt5682->regmap);
2336 }
2337
2338 #ifdef CONFIG_PM
2339 static int rt5682_suspend(struct snd_soc_component *component)
2340 {
2341         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2342
2343         regcache_cache_only(rt5682->regmap, true);
2344         regcache_mark_dirty(rt5682->regmap);
2345         return 0;
2346 }
2347
2348 static int rt5682_resume(struct snd_soc_component *component)
2349 {
2350         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2351
2352         regcache_cache_only(rt5682->regmap, false);
2353         regcache_sync(rt5682->regmap);
2354
2355         rt5682_irq(0, rt5682);
2356
2357         return 0;
2358 }
2359 #else
2360 #define rt5682_suspend NULL
2361 #define rt5682_resume NULL
2362 #endif
2363
2364 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2365 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2366                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2367
2368 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2369         .hw_params = rt5682_hw_params,
2370         .set_fmt = rt5682_set_dai_fmt,
2371         .set_tdm_slot = rt5682_set_tdm_slot,
2372 };
2373
2374 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2375         .hw_params = rt5682_hw_params,
2376         .set_fmt = rt5682_set_dai_fmt,
2377         .set_bclk_ratio = rt5682_set_bclk_ratio,
2378 };
2379
2380 static struct snd_soc_dai_driver rt5682_dai[] = {
2381         {
2382                 .name = "rt5682-aif1",
2383                 .id = RT5682_AIF1,
2384                 .playback = {
2385                         .stream_name = "AIF1 Playback",
2386                         .channels_min = 1,
2387                         .channels_max = 2,
2388                         .rates = RT5682_STEREO_RATES,
2389                         .formats = RT5682_FORMATS,
2390                 },
2391                 .capture = {
2392                         .stream_name = "AIF1 Capture",
2393                         .channels_min = 1,
2394                         .channels_max = 2,
2395                         .rates = RT5682_STEREO_RATES,
2396                         .formats = RT5682_FORMATS,
2397                 },
2398                 .ops = &rt5682_aif1_dai_ops,
2399         },
2400         {
2401                 .name = "rt5682-aif2",
2402                 .id = RT5682_AIF2,
2403                 .capture = {
2404                         .stream_name = "AIF2 Capture",
2405                         .channels_min = 1,
2406                         .channels_max = 2,
2407                         .rates = RT5682_STEREO_RATES,
2408                         .formats = RT5682_FORMATS,
2409                 },
2410                 .ops = &rt5682_aif2_dai_ops,
2411         },
2412 };
2413
2414 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2415         .probe = rt5682_probe,
2416         .remove = rt5682_remove,
2417         .suspend = rt5682_suspend,
2418         .resume = rt5682_resume,
2419         .set_bias_level = rt5682_set_bias_level,
2420         .controls = rt5682_snd_controls,
2421         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2422         .dapm_widgets = rt5682_dapm_widgets,
2423         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2424         .dapm_routes = rt5682_dapm_routes,
2425         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2426         .set_sysclk = rt5682_set_component_sysclk,
2427         .set_pll = rt5682_set_component_pll,
2428         .set_jack = rt5682_set_jack_detect,
2429         .use_pmdown_time        = 1,
2430         .endianness             = 1,
2431         .non_legacy_dai_naming  = 1,
2432 };
2433
2434 static const struct regmap_config rt5682_regmap = {
2435         .reg_bits = 16,
2436         .val_bits = 16,
2437         .max_register = RT5682_I2C_MODE,
2438         .volatile_reg = rt5682_volatile_register,
2439         .readable_reg = rt5682_readable_register,
2440         .cache_type = REGCACHE_RBTREE,
2441         .reg_defaults = rt5682_reg,
2442         .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2443         .use_single_read = true,
2444         .use_single_write = true,
2445 };
2446
2447 static const struct i2c_device_id rt5682_i2c_id[] = {
2448         {"rt5682", 0},
2449         {}
2450 };
2451 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2452
2453 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2454 {
2455
2456         device_property_read_u32(dev, "realtek,dmic1-data-pin",
2457                 &rt5682->pdata.dmic1_data_pin);
2458         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2459                 &rt5682->pdata.dmic1_clk_pin);
2460         device_property_read_u32(dev, "realtek,jd-src",
2461                 &rt5682->pdata.jd_src);
2462         device_property_read_u32(dev, "realtek,btndet-delay",
2463                 &rt5682->pdata.btndet_delay);
2464
2465         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2466                 "realtek,ldo1-en-gpios", 0);
2467
2468         return 0;
2469 }
2470
2471 static void rt5682_calibrate(struct rt5682_priv *rt5682)
2472 {
2473         int value, count;
2474
2475         mutex_lock(&rt5682->calibrate_mutex);
2476
2477         rt5682_reset(rt5682->regmap);
2478         regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
2479         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
2480         usleep_range(15000, 20000);
2481         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
2482         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2483         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2484         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2485         regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
2486         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2487         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
2488         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2489         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2490         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2491         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2492         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2493         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2494         regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2495         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2496
2497         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2498
2499         for (count = 0; count < 60; count++) {
2500                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2501                 if (!(value & 0x8000))
2502                         break;
2503
2504                 usleep_range(10000, 10005);
2505         }
2506
2507         if (count >= 60)
2508                 pr_err("HP Calibration Failure\n");
2509
2510         /* restore settings */
2511         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af);
2512         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
2513         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2514         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2515         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
2516         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
2517         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
2518
2519         mutex_unlock(&rt5682->calibrate_mutex);
2520
2521 }
2522
2523 static int rt5682_i2c_probe(struct i2c_client *i2c,
2524                     const struct i2c_device_id *id)
2525 {
2526         struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2527         struct rt5682_priv *rt5682;
2528         int i, ret;
2529         unsigned int val;
2530
2531         rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2532                 GFP_KERNEL);
2533
2534         if (rt5682 == NULL)
2535                 return -ENOMEM;
2536
2537         i2c_set_clientdata(i2c, rt5682);
2538
2539         rt5682->pdata = i2s_default_platform_data;
2540
2541         if (pdata)
2542                 rt5682->pdata = *pdata;
2543         else
2544                 rt5682_parse_dt(rt5682, &i2c->dev);
2545
2546         rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2547         if (IS_ERR(rt5682->regmap)) {
2548                 ret = PTR_ERR(rt5682->regmap);
2549                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2550                         ret);
2551                 return ret;
2552         }
2553
2554         for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2555                 rt5682->supplies[i].supply = rt5682_supply_names[i];
2556
2557         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2558                                       rt5682->supplies);
2559         if (ret != 0) {
2560                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2561                 return ret;
2562         }
2563
2564         ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2565                                     rt5682->supplies);
2566         if (ret != 0) {
2567                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2568                 return ret;
2569         }
2570
2571         if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2572                 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2573                                           GPIOF_OUT_INIT_HIGH, "rt5682"))
2574                         dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2575         }
2576
2577         /* Sleep for 300 ms miniumum */
2578         usleep_range(300000, 350000);
2579
2580         regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2581         usleep_range(10000, 15000);
2582
2583         regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2584         if (val != DEVICE_ID) {
2585                 pr_err("Device with ID register %x is not rt5682\n", val);
2586                 return -ENODEV;
2587         }
2588
2589         rt5682_reset(rt5682->regmap);
2590
2591         mutex_init(&rt5682->calibrate_mutex);
2592         rt5682_calibrate(rt5682);
2593
2594         ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
2595                                     ARRAY_SIZE(patch_list));
2596         if (ret != 0)
2597                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2598
2599         regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2600
2601         /* DMIC pin*/
2602         if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2603                 switch (rt5682->pdata.dmic1_data_pin) {
2604                 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2605                         regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2606                                 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2607                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2608                                 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2609                         break;
2610
2611                 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2612                         regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2613                                 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2614                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2615                                 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2616                         break;
2617
2618                 default:
2619                         dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2620                         break;
2621                 }
2622
2623                 switch (rt5682->pdata.dmic1_clk_pin) {
2624                 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2625                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2626                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2627                         break;
2628
2629                 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2630                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2631                                 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2632                         break;
2633
2634                 default:
2635                         dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2636                         break;
2637                 }
2638         }
2639
2640         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2641                         RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2642                         RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2643         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2644         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2645                         RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2646                         RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2647         regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2648         regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
2649                         RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
2650         regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
2651                         RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
2652         regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
2653                         RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
2654
2655         INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2656                                 rt5682_jack_detect_handler);
2657         INIT_DELAYED_WORK(&rt5682->jd_check_work,
2658                                 rt5682_jd_check_handler);
2659
2660
2661         if (i2c->irq) {
2662                 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2663                         rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2664                         | IRQF_ONESHOT, "rt5682", rt5682);
2665                 if (ret)
2666                         dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2667
2668         }
2669
2670         return devm_snd_soc_register_component(&i2c->dev,
2671                                         &soc_component_dev_rt5682,
2672                                         rt5682_dai, ARRAY_SIZE(rt5682_dai));
2673 }
2674
2675 static void rt5682_i2c_shutdown(struct i2c_client *client)
2676 {
2677         struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2678
2679         rt5682_reset(rt5682->regmap);
2680 }
2681
2682 #ifdef CONFIG_OF
2683 static const struct of_device_id rt5682_of_match[] = {
2684         {.compatible = "realtek,rt5682i"},
2685         {},
2686 };
2687 MODULE_DEVICE_TABLE(of, rt5682_of_match);
2688 #endif
2689
2690 #ifdef CONFIG_ACPI
2691 static const struct acpi_device_id rt5682_acpi_match[] = {
2692         {"10EC5682", 0,},
2693         {},
2694 };
2695 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2696 #endif
2697
2698 static struct i2c_driver rt5682_i2c_driver = {
2699         .driver = {
2700                 .name = "rt5682",
2701                 .of_match_table = of_match_ptr(rt5682_of_match),
2702                 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2703         },
2704         .probe = rt5682_i2c_probe,
2705         .shutdown = rt5682_i2c_shutdown,
2706         .id_table = rt5682_i2c_id,
2707 };
2708 module_i2c_driver(rt5682_i2c_driver);
2709
2710 MODULE_DESCRIPTION("ASoC RT5682 driver");
2711 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2712 MODULE_LICENSE("GPL v2");