sound/soc/codecs/rt5682.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // rt5682.c  --  RT5682 ALSA SoC audio component driver
   4 //
   5 // Copyright 2018 Realtek Semiconductor Corp.
   6 // Author: Bard Liao <bardliao@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/acpi.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/mutex.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/jack.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/rt5682.h>
  30
  31 #include "rl6231.h"
  32 #include "rt5682.h"
  33
  34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  35         "AVDD",
  36         "MICVDD",
  37         "VBAT",
  38 };
  39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
  40
  41 static const struct reg_sequence patch_list[] = {
  42         {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  43         {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  44         {RT5682_I2C_CTRL, 0x000f},
  45         {RT5682_PLL2_INTERNAL, 0x8266},
  46         {RT5682_SAR_IL_CMD_1, 0x22b7},
  47         {RT5682_SAR_IL_CMD_3, 0x0365},
  48         {RT5682_SAR_IL_CMD_6, 0x0110},
  49         {RT5682_CHARGE_PUMP_1, 0x0210},
  50         {RT5682_HP_LOGIC_CTRL_2, 0x0007},
  51         {RT5682_SAR_IL_CMD_2, 0xac00},
  52         {RT5682_CBJ_CTRL_7, 0x0104},
  53 };
  54
  55 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
  56 {
  57         int ret;
  58
  59         ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
  60                                      ARRAY_SIZE(patch_list));
  61         if (ret)
  62                 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  63 }
  64 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
  65
  66 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
  67         {0x0002, 0x8080},
  68         {0x0003, 0x8000},
  69         {0x0005, 0x0000},
  70         {0x0006, 0x0000},
  71         {0x0008, 0x800f},
  72         {0x000b, 0x0000},
  73         {0x0010, 0x4040},
  74         {0x0011, 0x0000},
  75         {0x0012, 0x1404},
  76         {0x0013, 0x1000},
  77         {0x0014, 0xa00a},
  78         {0x0015, 0x0404},
  79         {0x0016, 0x0404},
  80         {0x0019, 0xafaf},
  81         {0x001c, 0x2f2f},
  82         {0x001f, 0x0000},
  83         {0x0022, 0x5757},
  84         {0x0023, 0x0039},
  85         {0x0024, 0x000b},
  86         {0x0026, 0xc0c4},
  87         {0x0029, 0x8080},
  88         {0x002a, 0xa0a0},
  89         {0x002b, 0x0300},
  90         {0x0030, 0x0000},
  91         {0x003c, 0x0080},
  92         {0x0044, 0x0c0c},
  93         {0x0049, 0x0000},
  94         {0x0061, 0x0000},
  95         {0x0062, 0x0000},
  96         {0x0063, 0x003f},
  97         {0x0064, 0x0000},
  98         {0x0065, 0x0000},
  99         {0x0066, 0x0030},
 100         {0x0067, 0x0000},
 101         {0x006b, 0x0000},
 102         {0x006c, 0x0000},
 103         {0x006d, 0x2200},
 104         {0x006e, 0x0a10},
 105         {0x0070, 0x8000},
 106         {0x0071, 0x8000},
 107         {0x0073, 0x0000},
 108         {0x0074, 0x0000},
 109         {0x0075, 0x0002},
 110         {0x0076, 0x0001},
 111         {0x0079, 0x0000},
 112         {0x007a, 0x0000},
 113         {0x007b, 0x0000},
 114         {0x007c, 0x0100},
 115         {0x007e, 0x0000},
 116         {0x0080, 0x0000},
 117         {0x0081, 0x0000},
 118         {0x0082, 0x0000},
 119         {0x0083, 0x0000},
 120         {0x0084, 0x0000},
 121         {0x0085, 0x0000},
 122         {0x0086, 0x0005},
 123         {0x0087, 0x0000},
 124         {0x0088, 0x0000},
 125         {0x008c, 0x0003},
 126         {0x008d, 0x0000},
 127         {0x008e, 0x0060},
 128         {0x008f, 0x1000},
 129         {0x0091, 0x0c26},
 130         {0x0092, 0x0073},
 131         {0x0093, 0x0000},
 132         {0x0094, 0x0080},
 133         {0x0098, 0x0000},
 134         {0x009a, 0x0000},
 135         {0x009b, 0x0000},
 136         {0x009c, 0x0000},
 137         {0x009d, 0x0000},
 138         {0x009e, 0x100c},
 139         {0x009f, 0x0000},
 140         {0x00a0, 0x0000},
 141         {0x00a3, 0x0002},
 142         {0x00a4, 0x0001},
 143         {0x00ae, 0x2040},
 144         {0x00af, 0x0000},
 145         {0x00b6, 0x0000},
 146         {0x00b7, 0x0000},
 147         {0x00b8, 0x0000},
 148         {0x00b9, 0x0002},
 149         {0x00be, 0x0000},
 150         {0x00c0, 0x0160},
 151         {0x00c1, 0x82a0},
 152         {0x00c2, 0x0000},
 153         {0x00d0, 0x0000},
 154         {0x00d1, 0x2244},
 155         {0x00d2, 0x3300},
 156         {0x00d3, 0x2200},
 157         {0x00d4, 0x0000},
 158         {0x00d9, 0x0009},
 159         {0x00da, 0x0000},
 160         {0x00db, 0x0000},
 161         {0x00dc, 0x00c0},
 162         {0x00dd, 0x2220},
 163         {0x00de, 0x3131},
 164         {0x00df, 0x3131},
 165         {0x00e0, 0x3131},
 166         {0x00e2, 0x0000},
 167         {0x00e3, 0x4000},
 168         {0x00e4, 0x0aa0},
 169         {0x00e5, 0x3131},
 170         {0x00e6, 0x3131},
 171         {0x00e7, 0x3131},
 172         {0x00e8, 0x3131},
 173         {0x00ea, 0xb320},
 174         {0x00eb, 0x0000},
 175         {0x00f0, 0x0000},
 176         {0x00f1, 0x00d0},
 177         {0x00f2, 0x00d0},
 178         {0x00f6, 0x0000},
 179         {0x00fa, 0x0000},
 180         {0x00fb, 0x0000},
 181         {0x00fc, 0x0000},
 182         {0x00fd, 0x0000},
 183         {0x00fe, 0x10ec},
 184         {0x00ff, 0x6530},
 185         {0x0100, 0xa0a0},
 186         {0x010b, 0x0000},
 187         {0x010c, 0xae00},
 188         {0x010d, 0xaaa0},
 189         {0x010e, 0x8aa2},
 190         {0x010f, 0x02a2},
 191         {0x0110, 0xc000},
 192         {0x0111, 0x04a2},
 193         {0x0112, 0x2800},
 194         {0x0113, 0x0000},
 195         {0x0117, 0x0100},
 196         {0x0125, 0x0410},
 197         {0x0132, 0x6026},
 198         {0x0136, 0x5555},
 199         {0x0138, 0x3700},
 200         {0x013a, 0x2000},
 201         {0x013b, 0x2000},
 202         {0x013c, 0x2005},
 203         {0x013f, 0x0000},
 204         {0x0142, 0x0000},
 205         {0x0145, 0x0002},
 206         {0x0146, 0x0000},
 207         {0x0147, 0x0000},
 208         {0x0148, 0x0000},
 209         {0x0149, 0x0000},
 210         {0x0150, 0x79a1},
 211         {0x0156, 0xaaaa},
 212         {0x0160, 0x4ec0},
 213         {0x0161, 0x0080},
 214         {0x0162, 0x0200},
 215         {0x0163, 0x0800},
 216         {0x0164, 0x0000},
 217         {0x0165, 0x0000},
 218         {0x0166, 0x0000},
 219         {0x0167, 0x000f},
 220         {0x0168, 0x000f},
 221         {0x0169, 0x0021},
 222         {0x0190, 0x413d},
 223         {0x0194, 0x0000},
 224         {0x0195, 0x0000},
 225         {0x0197, 0x0022},
 226         {0x0198, 0x0000},
 227         {0x0199, 0x0000},
 228         {0x01af, 0x0000},
 229         {0x01b0, 0x0400},
 230         {0x01b1, 0x0000},
 231         {0x01b2, 0x0000},
 232         {0x01b3, 0x0000},
 233         {0x01b4, 0x0000},
 234         {0x01b5, 0x0000},
 235         {0x01b6, 0x01c3},
 236         {0x01b7, 0x02a0},
 237         {0x01b8, 0x03e9},
 238         {0x01b9, 0x1389},
 239         {0x01ba, 0xc351},
 240         {0x01bb, 0x0009},
 241         {0x01bc, 0x0018},
 242         {0x01bd, 0x002a},
 243         {0x01be, 0x004c},
 244         {0x01bf, 0x0097},
 245         {0x01c0, 0x433d},
 246         {0x01c2, 0x0000},
 247         {0x01c3, 0x0000},
 248         {0x01c4, 0x0000},
 249         {0x01c5, 0x0000},
 250         {0x01c6, 0x0000},
 251         {0x01c7, 0x0000},
 252         {0x01c8, 0x40af},
 253         {0x01c9, 0x0702},
 254         {0x01ca, 0x0000},
 255         {0x01cb, 0x0000},
 256         {0x01cc, 0x5757},
 257         {0x01cd, 0x5757},
 258         {0x01ce, 0x5757},
 259         {0x01cf, 0x5757},
 260         {0x01d0, 0x5757},
 261         {0x01d1, 0x5757},
 262         {0x01d2, 0x5757},
 263         {0x01d3, 0x5757},
 264         {0x01d4, 0x5757},
 265         {0x01d5, 0x5757},
 266         {0x01d6, 0x0000},
 267         {0x01d7, 0x0008},
 268         {0x01d8, 0x0029},
 269         {0x01d9, 0x3333},
 270         {0x01da, 0x0000},
 271         {0x01db, 0x0004},
 272         {0x01dc, 0x0000},
 273         {0x01de, 0x7c00},
 274         {0x01df, 0x0320},
 275         {0x01e0, 0x06a1},
 276         {0x01e1, 0x0000},
 277         {0x01e2, 0x0000},
 278         {0x01e3, 0x0000},
 279         {0x01e4, 0x0000},
 280         {0x01e6, 0x0001},
 281         {0x01e7, 0x0000},
 282         {0x01e8, 0x0000},
 283         {0x01ea, 0x0000},
 284         {0x01eb, 0x0000},
 285         {0x01ec, 0x0000},
 286         {0x01ed, 0x0000},
 287         {0x01ee, 0x0000},
 288         {0x01ef, 0x0000},
 289         {0x01f0, 0x0000},
 290         {0x01f1, 0x0000},
 291         {0x01f2, 0x0000},
 292         {0x01f3, 0x0000},
 293         {0x01f4, 0x0000},
 294         {0x0210, 0x6297},
 295         {0x0211, 0xa005},
 296         {0x0212, 0x824c},
 297         {0x0213, 0xf7ff},
 298         {0x0214, 0xf24c},
 299         {0x0215, 0x0102},
 300         {0x0216, 0x00a3},
 301         {0x0217, 0x0048},
 302         {0x0218, 0xa2c0},
 303         {0x0219, 0x0400},
 304         {0x021a, 0x00c8},
 305         {0x021b, 0x00c0},
 306         {0x021c, 0x0000},
 307         {0x0250, 0x4500},
 308         {0x0251, 0x40b3},
 309         {0x0252, 0x0000},
 310         {0x0253, 0x0000},
 311         {0x0254, 0x0000},
 312         {0x0255, 0x0000},
 313         {0x0256, 0x0000},
 314         {0x0257, 0x0000},
 315         {0x0258, 0x0000},
 316         {0x0259, 0x0000},
 317         {0x025a, 0x0005},
 318         {0x0270, 0x0000},
 319         {0x02ff, 0x0110},
 320         {0x0300, 0x001f},
 321         {0x0301, 0x032c},
 322         {0x0302, 0x5f21},
 323         {0x0303, 0x4000},
 324         {0x0304, 0x4000},
 325         {0x0305, 0x06d5},
 326         {0x0306, 0x8000},
 327         {0x0307, 0x0700},
 328         {0x0310, 0x4560},
 329         {0x0311, 0xa4a8},
 330         {0x0312, 0x7418},
 331         {0x0313, 0x0000},
 332         {0x0314, 0x0006},
 333         {0x0315, 0xffff},
 334         {0x0316, 0xc400},
 335         {0x0317, 0x0000},
 336         {0x03c0, 0x7e00},
 337         {0x03c1, 0x8000},
 338         {0x03c2, 0x8000},
 339         {0x03c3, 0x8000},
 340         {0x03c4, 0x8000},
 341         {0x03c5, 0x8000},
 342         {0x03c6, 0x8000},
 343         {0x03c7, 0x8000},
 344         {0x03c8, 0x8000},
 345         {0x03c9, 0x8000},
 346         {0x03ca, 0x8000},
 347         {0x03cb, 0x8000},
 348         {0x03cc, 0x8000},
 349         {0x03d0, 0x0000},
 350         {0x03d1, 0x0000},
 351         {0x03d2, 0x0000},
 352         {0x03d3, 0x0000},
 353         {0x03d4, 0x2000},
 354         {0x03d5, 0x2000},
 355         {0x03d6, 0x0000},
 356         {0x03d7, 0x0000},
 357         {0x03d8, 0x2000},
 358         {0x03d9, 0x2000},
 359         {0x03da, 0x2000},
 360         {0x03db, 0x2000},
 361         {0x03dc, 0x0000},
 362         {0x03dd, 0x0000},
 363         {0x03de, 0x0000},
 364         {0x03df, 0x2000},
 365         {0x03e0, 0x0000},
 366         {0x03e1, 0x0000},
 367         {0x03e2, 0x0000},
 368         {0x03e3, 0x0000},
 369         {0x03e4, 0x0000},
 370         {0x03e5, 0x0000},
 371         {0x03e6, 0x0000},
 372         {0x03e7, 0x0000},
 373         {0x03e8, 0x0000},
 374         {0x03e9, 0x0000},
 375         {0x03ea, 0x0000},
 376         {0x03eb, 0x0000},
 377         {0x03ec, 0x0000},
 378         {0x03ed, 0x0000},
 379         {0x03ee, 0x0000},
 380         {0x03ef, 0x0000},
 381         {0x03f0, 0x0800},
 382         {0x03f1, 0x0800},
 383         {0x03f2, 0x0800},
 384         {0x03f3, 0x0800},
 385 };
 386 EXPORT_SYMBOL_GPL(rt5682_reg);
 387
 388 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
 389 {
 390         switch (reg) {
 391         case RT5682_RESET:
 392         case RT5682_CBJ_CTRL_2:
 393         case RT5682_INT_ST_1:
 394         case RT5682_4BTN_IL_CMD_1:
 395         case RT5682_AJD1_CTRL:
 396         case RT5682_HP_CALIB_CTRL_1:
 397         case RT5682_DEVICE_ID:
 398         case RT5682_I2C_MODE:
 399         case RT5682_HP_CALIB_CTRL_10:
 400         case RT5682_EFUSE_CTRL_2:
 401         case RT5682_JD_TOP_VC_VTRL:
 402         case RT5682_HP_IMP_SENS_CTRL_19:
 403         case RT5682_IL_CMD_1:
 404         case RT5682_SAR_IL_CMD_2:
 405         case RT5682_SAR_IL_CMD_4:
 406         case RT5682_SAR_IL_CMD_10:
 407         case RT5682_SAR_IL_CMD_11:
 408         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
 409         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
 410                 return true;
 411         default:
 412                 return false;
 413         }
 414 }
 415 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
 416
 417 bool rt5682_readable_register(struct device *dev, unsigned int reg)
 418 {
 419         switch (reg) {
 420         case RT5682_RESET:
 421         case RT5682_VERSION_ID:
 422         case RT5682_VENDOR_ID:
 423         case RT5682_DEVICE_ID:
 424         case RT5682_HP_CTRL_1:
 425         case RT5682_HP_CTRL_2:
 426         case RT5682_HPL_GAIN:
 427         case RT5682_HPR_GAIN:
 428         case RT5682_I2C_CTRL:
 429         case RT5682_CBJ_BST_CTRL:
 430         case RT5682_CBJ_CTRL_1:
 431         case RT5682_CBJ_CTRL_2:
 432         case RT5682_CBJ_CTRL_3:
 433         case RT5682_CBJ_CTRL_4:
 434         case RT5682_CBJ_CTRL_5:
 435         case RT5682_CBJ_CTRL_6:
 436         case RT5682_CBJ_CTRL_7:
 437         case RT5682_DAC1_DIG_VOL:
 438         case RT5682_STO1_ADC_DIG_VOL:
 439         case RT5682_STO1_ADC_BOOST:
 440         case RT5682_HP_IMP_GAIN_1:
 441         case RT5682_HP_IMP_GAIN_2:
 442         case RT5682_SIDETONE_CTRL:
 443         case RT5682_STO1_ADC_MIXER:
 444         case RT5682_AD_DA_MIXER:
 445         case RT5682_STO1_DAC_MIXER:
 446         case RT5682_A_DAC1_MUX:
 447         case RT5682_DIG_INF2_DATA:
 448         case RT5682_REC_MIXER:
 449         case RT5682_CAL_REC:
 450         case RT5682_ALC_BACK_GAIN:
 451         case RT5682_PWR_DIG_1:
 452         case RT5682_PWR_DIG_2:
 453         case RT5682_PWR_ANLG_1:
 454         case RT5682_PWR_ANLG_2:
 455         case RT5682_PWR_ANLG_3:
 456         case RT5682_PWR_MIXER:
 457         case RT5682_PWR_VOL:
 458         case RT5682_CLK_DET:
 459         case RT5682_RESET_LPF_CTRL:
 460         case RT5682_RESET_HPF_CTRL:
 461         case RT5682_DMIC_CTRL_1:
 462         case RT5682_I2S1_SDP:
 463         case RT5682_I2S2_SDP:
 464         case RT5682_ADDA_CLK_1:
 465         case RT5682_ADDA_CLK_2:
 466         case RT5682_I2S1_F_DIV_CTRL_1:
 467         case RT5682_I2S1_F_DIV_CTRL_2:
 468         case RT5682_TDM_CTRL:
 469         case RT5682_TDM_ADDA_CTRL_1:
 470         case RT5682_TDM_ADDA_CTRL_2:
 471         case RT5682_DATA_SEL_CTRL_1:
 472         case RT5682_TDM_TCON_CTRL:
 473         case RT5682_GLB_CLK:
 474         case RT5682_PLL_CTRL_1:
 475         case RT5682_PLL_CTRL_2:
 476         case RT5682_PLL_TRACK_1:
 477         case RT5682_PLL_TRACK_2:
 478         case RT5682_PLL_TRACK_3:
 479         case RT5682_PLL_TRACK_4:
 480         case RT5682_PLL_TRACK_5:
 481         case RT5682_PLL_TRACK_6:
 482         case RT5682_PLL_TRACK_11:
 483         case RT5682_SDW_REF_CLK:
 484         case RT5682_DEPOP_1:
 485         case RT5682_DEPOP_2:
 486         case RT5682_HP_CHARGE_PUMP_1:
 487         case RT5682_HP_CHARGE_PUMP_2:
 488         case RT5682_MICBIAS_1:
 489         case RT5682_MICBIAS_2:
 490         case RT5682_PLL_TRACK_12:
 491         case RT5682_PLL_TRACK_14:
 492         case RT5682_PLL2_CTRL_1:
 493         case RT5682_PLL2_CTRL_2:
 494         case RT5682_PLL2_CTRL_3:
 495         case RT5682_PLL2_CTRL_4:
 496         case RT5682_RC_CLK_CTRL:
 497         case RT5682_I2S_M_CLK_CTRL_1:
 498         case RT5682_I2S2_F_DIV_CTRL_1:
 499         case RT5682_I2S2_F_DIV_CTRL_2:
 500         case RT5682_EQ_CTRL_1:
 501         case RT5682_EQ_CTRL_2:
 502         case RT5682_IRQ_CTRL_1:
 503         case RT5682_IRQ_CTRL_2:
 504         case RT5682_IRQ_CTRL_3:
 505         case RT5682_IRQ_CTRL_4:
 506         case RT5682_INT_ST_1:
 507         case RT5682_GPIO_CTRL_1:
 508         case RT5682_GPIO_CTRL_2:
 509         case RT5682_GPIO_CTRL_3:
 510         case RT5682_HP_AMP_DET_CTRL_1:
 511         case RT5682_HP_AMP_DET_CTRL_2:
 512         case RT5682_MID_HP_AMP_DET:
 513         case RT5682_LOW_HP_AMP_DET:
 514         case RT5682_DELAY_BUF_CTRL:
 515         case RT5682_SV_ZCD_1:
 516         case RT5682_SV_ZCD_2:
 517         case RT5682_IL_CMD_1:
 518         case RT5682_IL_CMD_2:
 519         case RT5682_IL_CMD_3:
 520         case RT5682_IL_CMD_4:
 521         case RT5682_IL_CMD_5:
 522         case RT5682_IL_CMD_6:
 523         case RT5682_4BTN_IL_CMD_1:
 524         case RT5682_4BTN_IL_CMD_2:
 525         case RT5682_4BTN_IL_CMD_3:
 526         case RT5682_4BTN_IL_CMD_4:
 527         case RT5682_4BTN_IL_CMD_5:
 528         case RT5682_4BTN_IL_CMD_6:
 529         case RT5682_4BTN_IL_CMD_7:
 530         case RT5682_ADC_STO1_HP_CTRL_1:
 531         case RT5682_ADC_STO1_HP_CTRL_2:
 532         case RT5682_AJD1_CTRL:
 533         case RT5682_JD1_THD:
 534         case RT5682_JD2_THD:
 535         case RT5682_JD_CTRL_1:
 536         case RT5682_DUMMY_1:
 537         case RT5682_DUMMY_2:
 538         case RT5682_DUMMY_3:
 539         case RT5682_DAC_ADC_DIG_VOL1:
 540         case RT5682_BIAS_CUR_CTRL_2:
 541         case RT5682_BIAS_CUR_CTRL_3:
 542         case RT5682_BIAS_CUR_CTRL_4:
 543         case RT5682_BIAS_CUR_CTRL_5:
 544         case RT5682_BIAS_CUR_CTRL_6:
 545         case RT5682_BIAS_CUR_CTRL_7:
 546         case RT5682_BIAS_CUR_CTRL_8:
 547         case RT5682_BIAS_CUR_CTRL_9:
 548         case RT5682_BIAS_CUR_CTRL_10:
 549         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
 550         case RT5682_CHARGE_PUMP_1:
 551         case RT5682_DIG_IN_CTRL_1:
 552         case RT5682_PAD_DRIVING_CTRL:
 553         case RT5682_SOFT_RAMP_DEPOP:
 554         case RT5682_CHOP_DAC:
 555         case RT5682_CHOP_ADC:
 556         case RT5682_CALIB_ADC_CTRL:
 557         case RT5682_VOL_TEST:
 558         case RT5682_SPKVDD_DET_STA:
 559         case RT5682_TEST_MODE_CTRL_1:
 560         case RT5682_TEST_MODE_CTRL_2:
 561         case RT5682_TEST_MODE_CTRL_3:
 562         case RT5682_TEST_MODE_CTRL_4:
 563         case RT5682_TEST_MODE_CTRL_5:
 564         case RT5682_PLL1_INTERNAL:
 565         case RT5682_PLL2_INTERNAL:
 566         case RT5682_STO_NG2_CTRL_1:
 567         case RT5682_STO_NG2_CTRL_2:
 568         case RT5682_STO_NG2_CTRL_3:
 569         case RT5682_STO_NG2_CTRL_4:
 570         case RT5682_STO_NG2_CTRL_5:
 571         case RT5682_STO_NG2_CTRL_6:
 572         case RT5682_STO_NG2_CTRL_7:
 573         case RT5682_STO_NG2_CTRL_8:
 574         case RT5682_STO_NG2_CTRL_9:
 575         case RT5682_STO_NG2_CTRL_10:
 576         case RT5682_STO1_DAC_SIL_DET:
 577         case RT5682_SIL_PSV_CTRL1:
 578         case RT5682_SIL_PSV_CTRL2:
 579         case RT5682_SIL_PSV_CTRL3:
 580         case RT5682_SIL_PSV_CTRL4:
 581         case RT5682_SIL_PSV_CTRL5:
 582         case RT5682_HP_IMP_SENS_CTRL_01:
 583         case RT5682_HP_IMP_SENS_CTRL_02:
 584         case RT5682_HP_IMP_SENS_CTRL_03:
 585         case RT5682_HP_IMP_SENS_CTRL_04:
 586         case RT5682_HP_IMP_SENS_CTRL_05:
 587         case RT5682_HP_IMP_SENS_CTRL_06:
 588         case RT5682_HP_IMP_SENS_CTRL_07:
 589         case RT5682_HP_IMP_SENS_CTRL_08:
 590         case RT5682_HP_IMP_SENS_CTRL_09:
 591         case RT5682_HP_IMP_SENS_CTRL_10:
 592         case RT5682_HP_IMP_SENS_CTRL_11:
 593         case RT5682_HP_IMP_SENS_CTRL_12:
 594         case RT5682_HP_IMP_SENS_CTRL_13:
 595         case RT5682_HP_IMP_SENS_CTRL_14:
 596         case RT5682_HP_IMP_SENS_CTRL_15:
 597         case RT5682_HP_IMP_SENS_CTRL_16:
 598         case RT5682_HP_IMP_SENS_CTRL_17:
 599         case RT5682_HP_IMP_SENS_CTRL_18:
 600         case RT5682_HP_IMP_SENS_CTRL_19:
 601         case RT5682_HP_IMP_SENS_CTRL_20:
 602         case RT5682_HP_IMP_SENS_CTRL_21:
 603         case RT5682_HP_IMP_SENS_CTRL_22:
 604         case RT5682_HP_IMP_SENS_CTRL_23:
 605         case RT5682_HP_IMP_SENS_CTRL_24:
 606         case RT5682_HP_IMP_SENS_CTRL_25:
 607         case RT5682_HP_IMP_SENS_CTRL_26:
 608         case RT5682_HP_IMP_SENS_CTRL_27:
 609         case RT5682_HP_IMP_SENS_CTRL_28:
 610         case RT5682_HP_IMP_SENS_CTRL_29:
 611         case RT5682_HP_IMP_SENS_CTRL_30:
 612         case RT5682_HP_IMP_SENS_CTRL_31:
 613         case RT5682_HP_IMP_SENS_CTRL_32:
 614         case RT5682_HP_IMP_SENS_CTRL_33:
 615         case RT5682_HP_IMP_SENS_CTRL_34:
 616         case RT5682_HP_IMP_SENS_CTRL_35:
 617         case RT5682_HP_IMP_SENS_CTRL_36:
 618         case RT5682_HP_IMP_SENS_CTRL_37:
 619         case RT5682_HP_IMP_SENS_CTRL_38:
 620         case RT5682_HP_IMP_SENS_CTRL_39:
 621         case RT5682_HP_IMP_SENS_CTRL_40:
 622         case RT5682_HP_IMP_SENS_CTRL_41:
 623         case RT5682_HP_IMP_SENS_CTRL_42:
 624         case RT5682_HP_IMP_SENS_CTRL_43:
 625         case RT5682_HP_LOGIC_CTRL_1:
 626         case RT5682_HP_LOGIC_CTRL_2:
 627         case RT5682_HP_LOGIC_CTRL_3:
 628         case RT5682_HP_CALIB_CTRL_1:
 629         case RT5682_HP_CALIB_CTRL_2:
 630         case RT5682_HP_CALIB_CTRL_3:
 631         case RT5682_HP_CALIB_CTRL_4:
 632         case RT5682_HP_CALIB_CTRL_5:
 633         case RT5682_HP_CALIB_CTRL_6:
 634         case RT5682_HP_CALIB_CTRL_7:
 635         case RT5682_HP_CALIB_CTRL_9:
 636         case RT5682_HP_CALIB_CTRL_10:
 637         case RT5682_HP_CALIB_CTRL_11:
 638         case RT5682_HP_CALIB_STA_1:
 639         case RT5682_HP_CALIB_STA_2:
 640         case RT5682_HP_CALIB_STA_3:
 641         case RT5682_HP_CALIB_STA_4:
 642         case RT5682_HP_CALIB_STA_5:
 643         case RT5682_HP_CALIB_STA_6:
 644         case RT5682_HP_CALIB_STA_7:
 645         case RT5682_HP_CALIB_STA_8:
 646         case RT5682_HP_CALIB_STA_9:
 647         case RT5682_HP_CALIB_STA_10:
 648         case RT5682_HP_CALIB_STA_11:
 649         case RT5682_SAR_IL_CMD_1:
 650         case RT5682_SAR_IL_CMD_2:
 651         case RT5682_SAR_IL_CMD_3:
 652         case RT5682_SAR_IL_CMD_4:
 653         case RT5682_SAR_IL_CMD_5:
 654         case RT5682_SAR_IL_CMD_6:
 655         case RT5682_SAR_IL_CMD_7:
 656         case RT5682_SAR_IL_CMD_8:
 657         case RT5682_SAR_IL_CMD_9:
 658         case RT5682_SAR_IL_CMD_10:
 659         case RT5682_SAR_IL_CMD_11:
 660         case RT5682_SAR_IL_CMD_12:
 661         case RT5682_SAR_IL_CMD_13:
 662         case RT5682_EFUSE_CTRL_1:
 663         case RT5682_EFUSE_CTRL_2:
 664         case RT5682_EFUSE_CTRL_3:
 665         case RT5682_EFUSE_CTRL_4:
 666         case RT5682_EFUSE_CTRL_5:
 667         case RT5682_EFUSE_CTRL_6:
 668         case RT5682_EFUSE_CTRL_7:
 669         case RT5682_EFUSE_CTRL_8:
 670         case RT5682_EFUSE_CTRL_9:
 671         case RT5682_EFUSE_CTRL_10:
 672         case RT5682_EFUSE_CTRL_11:
 673         case RT5682_JD_TOP_VC_VTRL:
 674         case RT5682_DRC1_CTRL_0:
 675         case RT5682_DRC1_CTRL_1:
 676         case RT5682_DRC1_CTRL_2:
 677         case RT5682_DRC1_CTRL_3:
 678         case RT5682_DRC1_CTRL_4:
 679         case RT5682_DRC1_CTRL_5:
 680         case RT5682_DRC1_CTRL_6:
 681         case RT5682_DRC1_HARD_LMT_CTRL_1:
 682         case RT5682_DRC1_HARD_LMT_CTRL_2:
 683         case RT5682_DRC1_PRIV_1:
 684         case RT5682_DRC1_PRIV_2:
 685         case RT5682_DRC1_PRIV_3:
 686         case RT5682_DRC1_PRIV_4:
 687         case RT5682_DRC1_PRIV_5:
 688         case RT5682_DRC1_PRIV_6:
 689         case RT5682_DRC1_PRIV_7:
 690         case RT5682_DRC1_PRIV_8:
 691         case RT5682_EQ_AUTO_RCV_CTRL1:
 692         case RT5682_EQ_AUTO_RCV_CTRL2:
 693         case RT5682_EQ_AUTO_RCV_CTRL3:
 694         case RT5682_EQ_AUTO_RCV_CTRL4:
 695         case RT5682_EQ_AUTO_RCV_CTRL5:
 696         case RT5682_EQ_AUTO_RCV_CTRL6:
 697         case RT5682_EQ_AUTO_RCV_CTRL7:
 698         case RT5682_EQ_AUTO_RCV_CTRL8:
 699         case RT5682_EQ_AUTO_RCV_CTRL9:
 700         case RT5682_EQ_AUTO_RCV_CTRL10:
 701         case RT5682_EQ_AUTO_RCV_CTRL11:
 702         case RT5682_EQ_AUTO_RCV_CTRL12:
 703         case RT5682_EQ_AUTO_RCV_CTRL13:
 704         case RT5682_ADC_L_EQ_LPF1_A1:
 705         case RT5682_R_EQ_LPF1_A1:
 706         case RT5682_L_EQ_LPF1_H0:
 707         case RT5682_R_EQ_LPF1_H0:
 708         case RT5682_L_EQ_BPF1_A1:
 709         case RT5682_R_EQ_BPF1_A1:
 710         case RT5682_L_EQ_BPF1_A2:
 711         case RT5682_R_EQ_BPF1_A2:
 712         case RT5682_L_EQ_BPF1_H0:
 713         case RT5682_R_EQ_BPF1_H0:
 714         case RT5682_L_EQ_BPF2_A1:
 715         case RT5682_R_EQ_BPF2_A1:
 716         case RT5682_L_EQ_BPF2_A2:
 717         case RT5682_R_EQ_BPF2_A2:
 718         case RT5682_L_EQ_BPF2_H0:
 719         case RT5682_R_EQ_BPF2_H0:
 720         case RT5682_L_EQ_BPF3_A1:
 721         case RT5682_R_EQ_BPF3_A1:
 722         case RT5682_L_EQ_BPF3_A2:
 723         case RT5682_R_EQ_BPF3_A2:
 724         case RT5682_L_EQ_BPF3_H0:
 725         case RT5682_R_EQ_BPF3_H0:
 726         case RT5682_L_EQ_BPF4_A1:
 727         case RT5682_R_EQ_BPF4_A1:
 728         case RT5682_L_EQ_BPF4_A2:
 729         case RT5682_R_EQ_BPF4_A2:
 730         case RT5682_L_EQ_BPF4_H0:
 731         case RT5682_R_EQ_BPF4_H0:
 732         case RT5682_L_EQ_HPF1_A1:
 733         case RT5682_R_EQ_HPF1_A1:
 734         case RT5682_L_EQ_HPF1_H0:
 735         case RT5682_R_EQ_HPF1_H0:
 736         case RT5682_L_EQ_PRE_VOL:
 737         case RT5682_R_EQ_PRE_VOL:
 738         case RT5682_L_EQ_POST_VOL:
 739         case RT5682_R_EQ_POST_VOL:
 740         case RT5682_I2C_MODE:
 741                 return true;
 742         default:
 743                 return false;
 744         }
 745 }
 746 EXPORT_SYMBOL_GPL(rt5682_readable_register);
 747
 748 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 749 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 750 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 751
 752 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 753 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 754         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 755         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 756         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 757         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 758         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 759         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 760         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 761 );
 762
 763 /* Interface data select */
 764 static const char * const rt5682_data_select[] = {
 765         "L/R", "R/L", "L/L", "R/R"
 766 };
 767
 768 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
 769         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
 770
 771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
 772         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
 773
 774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
 775         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
 776
 777 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
 778         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
 779
 780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
 781         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
 782
 783 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
 784         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
 785
 786 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
 787         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
 788
 789 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
 790         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
 791
 792 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
 793         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
 794
 795 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
 796         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
 797
 798 static const char * const rt5682_dac_select[] = {
 799         "IF1", "SOUND"
 800 };
 801
 802 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
 803         RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
 804
 805 static const struct snd_kcontrol_new rt5682_dac_l_mux =
 806         SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
 807
 808 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
 809         RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
 810
 811 static const struct snd_kcontrol_new rt5682_dac_r_mux =
 812         SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
 813
 814 void rt5682_reset(struct rt5682_priv *rt5682)
 815 {
 816         regmap_write(rt5682->regmap, RT5682_RESET, 0);
 817         if (!rt5682->is_sdw)
 818                 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
 819 }
 820 EXPORT_SYMBOL_GPL(rt5682_reset);
 821
 822 /**
 823  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
 824  * @component: SoC audio component device.
 825  * @filter_mask: mask of filters.
 826  * @clk_src: clock source
 827  *
 828  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
 829  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 830  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 831  * ASRC function will track i2s clock and generate a corresponding system clock
 832  * for codec. This function provides an API to select the clock source for a
 833  * set of filters specified by the mask. And the component driver will turn on
 834  * ASRC for these filters if ASRC is selected as their clock source.
 835  */
 836 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
 837                 unsigned int filter_mask, unsigned int clk_src)
 838 {
 839         switch (clk_src) {
 840         case RT5682_CLK_SEL_SYS:
 841         case RT5682_CLK_SEL_I2S1_ASRC:
 842         case RT5682_CLK_SEL_I2S2_ASRC:
 843                 break;
 844
 845         default:
 846                 return -EINVAL;
 847         }
 848
 849         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
 850                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
 851                         RT5682_FILTER_CLK_SEL_MASK,
 852                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 853         }
 854
 855         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
 856                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
 857                         RT5682_FILTER_CLK_SEL_MASK,
 858                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 859         }
 860
 861         return 0;
 862 }
 863 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
 864
 865 static int rt5682_button_detect(struct snd_soc_component *component)
 866 {
 867         int btn_type, val;
 868
 869         val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
 870         btn_type = val & 0xfff0;
 871         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
 872         dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
 873         snd_soc_component_update_bits(component,
 874                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
 875
 876         return btn_type;
 877 }
 878
 879 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
 880                 bool enable)
 881 {
 882         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 883
 884         if (enable) {
 885                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 886                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
 887                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 888                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
 889                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
 890                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 891                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
 892                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
 893                 if (rt5682->is_sdw)
 894                         snd_soc_component_update_bits(component,
 895                                 RT5682_IRQ_CTRL_3,
 896                                 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
 897                                 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
 898                 else
 899                         snd_soc_component_update_bits(component,
 900                                 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
 901                                 RT5682_IL_IRQ_EN);
 902         } else {
 903                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 904                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
 905                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 906                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
 907                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 908                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
 909                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 910                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
 911                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 912                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
 913         }
 914 }
 915
 916 /**
 917  * rt5682_headset_detect - Detect headset.
 918  * @component: SoC audio component device.
 919  * @jack_insert: Jack insert or not.
 920  *
 921  * Detect whether is headset or not when jack inserted.
 922  *
 923  * Returns detect status.
 924  */
 925 static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
 926 {
 927         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 928         struct snd_soc_dapm_context *dapm = &component->dapm;
 929         unsigned int val, count;
 930
 931         if (jack_insert) {
 932                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 933                         RT5682_PWR_VREF2 | RT5682_PWR_MB,
 934                         RT5682_PWR_VREF2 | RT5682_PWR_MB);
 935                 snd_soc_component_update_bits(component,
 936                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
 937                 usleep_range(15000, 20000);
 938                 snd_soc_component_update_bits(component,
 939                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
 940                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 941                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
 942                 snd_soc_component_update_bits(component,
 943                         RT5682_HP_CHARGE_PUMP_1,
 944                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
 945                 rt5682_enable_push_button_irq(component, false);
 946                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 947                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 948                 usleep_range(55000, 60000);
 949                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 950                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
 951
 952                 count = 0;
 953                 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
 954                         & RT5682_JACK_TYPE_MASK;
 955                 while (val == 0 && count < 50) {
 956                         usleep_range(10000, 15000);
 957                         val = snd_soc_component_read(component,
 958                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
 959                         count++;
 960                 }
 961
 962                 switch (val) {
 963                 case 0x1:
 964                 case 0x2:
 965                         rt5682->jack_type = SND_JACK_HEADSET;
 966                         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 967                                 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
 968                         rt5682_enable_push_button_irq(component, true);
 969                         break;
 970                 default:
 971                         rt5682->jack_type = SND_JACK_HEADPHONE;
 972                         break;
 973                 }
 974
 975                 snd_soc_component_update_bits(component,
 976                         RT5682_HP_CHARGE_PUMP_1,
 977                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
 978                         RT5682_OSW_L_EN | RT5682_OSW_R_EN);
 979                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 980                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
 981                         RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
 982         } else {
 983                 rt5682_enable_push_button_irq(component, false);
 984                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 985                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 986                 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
 987                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 988                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 989                         snd_soc_component_update_bits(component,
 990                                 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
 991                 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
 992                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 993                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 994                         snd_soc_component_update_bits(component,
 995                                 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
 996                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 997                         RT5682_PWR_CBJ, 0);
 998                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 999                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
1000                         RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
1001                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
1002                         RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
1003
1004                 rt5682->jack_type = 0;
1005         }
1006
1007         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
1008         return rt5682->jack_type;
1009 }
1010
1011 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1012                 struct snd_soc_jack *hs_jack, void *data)
1013 {
1014         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1015
1016         rt5682->hs_jack = hs_jack;
1017
1018         if (!hs_jack) {
1019                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1020                         RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1021                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1022                         RT5682_POW_JDH | RT5682_POW_JDL, 0);
1023                 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1024
1025                 return 0;
1026         }
1027
1028         if (!rt5682->is_sdw) {
1029                 switch (rt5682->pdata.jd_src) {
1030                 case RT5682_JD1:
1031                         snd_soc_component_update_bits(component,
1032                                 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1033                         snd_soc_component_update_bits(component,
1034                                 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1035                                 RT5682_EXT_JD_SRC_MANUAL);
1036                         snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1037                                 0xd142);
1038                         snd_soc_component_update_bits(component,
1039                                 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1040                                 RT5682_CBJ_IN_BUF_EN);
1041                         snd_soc_component_update_bits(component,
1042                                 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1043                                 RT5682_SAR_POW_EN);
1044                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1045                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1046                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1047                                 RT5682_POW_IRQ | RT5682_POW_JDH |
1048                                 RT5682_POW_ANA, RT5682_POW_IRQ |
1049                                 RT5682_POW_JDH | RT5682_POW_ANA);
1050                         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1051                                 RT5682_PWR_JDH, RT5682_PWR_JDH);
1052                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1053                                 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1054                                 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1055                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1056                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1057                                 rt5682->pdata.btndet_delay));
1058                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1059                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1060                                 rt5682->pdata.btndet_delay));
1061                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1062                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1063                                 rt5682->pdata.btndet_delay));
1064                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1065                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1066                                 rt5682->pdata.btndet_delay));
1067                         mod_delayed_work(system_power_efficient_wq,
1068                                 &rt5682->jack_detect_work,
1069                                 msecs_to_jiffies(250));
1070                         break;
1071
1072                 case RT5682_JD_NULL:
1073                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1074                                 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1075                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1076                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1077                         break;
1078
1079                 default:
1080                         dev_warn(component->dev, "Wrong JD source\n");
1081                         break;
1082                 }
1083         }
1084
1085         return 0;
1086 }
1087
1088 void rt5682_jack_detect_handler(struct work_struct *work)
1089 {
1090         struct rt5682_priv *rt5682 =
1091                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1092         struct snd_soc_dapm_context *dapm;
1093         int val, btn_type;
1094
1095         while (!rt5682->component)
1096                 usleep_range(10000, 15000);
1097
1098         while (!rt5682->component->card->instantiated)
1099                 usleep_range(10000, 15000);
1100
1101         dapm = snd_soc_component_get_dapm(rt5682->component);
1102
1103         snd_soc_dapm_mutex_lock(dapm);
1104         mutex_lock(&rt5682->calibrate_mutex);
1105
1106         val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1107                 & RT5682_JDH_RS_MASK;
1108         if (!val) {
1109                 /* jack in */
1110                 if (rt5682->jack_type == 0) {
1111                         /* jack was out, report jack type */
1112                         rt5682->jack_type =
1113                                 rt5682_headset_detect(rt5682->component, 1);
1114                         rt5682->irq_work_delay_time = 0;
1115                 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1116                         SND_JACK_HEADSET) {
1117                         /* jack is already in, report button event */
1118                         rt5682->jack_type = SND_JACK_HEADSET;
1119                         btn_type = rt5682_button_detect(rt5682->component);
1120                         /**
1121                          * rt5682 can report three kinds of button behavior,
1122                          * one click, double click and hold. However,
1123                          * currently we will report button pressed/released
1124                          * event. So all the three button behaviors are
1125                          * treated as button pressed.
1126                          */
1127                         switch (btn_type) {
1128                         case 0x8000:
1129                         case 0x4000:
1130                         case 0x2000:
1131                                 rt5682->jack_type |= SND_JACK_BTN_0;
1132                                 break;
1133                         case 0x1000:
1134                         case 0x0800:
1135                         case 0x0400:
1136                                 rt5682->jack_type |= SND_JACK_BTN_1;
1137                                 break;
1138                         case 0x0200:
1139                         case 0x0100:
1140                         case 0x0080:
1141                                 rt5682->jack_type |= SND_JACK_BTN_2;
1142                                 break;
1143                         case 0x0040:
1144                         case 0x0020:
1145                         case 0x0010:
1146                                 rt5682->jack_type |= SND_JACK_BTN_3;
1147                                 break;
1148                         case 0x0000: /* unpressed */
1149                                 break;
1150                         default:
1151                                 dev_err(rt5682->component->dev,
1152                                         "Unexpected button code 0x%04x\n",
1153                                         btn_type);
1154                                 break;
1155                         }
1156                 }
1157         } else {
1158                 /* jack out */
1159                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1160                 rt5682->irq_work_delay_time = 50;
1161         }
1162
1163         mutex_unlock(&rt5682->calibrate_mutex);
1164         snd_soc_dapm_mutex_unlock(dapm);
1165
1166         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1167                 SND_JACK_HEADSET |
1168                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1169                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1170
1171         if (!rt5682->is_sdw) {
1172                 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1173                         SND_JACK_BTN_2 | SND_JACK_BTN_3))
1174                         schedule_delayed_work(&rt5682->jd_check_work, 0);
1175                 else
1176                         cancel_delayed_work_sync(&rt5682->jd_check_work);
1177         }
1178 }
1179 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1180
1181 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1182         /* DAC Digital Volume */
1183         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1184                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1185
1186         /* IN Boost Volume */
1187         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1188                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1189
1190         /* ADC Digital Volume Control */
1191         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1192                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1193         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1194                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1195
1196         /* ADC Boost Volume Control */
1197         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1198                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1199                 3, 0, adc_bst_tlv),
1200 };
1201
1202 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1203                 int target, const int div[], int size)
1204 {
1205         int i;
1206
1207         if (rt5682->sysclk < target) {
1208                 dev_err(rt5682->component->dev,
1209                         "sysclk rate %d is too low\n", rt5682->sysclk);
1210                 return 0;
1211         }
1212
1213         for (i = 0; i < size - 1; i++) {
1214                 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1215                 if (target * div[i] == rt5682->sysclk)
1216                         return i;
1217                 if (target * div[i + 1] > rt5682->sysclk) {
1218                         dev_dbg(rt5682->component->dev,
1219                                 "can't find div for sysclk %d\n",
1220                                 rt5682->sysclk);
1221                         return i;
1222                 }
1223         }
1224
1225         if (target * div[i] < rt5682->sysclk)
1226                 dev_err(rt5682->component->dev,
1227                         "sysclk rate %d is too high\n", rt5682->sysclk);
1228
1229         return size - 1;
1230 }
1231
1232 /**
1233  * set_dmic_clk - Set parameter of dmic.
1234  *
1235  * @w: DAPM widget.
1236  * @kcontrol: The kcontrol of this widget.
1237  * @event: Event id.
1238  *
1239  * Choose dmic clock between 1MHz and 3MHz.
1240  * It is better for clock to approximate 3MHz.
1241  */
1242 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1243                 struct snd_kcontrol *kcontrol, int event)
1244 {
1245         struct snd_soc_component *component =
1246                 snd_soc_dapm_to_component(w->dapm);
1247         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1248         int idx, dmic_clk_rate = 3072000;
1249         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1250
1251         if (rt5682->pdata.dmic_clk_rate)
1252                 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1253
1254         idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1255
1256         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1257                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1258
1259         return 0;
1260 }
1261
1262 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1263                 struct snd_kcontrol *kcontrol, int event)
1264 {
1265         struct snd_soc_component *component =
1266                 snd_soc_dapm_to_component(w->dapm);
1267         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1268         int ref, val, reg, idx;
1269         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1270         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1271
1272         if (rt5682->is_sdw)
1273                 return 0;
1274
1275         val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1276                 RT5682_GP4_PIN_MASK;
1277         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1278                 val == RT5682_GP4_PIN_ADCDAT2)
1279                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1280         else
1281                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1282
1283         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1284
1285         if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1286                 reg = RT5682_PLL_TRACK_3;
1287         else
1288                 reg = RT5682_PLL_TRACK_2;
1289
1290         snd_soc_component_update_bits(component, reg,
1291                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1292
1293         /* select over sample rate */
1294         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1295                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1296                         break;
1297         }
1298
1299         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1300                 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1301                 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1302
1303         return 0;
1304 }
1305
1306 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1307                 struct snd_soc_dapm_widget *sink)
1308 {
1309         unsigned int val;
1310         struct snd_soc_component *component =
1311                 snd_soc_dapm_to_component(w->dapm);
1312
1313         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1314         val &= RT5682_SCLK_SRC_MASK;
1315         if (val == RT5682_SCLK_SRC_PLL1)
1316                 return 1;
1317         else
1318                 return 0;
1319 }
1320
1321 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1322                 struct snd_soc_dapm_widget *sink)
1323 {
1324         unsigned int val;
1325         struct snd_soc_component *component =
1326                 snd_soc_dapm_to_component(w->dapm);
1327
1328         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1329         val &= RT5682_SCLK_SRC_MASK;
1330         if (val == RT5682_SCLK_SRC_PLL2)
1331                 return 1;
1332         else
1333                 return 0;
1334 }
1335
1336 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1337                 struct snd_soc_dapm_widget *sink)
1338 {
1339         unsigned int reg, shift, val;
1340         struct snd_soc_component *component =
1341                 snd_soc_dapm_to_component(w->dapm);
1342
1343         switch (w->shift) {
1344         case RT5682_ADC_STO1_ASRC_SFT:
1345                 reg = RT5682_PLL_TRACK_3;
1346                 shift = RT5682_FILTER_CLK_SEL_SFT;
1347                 break;
1348         case RT5682_DAC_STO1_ASRC_SFT:
1349                 reg = RT5682_PLL_TRACK_2;
1350                 shift = RT5682_FILTER_CLK_SEL_SFT;
1351                 break;
1352         default:
1353                 return 0;
1354         }
1355
1356         val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1357         switch (val) {
1358         case RT5682_CLK_SEL_I2S1_ASRC:
1359         case RT5682_CLK_SEL_I2S2_ASRC:
1360                 return 1;
1361         default:
1362                 return 0;
1363         }
1364 }
1365
1366 /* Digital Mixer */
1367 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1368         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1369                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1370         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1371                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1372 };
1373
1374 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1375         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1376                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1377         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1378                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1379 };
1380
1381 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1382         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1383                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1384         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1385                         RT5682_M_DAC1_L_SFT, 1, 1),
1386 };
1387
1388 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1389         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1390                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1391         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1392                         RT5682_M_DAC1_R_SFT, 1, 1),
1393 };
1394
1395 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1396         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1397                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1398         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1399                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1400 };
1401
1402 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1403         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1404                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1405         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1406                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1407 };
1408
1409 /* Analog Input Mixer */
1410 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1411         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1412                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1413 };
1414
1415 /* STO1 ADC1 Source */
1416 /* MX-26 [13] [5] */
1417 static const char * const rt5682_sto1_adc1_src[] = {
1418         "DAC MIX", "ADC"
1419 };
1420
1421 static SOC_ENUM_SINGLE_DECL(
1422         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1423         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1424
1425 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1426         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1427
1428 static SOC_ENUM_SINGLE_DECL(
1429         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1430         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1431
1432 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1433         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1434
1435 /* STO1 ADC Source */
1436 /* MX-26 [11:10] [3:2] */
1437 static const char * const rt5682_sto1_adc_src[] = {
1438         "ADC1 L", "ADC1 R"
1439 };
1440
1441 static SOC_ENUM_SINGLE_DECL(
1442         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1443         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1444
1445 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1446         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1447
1448 static SOC_ENUM_SINGLE_DECL(
1449         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1450         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1451
1452 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1453         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1454
1455 /* STO1 ADC2 Source */
1456 /* MX-26 [12] [4] */
1457 static const char * const rt5682_sto1_adc2_src[] = {
1458         "DAC MIX", "DMIC"
1459 };
1460
1461 static SOC_ENUM_SINGLE_DECL(
1462         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1463         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1464
1465 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1466         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1467
1468 static SOC_ENUM_SINGLE_DECL(
1469         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1470         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1471
1472 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1473         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1474
1475 /* MX-79 [6:4] I2S1 ADC data location */
1476 static const unsigned int rt5682_if1_adc_slot_values[] = {
1477         0,
1478         2,
1479         4,
1480         6,
1481 };
1482
1483 static const char * const rt5682_if1_adc_slot_src[] = {
1484         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1485 };
1486
1487 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1488         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1489         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1490
1491 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1492         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1493
1494 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1495 /* MX-2B [4], MX-2B [0]*/
1496 static const char * const rt5682_alg_dac1_src[] = {
1497         "Stereo1 DAC Mixer", "DAC1"
1498 };
1499
1500 static SOC_ENUM_SINGLE_DECL(
1501         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1502         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1503
1504 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1505         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1506
1507 static SOC_ENUM_SINGLE_DECL(
1508         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1509         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1510
1511 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1512         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1513
1514 /* Out Switch */
1515 static const struct snd_kcontrol_new hpol_switch =
1516         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1517                 RT5682_L_MUTE_SFT, 1, 1);
1518 static const struct snd_kcontrol_new hpor_switch =
1519         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1520                 RT5682_R_MUTE_SFT, 1, 1);
1521
1522 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1523                 struct snd_kcontrol *kcontrol, int event)
1524 {
1525         struct snd_soc_component *component =
1526                 snd_soc_dapm_to_component(w->dapm);
1527
1528         switch (event) {
1529         case SND_SOC_DAPM_PRE_PMU:
1530                 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1531                         RT5682_HP_C2_DAC_AMP_MUTE, 0);
1532                 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
1533                         RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
1534                 snd_soc_component_update_bits(component,
1535                         RT5682_DEPOP_1, 0x60, 0x60);
1536                 snd_soc_component_update_bits(component,
1537                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1538                 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1539                         RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
1540                         RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
1541                 usleep_range(5000, 10000);
1542                 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1543                         RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
1544                 break;
1545
1546         case SND_SOC_DAPM_POST_PMD:
1547                 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1548                         RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);
1549                 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1550                         RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
1551                 snd_soc_component_update_bits(component,
1552                         RT5682_DEPOP_1, 0x60, 0x0);
1553                 snd_soc_component_update_bits(component,
1554                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1555                 break;
1556         }
1557
1558         return 0;
1559 }
1560
1561 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1562                 struct snd_kcontrol *kcontrol, int event)
1563 {
1564         struct snd_soc_component *component =
1565                 snd_soc_dapm_to_component(w->dapm);
1566         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1567         unsigned int delay = 50, val;
1568
1569         if (rt5682->pdata.dmic_delay)
1570                 delay = rt5682->pdata.dmic_delay;
1571
1572         switch (event) {
1573         case SND_SOC_DAPM_POST_PMU:
1574                 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1575                 val &= RT5682_SCLK_SRC_MASK;
1576                 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1577                         snd_soc_component_update_bits(component,
1578                                 RT5682_PWR_ANLG_1,
1579                                 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1580                                 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1581
1582                 /*Add delay to avoid pop noise*/
1583                 msleep(delay);
1584                 break;
1585
1586         case SND_SOC_DAPM_POST_PMD:
1587                 if (!rt5682->jack_type) {
1588                         if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1589                                 snd_soc_component_update_bits(component,
1590                                         RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1591                         if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1592                                 snd_soc_component_update_bits(component,
1593                                         RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1594                 }
1595                 break;
1596         }
1597
1598         return 0;
1599 }
1600
1601 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1602                 struct snd_kcontrol *kcontrol, int event)
1603 {
1604         struct snd_soc_component *component =
1605                 snd_soc_dapm_to_component(w->dapm);
1606
1607         switch (event) {
1608         case SND_SOC_DAPM_PRE_PMU:
1609                 switch (w->shift) {
1610                 case RT5682_PWR_VREF1_BIT:
1611                         snd_soc_component_update_bits(component,
1612                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1613                         break;
1614
1615                 case RT5682_PWR_VREF2_BIT:
1616                         snd_soc_component_update_bits(component,
1617                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1618                         break;
1619                 }
1620                 break;
1621
1622         case SND_SOC_DAPM_POST_PMU:
1623                 usleep_range(15000, 20000);
1624                 switch (w->shift) {
1625                 case RT5682_PWR_VREF1_BIT:
1626                         snd_soc_component_update_bits(component,
1627                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1628                                 RT5682_PWR_FV1);
1629                         break;
1630
1631                 case RT5682_PWR_VREF2_BIT:
1632                         snd_soc_component_update_bits(component,
1633                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1634                                 RT5682_PWR_FV2);
1635                         break;
1636                 }
1637                 break;
1638         }
1639
1640         return 0;
1641 }
1642
1643 static const unsigned int rt5682_adcdat_pin_values[] = {
1644         1,
1645         3,
1646 };
1647
1648 static const char * const rt5682_adcdat_pin_select[] = {
1649         "ADCDAT1",
1650         "ADCDAT2",
1651 };
1652
1653 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1654         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1655         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1656
1657 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1658         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1659
1660 static const unsigned int rt5682_hpo_sig_out_values[] = {
1661         2,
1662         7,
1663 };
1664
1665 static const char * const rt5682_hpo_sig_out_mode[] = {
1666         "Legacy",
1667         "OneBit",
1668 };
1669
1670 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
1671         RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
1672         rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
1673
1674 static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
1675         SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
1676
1677 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1678         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1679                 0, NULL, 0),
1680         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1681                 0, NULL, 0),
1682         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1683                 0, NULL, 0),
1684         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1685                 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1686         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1687                 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1688         SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1689         SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1690
1691         /* ASRC */
1692         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1693                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1694         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1695                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1696         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1697                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1698         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1699                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1700         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1701                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1702
1703         /* Input Side */
1704         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1705                 0, NULL, 0),
1706         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1707                 0, NULL, 0),
1708
1709         /* Input Lines */
1710         SND_SOC_DAPM_INPUT("DMIC L1"),
1711         SND_SOC_DAPM_INPUT("DMIC R1"),
1712
1713         SND_SOC_DAPM_INPUT("IN1P"),
1714
1715         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1716                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1717         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1718                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1719                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1720
1721         /* Boost */
1722         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1723                 0, 0, NULL, 0),
1724
1725         /* REC Mixer */
1726         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1727                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1728         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1729                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1730
1731         /* ADCs */
1732         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1733         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1734
1735         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1736                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1737         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1738                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1739         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1740                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1741
1742         /* ADC Mux */
1743         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1744                 &rt5682_sto1_adc1l_mux),
1745         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1746                 &rt5682_sto1_adc1r_mux),
1747         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1748                 &rt5682_sto1_adc2l_mux),
1749         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1750                 &rt5682_sto1_adc2r_mux),
1751         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1752                 &rt5682_sto1_adcl_mux),
1753         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1754                 &rt5682_sto1_adcr_mux),
1755         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1756                 &rt5682_if1_adc_slot_mux),
1757
1758         /* ADC Mixer */
1759         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1760                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1761                 SND_SOC_DAPM_PRE_PMU),
1762         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1763                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1764                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1765         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1766                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1767                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1768
1769         /* ADC PGA */
1770         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1771
1772         /* Digital Interface */
1773         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1774                 0, NULL, 0),
1775         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1776                 0, NULL, 0),
1777         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1778         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1779         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1780         SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1781         SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1782
1783         /* Digital Interface Select */
1784         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1785                 &rt5682_if1_01_adc_swap_mux),
1786         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1787                 &rt5682_if1_23_adc_swap_mux),
1788         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1789                 &rt5682_if1_45_adc_swap_mux),
1790         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1791                 &rt5682_if1_67_adc_swap_mux),
1792         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1793                 &rt5682_if2_adc_swap_mux),
1794
1795         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1796                 &rt5682_adcdat_pin_ctrl),
1797
1798         SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1799                 &rt5682_dac_l_mux),
1800         SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1801                 &rt5682_dac_r_mux),
1802
1803         /* Audio Interface */
1804         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1805                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1806         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1807                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1808         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1809         SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1810         SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1811
1812         /* Output Side */
1813         /* DAC mixer before sound effect  */
1814         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1815                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1816         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1817                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1818
1819         /* DAC channel Mux */
1820         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1821                 &rt5682_alg_dac_l1_mux),
1822         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1823                 &rt5682_alg_dac_r1_mux),
1824
1825         /* DAC Mixer */
1826         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1827                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1828                 SND_SOC_DAPM_PRE_PMU),
1829         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1830                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1831         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1832                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1833
1834         /* DACs */
1835         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1836                 RT5682_PWR_DAC_L1_BIT, 0),
1837         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1838                 RT5682_PWR_DAC_R1_BIT, 0),
1839         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1840                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1841
1842         /* HPO */
1843         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1844                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1845
1846         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1847                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1848         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1849                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1850         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1851                 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1852         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1853                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1854
1855         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1856                 &hpol_switch),
1857         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1858                 &hpor_switch),
1859
1860         SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
1861         SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
1862         SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
1863
1864         /* CLK DET */
1865         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1866                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1867         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1868                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1869         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1870                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1871         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1872                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1873
1874         /* Output Lines */
1875         SND_SOC_DAPM_OUTPUT("HPOL"),
1876         SND_SOC_DAPM_OUTPUT("HPOR"),
1877 };
1878
1879 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1880         /*PLL*/
1881         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1882         {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1883         {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1884         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1885         {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1886         {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1887
1888         /*ASRC*/
1889         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1890         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1891         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1892         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1893         {"ADC STO1 ASRC", NULL, "CLKDET"},
1894         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1895         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1896         {"DAC STO1 ASRC", NULL, "CLKDET"},
1897
1898         /*Vref*/
1899         {"MICBIAS1", NULL, "Vref1"},
1900         {"MICBIAS2", NULL, "Vref1"},
1901
1902         {"CLKDET SYS", NULL, "CLKDET"},
1903
1904         {"BST1 CBJ", NULL, "IN1P"},
1905
1906         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1907         {"RECMIX1L", NULL, "RECMIX1L Power"},
1908
1909         {"ADC1 L", NULL, "RECMIX1L"},
1910         {"ADC1 L", NULL, "ADC1 L Power"},
1911         {"ADC1 L", NULL, "ADC1 clock"},
1912
1913         {"DMIC L1", NULL, "DMIC CLK"},
1914         {"DMIC L1", NULL, "DMIC1 Power"},
1915         {"DMIC R1", NULL, "DMIC CLK"},
1916         {"DMIC R1", NULL, "DMIC1 Power"},
1917         {"DMIC CLK", NULL, "DMIC ASRC"},
1918
1919         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1920         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1921         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1922         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1923
1924         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1925         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1926         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1927         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1928
1929         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1930         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1931         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1932         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1933
1934         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1935         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1936         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1937
1938         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1939         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1940         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1941
1942         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1943         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1944
1945         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1946         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1947         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1948         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1949         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1950         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1951         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1952         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1953         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1954         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1955         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1956         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1957         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1958         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1959         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1960         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1961
1962         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1963         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1964         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1965         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1966         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1967         {"AIF1TX", NULL, "I2S1"},
1968         {"AIF1TX", NULL, "ADCDAT Mux"},
1969         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1970         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1971         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1972         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1973         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1974         {"AIF2TX", NULL, "ADCDAT Mux"},
1975
1976         {"SDWTX", NULL, "PLL2B"},
1977         {"SDWTX", NULL, "PLL2F"},
1978         {"SDWTX", NULL, "ADCDAT Mux"},
1979
1980         {"IF1 DAC1 L", NULL, "AIF1RX"},
1981         {"IF1 DAC1 L", NULL, "I2S1"},
1982         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1983         {"IF1 DAC1 R", NULL, "AIF1RX"},
1984         {"IF1 DAC1 R", NULL, "I2S1"},
1985         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1986
1987         {"SOUND DAC L", NULL, "SDWRX"},
1988         {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1989         {"SOUND DAC L", NULL, "PLL2B"},
1990         {"SOUND DAC L", NULL, "PLL2F"},
1991         {"SOUND DAC R", NULL, "SDWRX"},
1992         {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1993         {"SOUND DAC R", NULL, "PLL2B"},
1994         {"SOUND DAC R", NULL, "PLL2F"},
1995
1996         {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1997         {"DAC L Mux", "SOUND", "SOUND DAC L"},
1998         {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1999         {"DAC R Mux", "SOUND", "SOUND DAC R"},
2000
2001         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2002         {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
2003         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2004         {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
2005
2006         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
2007         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
2008
2009         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
2010         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
2011
2012         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
2013         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
2014         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
2015         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
2016
2017         {"DAC L1", NULL, "DAC L1 Source"},
2018         {"DAC R1", NULL, "DAC R1 Source"},
2019
2020         {"DAC L1", NULL, "DAC 1 Clock"},
2021         {"DAC R1", NULL, "DAC 1 Clock"},
2022
2023         {"HP Amp", NULL, "DAC L1"},
2024         {"HP Amp", NULL, "DAC R1"},
2025         {"HP Amp", NULL, "HP Amp L"},
2026         {"HP Amp", NULL, "HP Amp R"},
2027         {"HP Amp", NULL, "Capless"},
2028         {"HP Amp", NULL, "Charge Pump"},
2029         {"HP Amp", NULL, "CLKDET SYS"},
2030         {"HP Amp", NULL, "Vref1"},
2031
2032         {"HPO Signal Demux", NULL, "HP Amp"},
2033
2034         {"HPO Legacy", "Legacy", "HPO Signal Demux"},
2035         {"HPO OneBit", "OneBit", "HPO Signal Demux"},
2036
2037         {"HPOL Playback", "Switch", "HPO Legacy"},
2038         {"HPOR Playback", "Switch", "HPO Legacy"},
2039
2040         {"HPOL", NULL, "HPOL Playback"},
2041         {"HPOR", NULL, "HPOR Playback"},
2042         {"HPOL", NULL, "HPO OneBit"},
2043         {"HPOR", NULL, "HPO OneBit"},
2044 };
2045
2046 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2047                 unsigned int rx_mask, int slots, int slot_width)
2048 {
2049         struct snd_soc_component *component = dai->component;
2050         unsigned int cl, val = 0;
2051
2052         if (tx_mask || rx_mask)
2053                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2054                         RT5682_TDM_EN, RT5682_TDM_EN);
2055         else
2056                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2057                         RT5682_TDM_EN, 0);
2058
2059         switch (slots) {
2060         case 4:
2061                 val |= RT5682_TDM_TX_CH_4;
2062                 val |= RT5682_TDM_RX_CH_4;
2063                 break;
2064         case 6:
2065                 val |= RT5682_TDM_TX_CH_6;
2066                 val |= RT5682_TDM_RX_CH_6;
2067                 break;
2068         case 8:
2069                 val |= RT5682_TDM_TX_CH_8;
2070                 val |= RT5682_TDM_RX_CH_8;
2071                 break;
2072         case 2:
2073                 break;
2074         default:
2075                 return -EINVAL;
2076         }
2077
2078         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2079                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2080
2081         switch (slot_width) {
2082         case 8:
2083                 if (tx_mask || rx_mask)
2084                         return -EINVAL;
2085                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2086                 break;
2087         case 16:
2088                 val = RT5682_TDM_CL_16;
2089                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2090                 break;
2091         case 20:
2092                 val = RT5682_TDM_CL_20;
2093                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2094                 break;
2095         case 24:
2096                 val = RT5682_TDM_CL_24;
2097                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2098                 break;
2099         case 32:
2100                 val = RT5682_TDM_CL_32;
2101                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2102                 break;
2103         default:
2104                 return -EINVAL;
2105         }
2106
2107         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2108                 RT5682_TDM_CL_MASK, val);
2109         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2110                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2111
2112         return 0;
2113 }
2114
2115 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2116                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2117 {
2118         struct snd_soc_component *component = dai->component;
2119         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2120         unsigned int len_1 = 0, len_2 = 0;
2121         int pre_div, frame_size;
2122
2123         rt5682->lrck[dai->id] = params_rate(params);
2124         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2125
2126         frame_size = snd_soc_params_to_frame_size(params);
2127         if (frame_size < 0) {
2128                 dev_err(component->dev, "Unsupported frame size: %d\n",
2129                         frame_size);
2130                 return -EINVAL;
2131         }
2132
2133         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2134                 rt5682->lrck[dai->id], pre_div, dai->id);
2135
2136         switch (params_width(params)) {
2137         case 16:
2138                 break;
2139         case 20:
2140                 len_1 |= RT5682_I2S1_DL_20;
2141                 len_2 |= RT5682_I2S2_DL_20;
2142                 break;
2143         case 24:
2144                 len_1 |= RT5682_I2S1_DL_24;
2145                 len_2 |= RT5682_I2S2_DL_24;
2146                 break;
2147         case 32:
2148                 len_1 |= RT5682_I2S1_DL_32;
2149                 len_2 |= RT5682_I2S2_DL_24;
2150                 break;
2151         case 8:
2152                 len_1 |= RT5682_I2S2_DL_8;
2153                 len_2 |= RT5682_I2S2_DL_8;
2154                 break;
2155         default:
2156                 return -EINVAL;
2157         }
2158
2159         switch (dai->id) {
2160         case RT5682_AIF1:
2161                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2162                         RT5682_I2S1_DL_MASK, len_1);
2163                 if (rt5682->master[RT5682_AIF1]) {
2164                         snd_soc_component_update_bits(component,
2165                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2166                                 RT5682_I2S_CLK_SRC_MASK,
2167                                 pre_div << RT5682_I2S_M_DIV_SFT |
2168                                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2169                 }
2170                 if (params_channels(params) == 1) /* mono mode */
2171                         snd_soc_component_update_bits(component,
2172                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2173                                 RT5682_I2S1_MONO_EN);
2174                 else
2175                         snd_soc_component_update_bits(component,
2176                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2177                                 RT5682_I2S1_MONO_DIS);
2178                 break;
2179         case RT5682_AIF2:
2180                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2181                         RT5682_I2S2_DL_MASK, len_2);
2182                 if (rt5682->master[RT5682_AIF2]) {
2183                         snd_soc_component_update_bits(component,
2184                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2185                                 pre_div << RT5682_I2S2_M_PD_SFT);
2186                 }
2187                 if (params_channels(params) == 1) /* mono mode */
2188                         snd_soc_component_update_bits(component,
2189                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2190                                 RT5682_I2S2_MONO_EN);
2191                 else
2192                         snd_soc_component_update_bits(component,
2193                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2194                                 RT5682_I2S2_MONO_DIS);
2195                 break;
2196         default:
2197                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2198                 return -EINVAL;
2199         }
2200
2201         return 0;
2202 }
2203
2204 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2205 {
2206         struct snd_soc_component *component = dai->component;
2207         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2208         unsigned int reg_val = 0, tdm_ctrl = 0;
2209
2210         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2211         case SND_SOC_DAIFMT_CBM_CFM:
2212                 rt5682->master[dai->id] = 1;
2213                 break;
2214         case SND_SOC_DAIFMT_CBS_CFS:
2215                 rt5682->master[dai->id] = 0;
2216                 break;
2217         default:
2218                 return -EINVAL;
2219         }
2220
2221         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2222         case SND_SOC_DAIFMT_NB_NF:
2223                 break;
2224         case SND_SOC_DAIFMT_IB_NF:
2225                 reg_val |= RT5682_I2S_BP_INV;
2226                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2227                 break;
2228         case SND_SOC_DAIFMT_NB_IF:
2229                 if (dai->id == RT5682_AIF1)
2230                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2231                 else
2232                         return -EINVAL;
2233                 break;
2234         case SND_SOC_DAIFMT_IB_IF:
2235                 if (dai->id == RT5682_AIF1)
2236                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2237                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2238                 else
2239                         return -EINVAL;
2240                 break;
2241         default:
2242                 return -EINVAL;
2243         }
2244
2245         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2246         case SND_SOC_DAIFMT_I2S:
2247                 break;
2248         case SND_SOC_DAIFMT_LEFT_J:
2249                 reg_val |= RT5682_I2S_DF_LEFT;
2250                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2251                 break;
2252         case SND_SOC_DAIFMT_DSP_A:
2253                 reg_val |= RT5682_I2S_DF_PCM_A;
2254                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2255                 break;
2256         case SND_SOC_DAIFMT_DSP_B:
2257                 reg_val |= RT5682_I2S_DF_PCM_B;
2258                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2259                 break;
2260         default:
2261                 return -EINVAL;
2262         }
2263
2264         switch (dai->id) {
2265         case RT5682_AIF1:
2266                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2267                         RT5682_I2S_DF_MASK, reg_val);
2268                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2269                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2270                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2271                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2272                         tdm_ctrl | rt5682->master[dai->id]);
2273                 break;
2274         case RT5682_AIF2:
2275                 if (rt5682->master[dai->id] == 0)
2276                         reg_val |= RT5682_I2S2_MS_S;
2277                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2278                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2279                         RT5682_I2S_DF_MASK, reg_val);
2280                 break;
2281         default:
2282                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2283                 return -EINVAL;
2284         }
2285         return 0;
2286 }
2287
2288 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2289                 int clk_id, int source, unsigned int freq, int dir)
2290 {
2291         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2292         unsigned int reg_val = 0, src = 0;
2293
2294         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2295                 return 0;
2296
2297         switch (clk_id) {
2298         case RT5682_SCLK_S_MCLK:
2299                 reg_val |= RT5682_SCLK_SRC_MCLK;
2300                 src = RT5682_CLK_SRC_MCLK;
2301                 break;
2302         case RT5682_SCLK_S_PLL1:
2303                 reg_val |= RT5682_SCLK_SRC_PLL1;
2304                 src = RT5682_CLK_SRC_PLL1;
2305                 break;
2306         case RT5682_SCLK_S_PLL2:
2307                 reg_val |= RT5682_SCLK_SRC_PLL2;
2308                 src = RT5682_CLK_SRC_PLL2;
2309                 break;
2310         case RT5682_SCLK_S_RCCLK:
2311                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2312                 src = RT5682_CLK_SRC_RCCLK;
2313                 break;
2314         default:
2315                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2316                 return -EINVAL;
2317         }
2318         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2319                 RT5682_SCLK_SRC_MASK, reg_val);
2320
2321         if (rt5682->master[RT5682_AIF2]) {
2322                 snd_soc_component_update_bits(component,
2323                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2324                         src << RT5682_I2S2_SRC_SFT);
2325         }
2326
2327         rt5682->sysclk = freq;
2328         rt5682->sysclk_src = clk_id;
2329
2330         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2331                 freq, clk_id);
2332
2333         return 0;
2334 }
2335
2336 static int rt5682_set_component_pll(struct snd_soc_component *component,
2337                 int pll_id, int source, unsigned int freq_in,
2338                 unsigned int freq_out)
2339 {
2340         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2341         struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2342         unsigned int pll2_fout1, pll2_ps_val;
2343         int ret;
2344
2345         if (source == rt5682->pll_src[pll_id] &&
2346             freq_in == rt5682->pll_in[pll_id] &&
2347             freq_out == rt5682->pll_out[pll_id])
2348                 return 0;
2349
2350         if (!freq_in || !freq_out) {
2351                 dev_dbg(component->dev, "PLL disabled\n");
2352
2353                 rt5682->pll_in[pll_id] = 0;
2354                 rt5682->pll_out[pll_id] = 0;
2355                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2356                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2357                 return 0;
2358         }
2359
2360         if (pll_id == RT5682_PLL2) {
2361                 switch (source) {
2362                 case RT5682_PLL2_S_MCLK:
2363                         snd_soc_component_update_bits(component,
2364                                 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2365                                 RT5682_PLL2_SRC_MCLK);
2366                         break;
2367                 default:
2368                         dev_err(component->dev, "Unknown PLL2 Source %d\n",
2369                                 source);
2370                         return -EINVAL;
2371                 }
2372
2373                 /**
2374                  * PLL2 concatenates 2 PLL units.
2375                  * We suggest the Fout of the front PLL is 3.84MHz.
2376                  */
2377                 pll2_fout1 = 3840000;
2378                 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2379                 if (ret < 0) {
2380                         dev_err(component->dev, "Unsupported input clock %d\n",
2381                                 freq_in);
2382                         return ret;
2383                 }
2384                 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2385                         freq_in, pll2_fout1,
2386                         pll2f_code.m_bp,
2387                         (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2388                         pll2f_code.n_code, pll2f_code.k_code);
2389
2390                 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2391                 if (ret < 0) {
2392                         dev_err(component->dev, "Unsupported input clock %d\n",
2393                                 pll2_fout1);
2394                         return ret;
2395                 }
2396                 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2397                         pll2_fout1, freq_out,
2398                         pll2b_code.m_bp,
2399                         (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2400                         pll2b_code.n_code, pll2b_code.k_code);
2401
2402                 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2403                         pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2404                         pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2405                         pll2b_code.m_code);
2406                 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2407                         pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2408                         pll2b_code.n_code);
2409                 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2410                         pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2411
2412                 if (freq_out == 22579200)
2413                         pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2414                 else
2415                         pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2416                 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2417                         RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2418                         RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2419                         pll2_ps_val |
2420                         (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2421                         (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2422                         0xf);
2423         } else {
2424                 switch (source) {
2425                 case RT5682_PLL1_S_MCLK:
2426                         snd_soc_component_update_bits(component,
2427                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2428                                 RT5682_PLL1_SRC_MCLK);
2429                         break;
2430                 case RT5682_PLL1_S_BCLK1:
2431                         snd_soc_component_update_bits(component,
2432                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2433                                 RT5682_PLL1_SRC_BCLK1);
2434                         break;
2435                 default:
2436                         dev_err(component->dev, "Unknown PLL1 Source %d\n",
2437                                 source);
2438                         return -EINVAL;
2439                 }
2440
2441                 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2442                 if (ret < 0) {
2443                         dev_err(component->dev, "Unsupported input clock %d\n",
2444                                 freq_in);
2445                         return ret;
2446                 }
2447
2448                 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2449                         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2450                         pll_code.n_code, pll_code.k_code);
2451
2452                 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2453                         (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2454                 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2455                         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2456                         ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2457         }
2458
2459         rt5682->pll_in[pll_id] = freq_in;
2460         rt5682->pll_out[pll_id] = freq_out;
2461         rt5682->pll_src[pll_id] = source;
2462
2463         return 0;
2464 }
2465
2466 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2467 {
2468         struct snd_soc_component *component = dai->component;
2469         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2470
2471         rt5682->bclk[dai->id] = ratio;
2472
2473         switch (ratio) {
2474         case 256:
2475                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2476                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2477                 break;
2478         case 128:
2479                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2480                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2481                 break;
2482         case 64:
2483                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2484                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2485                 break;
2486         case 32:
2487                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2488                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2489                 break;
2490         default:
2491                 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2492                 return -EINVAL;
2493         }
2494
2495         return 0;
2496 }
2497
2498 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2499 {
2500         struct snd_soc_component *component = dai->component;
2501         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2502
2503         rt5682->bclk[dai->id] = ratio;
2504
2505         switch (ratio) {
2506         case 64:
2507                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2508                         RT5682_I2S2_BCLK_MS2_MASK,
2509                         RT5682_I2S2_BCLK_MS2_64);
2510                 break;
2511         case 32:
2512                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2513                         RT5682_I2S2_BCLK_MS2_MASK,
2514                         RT5682_I2S2_BCLK_MS2_32);
2515                 break;
2516         default:
2517                 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2518                 return -EINVAL;
2519         }
2520
2521         return 0;
2522 }
2523
2524 static int rt5682_set_bias_level(struct snd_soc_component *component,
2525                 enum snd_soc_bias_level level)
2526 {
2527         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2528
2529         switch (level) {
2530         case SND_SOC_BIAS_PREPARE:
2531                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2532                         RT5682_PWR_BG, RT5682_PWR_BG);
2533                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2534                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2535                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2536                 break;
2537
2538         case SND_SOC_BIAS_STANDBY:
2539                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2540                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2541                 break;
2542         case SND_SOC_BIAS_OFF:
2543                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2544                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2545                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2546                         RT5682_PWR_BG, 0);
2547                 break;
2548         case SND_SOC_BIAS_ON:
2549                 break;
2550         }
2551
2552         return 0;
2553 }
2554
2555 #ifdef CONFIG_COMMON_CLK
2556 #define CLK_PLL2_FIN 48000000
2557 #define CLK_48 48000
2558 #define CLK_44 44100
2559
2560 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2561 {
2562         if (!rt5682->master[RT5682_AIF1]) {
2563                 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
2564                 return false;
2565         }
2566         return true;
2567 }
2568
2569 static int rt5682_wclk_prepare(struct clk_hw *hw)
2570 {
2571         struct rt5682_priv *rt5682 =
2572                 container_of(hw, struct rt5682_priv,
2573                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2574         struct snd_soc_component *component;
2575         struct snd_soc_dapm_context *dapm;
2576
2577         if (!rt5682_clk_check(rt5682))
2578                 return -EINVAL;
2579
2580         component = rt5682->component;
2581         dapm = snd_soc_component_get_dapm(component);
2582
2583         snd_soc_dapm_mutex_lock(dapm);
2584
2585         snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2586         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2587                                 RT5682_PWR_MB, RT5682_PWR_MB);
2588
2589         snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2590         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2591                         RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2592                         RT5682_PWR_VREF2);
2593         usleep_range(55000, 60000);
2594         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2595                         RT5682_PWR_FV2, RT5682_PWR_FV2);
2596
2597         snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2598         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2599         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2600         snd_soc_dapm_sync_unlocked(dapm);
2601
2602         snd_soc_dapm_mutex_unlock(dapm);
2603
2604         return 0;
2605 }
2606
2607 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2608 {
2609         struct rt5682_priv *rt5682 =
2610                 container_of(hw, struct rt5682_priv,
2611                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2612         struct snd_soc_component *component;
2613         struct snd_soc_dapm_context *dapm;
2614
2615         if (!rt5682_clk_check(rt5682))
2616                 return;
2617
2618         component = rt5682->component;
2619         dapm = snd_soc_component_get_dapm(component);
2620
2621         snd_soc_dapm_mutex_lock(dapm);
2622
2623         snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2624         snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2625         if (!rt5682->jack_type)
2626                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2627                                 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2628                                 RT5682_PWR_MB, 0);
2629
2630         snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2631         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2632         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2633         snd_soc_dapm_sync_unlocked(dapm);
2634
2635         snd_soc_dapm_mutex_unlock(dapm);
2636 }
2637
2638 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2639                                              unsigned long parent_rate)
2640 {
2641         struct rt5682_priv *rt5682 =
2642                 container_of(hw, struct rt5682_priv,
2643                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2644         const char * const clk_name = clk_hw_get_name(hw);
2645
2646         if (!rt5682_clk_check(rt5682))
2647                 return 0;
2648         /*
2649          * Only accept to set wclk rate to 44.1k or 48kHz.
2650          */
2651         if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2652             rt5682->lrck[RT5682_AIF1] != CLK_44) {
2653                 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2654                         __func__, clk_name, CLK_44, CLK_48);
2655                 return 0;
2656         }
2657
2658         return rt5682->lrck[RT5682_AIF1];
2659 }
2660
2661 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2662                                    unsigned long *parent_rate)
2663 {
2664         struct rt5682_priv *rt5682 =
2665                 container_of(hw, struct rt5682_priv,
2666                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2667         const char * const clk_name = clk_hw_get_name(hw);
2668
2669         if (!rt5682_clk_check(rt5682))
2670                 return -EINVAL;
2671         /*
2672          * Only accept to set wclk rate to 44.1k or 48kHz.
2673          * It will force to 48kHz if not both.
2674          */
2675         if (rate != CLK_48 && rate != CLK_44) {
2676                 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2677                         __func__, clk_name, CLK_44, CLK_48);
2678                 rate = CLK_48;
2679         }
2680
2681         return rate;
2682 }
2683
2684 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2685                                 unsigned long parent_rate)
2686 {
2687         struct rt5682_priv *rt5682 =
2688                 container_of(hw, struct rt5682_priv,
2689                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2690         struct snd_soc_component *component;
2691         struct clk_hw *parent_hw;
2692         const char * const clk_name = clk_hw_get_name(hw);
2693         int pre_div;
2694         unsigned int clk_pll2_out;
2695
2696         if (!rt5682_clk_check(rt5682))
2697                 return -EINVAL;
2698
2699         component = rt5682->component;
2700
2701         /*
2702          * Whether the wclk's parent clk (mclk) exists or not, please ensure
2703          * it is fixed or set to 48MHz before setting wclk rate. It's a
2704          * temporary limitation. Only accept 48MHz clk as the clk provider.
2705          *
2706          * It will set the codec anyway by assuming mclk is 48MHz.
2707          */
2708         parent_hw = clk_hw_get_parent(hw);
2709         if (!parent_hw)
2710                 dev_warn(rt5682->i2c_dev,
2711                         "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2712                         CLK_PLL2_FIN);
2713
2714         if (parent_rate != CLK_PLL2_FIN)
2715                 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
2716                         clk_name, CLK_PLL2_FIN);
2717
2718         /*
2719          * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2720          * PLL2 is needed.
2721          */
2722         clk_pll2_out = rate * 512;
2723         rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2724                 CLK_PLL2_FIN, clk_pll2_out);
2725
2726         rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2727                 clk_pll2_out, SND_SOC_CLOCK_IN);
2728
2729         rt5682->lrck[RT5682_AIF1] = rate;
2730
2731         pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2732
2733         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2734                 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2735                 pre_div << RT5682_I2S_M_DIV_SFT |
2736                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2737
2738         return 0;
2739 }
2740
2741 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2742                                              unsigned long parent_rate)
2743 {
2744         struct rt5682_priv *rt5682 =
2745                 container_of(hw, struct rt5682_priv,
2746                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2747         unsigned int bclks_per_wclk;
2748
2749         regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);
2750
2751         switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2752         case RT5682_TDM_BCLK_MS1_256:
2753                 return parent_rate * 256;
2754         case RT5682_TDM_BCLK_MS1_128:
2755                 return parent_rate * 128;
2756         case RT5682_TDM_BCLK_MS1_64:
2757                 return parent_rate * 64;
2758         case RT5682_TDM_BCLK_MS1_32:
2759                 return parent_rate * 32;
2760         default:
2761                 return 0;
2762         }
2763 }
2764
2765 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2766                                             unsigned long parent_rate)
2767 {
2768         unsigned long factor;
2769
2770         factor = rate / parent_rate;
2771         if (factor < 64)
2772                 return 32;
2773         else if (factor < 128)
2774                 return 64;
2775         else if (factor < 256)
2776                 return 128;
2777         else
2778                 return 256;
2779 }
2780
2781 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2782                                    unsigned long *parent_rate)
2783 {
2784         struct rt5682_priv *rt5682 =
2785                 container_of(hw, struct rt5682_priv,
2786                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2787         unsigned long factor;
2788
2789         if (!*parent_rate || !rt5682_clk_check(rt5682))
2790                 return -EINVAL;
2791
2792         /*
2793          * BCLK rates are set as a multiplier of WCLK in HW.
2794          * We don't allow changing the parent WCLK. We just do
2795          * some rounding down based on the parent WCLK rate
2796          * and find the appropriate multiplier of BCLK to
2797          * get the rounded down BCLK value.
2798          */
2799         factor = rt5682_bclk_get_factor(rate, *parent_rate);
2800
2801         return *parent_rate * factor;
2802 }
2803
2804 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2805                                 unsigned long parent_rate)
2806 {
2807         struct rt5682_priv *rt5682 =
2808                 container_of(hw, struct rt5682_priv,
2809                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2810         struct snd_soc_component *component;
2811         struct snd_soc_dai *dai;
2812         unsigned long factor;
2813
2814         if (!rt5682_clk_check(rt5682))
2815                 return -EINVAL;
2816
2817         component = rt5682->component;
2818
2819         factor = rt5682_bclk_get_factor(rate, parent_rate);
2820
2821         for_each_component_dais(component, dai)
2822                 if (dai->id == RT5682_AIF1)
2823                         break;
2824         if (!dai) {
2825                 dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
2826                         RT5682_AIF1);
2827                 return -ENODEV;
2828         }
2829
2830         return rt5682_set_bclk1_ratio(dai, factor);
2831 }
2832
2833 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2834         [RT5682_DAI_WCLK_IDX] = {
2835                 .prepare = rt5682_wclk_prepare,
2836                 .unprepare = rt5682_wclk_unprepare,
2837                 .recalc_rate = rt5682_wclk_recalc_rate,
2838                 .round_rate = rt5682_wclk_round_rate,
2839                 .set_rate = rt5682_wclk_set_rate,
2840         },
2841         [RT5682_DAI_BCLK_IDX] = {
2842                 .recalc_rate = rt5682_bclk_recalc_rate,
2843                 .round_rate = rt5682_bclk_round_rate,
2844                 .set_rate = rt5682_bclk_set_rate,
2845         },
2846 };
2847
2848 int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
2849 {
2850         struct device *dev = rt5682->i2c_dev;
2851         struct rt5682_platform_data *pdata = &rt5682->pdata;
2852         struct clk_hw *dai_clk_hw;
2853         int i, ret;
2854
2855         for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2856                 struct clk_init_data init = { };
2857                 const struct clk_hw *parent;
2858
2859                 dai_clk_hw = &rt5682->dai_clks_hw[i];
2860
2861                 switch (i) {
2862                 case RT5682_DAI_WCLK_IDX:
2863                         /* Make MCLK the parent of WCLK */
2864                         if (rt5682->mclk) {
2865                                 parent = __clk_get_hw(rt5682->mclk);
2866                                 init.parent_hws = &parent;
2867                                 init.num_parents = 1;
2868                         }
2869                         break;
2870                 case RT5682_DAI_BCLK_IDX:
2871                         /* Make WCLK the parent of BCLK */
2872                         parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2873                         init.parent_hws = &parent;
2874                         init.num_parents = 1;
2875                         break;
2876                 default:
2877                         dev_err(dev, "Invalid clock index\n");
2878                         return -EINVAL;
2879                 }
2880
2881                 init.name = pdata->dai_clk_names[i];
2882                 init.ops = &rt5682_dai_clk_ops[i];
2883                 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2884                 dai_clk_hw->init = &init;
2885
2886                 ret = devm_clk_hw_register(dev, dai_clk_hw);
2887                 if (ret) {
2888                         dev_warn(dev, "Failed to register %s: %d\n",
2889                                  init.name, ret);
2890                         return ret;
2891                 }
2892
2893                 if (dev->of_node) {
2894                         devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2895                                                     dai_clk_hw);
2896                 } else {
2897                         ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2898                                                           init.name,
2899                                                           dev_name(dev));
2900                         if (ret)
2901                                 return ret;
2902                 }
2903         }
2904
2905         return 0;
2906 }
2907 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
2908 #endif /* CONFIG_COMMON_CLK */
2909
2910 static int rt5682_probe(struct snd_soc_component *component)
2911 {
2912         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2913         struct sdw_slave *slave;
2914         unsigned long time;
2915         struct snd_soc_dapm_context *dapm = &component->dapm;
2916
2917         rt5682->component = component;
2918
2919         if (rt5682->is_sdw) {
2920                 slave = rt5682->slave;
2921                 time = wait_for_completion_timeout(
2922                         &slave->initialization_complete,
2923                         msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2924                 if (!time) {
2925                         dev_err(&slave->dev, "Initialization not complete, timed out\n");
2926                         return -ETIMEDOUT;
2927                 }
2928         }
2929
2930         snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2931         snd_soc_dapm_disable_pin(dapm, "Vref2");
2932         snd_soc_dapm_sync(dapm);
2933         return 0;
2934 }
2935
2936 static void rt5682_remove(struct snd_soc_component *component)
2937 {
2938         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2939
2940         rt5682_reset(rt5682);
2941 }
2942
2943 #ifdef CONFIG_PM
2944 static int rt5682_suspend(struct snd_soc_component *component)
2945 {
2946         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2947         unsigned int val;
2948
2949         if (rt5682->is_sdw)
2950                 return 0;
2951
2952         cancel_delayed_work_sync(&rt5682->jack_detect_work);
2953         cancel_delayed_work_sync(&rt5682->jd_check_work);
2954         if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
2955                 val = snd_soc_component_read(component,
2956                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
2957
2958                 switch (val) {
2959                 case 0x1:
2960                         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2961                                 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2962                                 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
2963                         break;
2964                 case 0x2:
2965                         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2966                                 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2967                                 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
2968                         break;
2969                 default:
2970                         break;
2971                 }
2972
2973                 /* enter SAR ADC power saving mode */
2974                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2975                         RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
2976                         RT5682_SAR_SEL_MB1_MB2_MASK, 0);
2977                 usleep_range(5000, 6000);
2978                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2979                         RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2980                         RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
2981                 usleep_range(10000, 12000);
2982                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2983                         RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
2984                         RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
2985                 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
2986                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
2987         }
2988
2989         regcache_cache_only(rt5682->regmap, true);
2990         regcache_mark_dirty(rt5682->regmap);
2991         return 0;
2992 }
2993
2994 static int rt5682_resume(struct snd_soc_component *component)
2995 {
2996         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2997
2998         if (rt5682->is_sdw)
2999                 return 0;
3000
3001         regcache_cache_only(rt5682->regmap, false);
3002         regcache_sync(rt5682->regmap);
3003
3004         if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
3005                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3006                         RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
3007                         RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
3008                 usleep_range(5000, 6000);
3009                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
3010                         RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
3011                         RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
3012                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
3013                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
3014         }
3015
3016         rt5682->jack_type = 0;
3017         mod_delayed_work(system_power_efficient_wq,
3018                 &rt5682->jack_detect_work, msecs_to_jiffies(0));
3019
3020         return 0;
3021 }
3022 #else
3023 #define rt5682_suspend NULL
3024 #define rt5682_resume NULL
3025 #endif
3026
3027 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
3028         .hw_params = rt5682_hw_params,
3029         .set_fmt = rt5682_set_dai_fmt,
3030         .set_tdm_slot = rt5682_set_tdm_slot,
3031         .set_bclk_ratio = rt5682_set_bclk1_ratio,
3032 };
3033 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
3034
3035 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
3036         .hw_params = rt5682_hw_params,
3037         .set_fmt = rt5682_set_dai_fmt,
3038         .set_bclk_ratio = rt5682_set_bclk2_ratio,
3039 };
3040 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
3041
3042 const struct snd_soc_component_driver rt5682_soc_component_dev = {
3043         .probe = rt5682_probe,
3044         .remove = rt5682_remove,
3045         .suspend = rt5682_suspend,
3046         .resume = rt5682_resume,
3047         .set_bias_level = rt5682_set_bias_level,
3048         .controls = rt5682_snd_controls,
3049         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3050         .dapm_widgets = rt5682_dapm_widgets,
3051         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3052         .dapm_routes = rt5682_dapm_routes,
3053         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3054         .set_sysclk = rt5682_set_component_sysclk,
3055         .set_pll = rt5682_set_component_pll,
3056         .set_jack = rt5682_set_jack_detect,
3057         .use_pmdown_time        = 1,
3058         .endianness             = 1,
3059         .non_legacy_dai_naming  = 1,
3060 };
3061 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
3062
3063 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3064 {
3065
3066         device_property_read_u32(dev, "realtek,dmic1-data-pin",
3067                 &rt5682->pdata.dmic1_data_pin);
3068         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
3069                 &rt5682->pdata.dmic1_clk_pin);
3070         device_property_read_u32(dev, "realtek,jd-src",
3071                 &rt5682->pdata.jd_src);
3072         device_property_read_u32(dev, "realtek,btndet-delay",
3073                 &rt5682->pdata.btndet_delay);
3074         device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
3075                 &rt5682->pdata.dmic_clk_rate);
3076         device_property_read_u32(dev, "realtek,dmic-delay-ms",
3077                 &rt5682->pdata.dmic_delay);
3078
3079         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3080                 "realtek,ldo1-en-gpios", 0);
3081
3082         if (device_property_read_string_array(dev, "clock-output-names",
3083                                               rt5682->pdata.dai_clk_names,
3084                                               RT5682_DAI_NUM_CLKS) < 0)
3085                 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3086                          rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3087                          rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3088
3089         rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3090                 "realtek,dmic-clk-driving-high");
3091
3092         return 0;
3093 }
3094 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3095
3096 void rt5682_calibrate(struct rt5682_priv *rt5682)
3097 {
3098         int value, count;
3099
3100         mutex_lock(&rt5682->calibrate_mutex);
3101
3102         rt5682_reset(rt5682);
3103         regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3104         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3105         usleep_range(15000, 20000);
3106         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3107         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3108         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3109         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3110         regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3111         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3112         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3113         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3114         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3115         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3116         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3117         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3118         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3119         regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3120         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3121
3122         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3123
3124         for (count = 0; count < 60; count++) {
3125                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3126                 if (!(value & 0x8000))
3127                         break;
3128
3129                 usleep_range(10000, 10005);
3130         }
3131
3132         if (count >= 60)
3133                 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3134
3135         /* restore settings */
3136         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3137         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3138         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3139         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3140         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3141         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3142         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3143         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3144
3145         mutex_unlock(&rt5682->calibrate_mutex);
3146 }
3147 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3148
3149 MODULE_DESCRIPTION("ASoC RT5682 driver");
3150 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3151 MODULE_LICENSE("GPL v2");