1 // SPDX-License-Identifier: GPL-2.0-only
5 * ASoC Driver for Cirrus Logic CS42L51 codecs
7 * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
9 * Based on cs4270.c - Copyright (c) Freescale Semiconductor
12 * - Only I2C is support. Not SPI
13 * - master mode *NOT* supported
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <sound/core.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 #include <sound/initval.h>
23 #include <sound/pcm_params.h>
24 #include <sound/pcm.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
31 enum master_slave_mode {
37 static const char * const cs42l51_supply_names[] = {
44 struct cs42l51_private {
46 struct clk *mclk_handle;
47 unsigned int audio_mode; /* The mode (I2S or left-justified) */
48 enum master_slave_mode func;
49 struct regulator_bulk_data supplies[ARRAY_SIZE(cs42l51_supply_names)];
50 struct gpio_desc *reset_gpio;
51 struct regmap *regmap;
54 #define CS42L51_FORMATS ( \
55 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
56 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
57 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
58 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE)
60 static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
61 struct snd_ctl_elem_value *ucontrol)
63 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
64 unsigned long value = snd_soc_component_read(component, CS42L51_PCM_MIXER)&3;
69 ucontrol->value.enumerated.item[0] = 0;
71 /* same value : (L+R)/2 and (R+L)/2 */
74 ucontrol->value.enumerated.item[0] = 1;
77 ucontrol->value.enumerated.item[0] = 2;
84 #define CHAN_MIX_NORMAL 0x00
85 #define CHAN_MIX_BOTH 0x55
86 #define CHAN_MIX_SWAP 0xFF
88 static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol,
89 struct snd_ctl_elem_value *ucontrol)
91 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
94 switch (ucontrol->value.enumerated.item[0]) {
97 val = CHAN_MIX_NORMAL;
107 snd_soc_component_write(component, CS42L51_PCM_MIXER, val);
112 static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0);
113 static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
115 static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0);
117 static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0);
118 static const DECLARE_TLV_DB_SCALE(adc_boost_tlv, 2000, 2000, 0);
119 static const char *chan_mix[] = {
125 static const DECLARE_TLV_DB_SCALE(pga_tlv, -300, 50, 0);
126 static const DECLARE_TLV_DB_SCALE(adc_att_tlv, -9600, 100, 0);
128 static SOC_ENUM_SINGLE_EXT_DECL(cs42l51_chan_mix, chan_mix);
130 static const struct snd_kcontrol_new cs42l51_snd_controls[] = {
131 SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
132 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL,
133 0, 0x19, 0x7F, adc_pcm_tlv),
134 SOC_DOUBLE_R("PCM Playback Switch",
135 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1),
136 SOC_DOUBLE_R_SX_TLV("Analog Playback Volume",
137 CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL,
138 0, 0x34, 0xE4, aout_tlv),
139 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
140 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL,
141 0, 0x19, 0x7F, adc_pcm_tlv),
142 SOC_DOUBLE_R("ADC Mixer Switch",
143 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1),
144 SOC_DOUBLE_R_SX_TLV("ADC Attenuator Volume",
145 CS42L51_ADCA_ATT, CS42L51_ADCB_ATT,
146 0, 0xA0, 96, adc_att_tlv),
147 SOC_DOUBLE_R_SX_TLV("PGA Volume",
148 CS42L51_ALC_PGA_CTL, CS42L51_ALC_PGB_CTL,
149 0, 0x1A, 30, pga_tlv),
150 SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0),
151 SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0),
152 SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0),
153 SOC_SINGLE("Zero Cross Switch", CS42L51_DAC_CTL, 0, 0, 0),
154 SOC_DOUBLE_TLV("Mic Boost Volume",
155 CS42L51_MIC_CTL, 0, 1, 1, 0, boost_tlv),
156 SOC_DOUBLE_TLV("ADC Boost Volume",
157 CS42L51_MIC_CTL, 5, 6, 1, 0, adc_boost_tlv),
158 SOC_SINGLE_TLV("Bass Volume", CS42L51_TONE_CTL, 0, 0xf, 1, tone_tlv),
159 SOC_SINGLE_TLV("Treble Volume", CS42L51_TONE_CTL, 4, 0xf, 1, tone_tlv),
160 SOC_ENUM_EXT("PCM channel mixer",
162 cs42l51_get_chan_mix, cs42l51_set_chan_mix),
166 * to power down, one must:
167 * 1.) Enable the PDN bit
168 * 2.) enable power-down for the select channels
169 * 3.) disable the PDN bit.
171 static int cs42l51_pdn_event(struct snd_soc_dapm_widget *w,
172 struct snd_kcontrol *kcontrol, int event)
174 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
177 case SND_SOC_DAPM_PRE_PMD:
178 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
179 CS42L51_POWER_CTL1_PDN,
180 CS42L51_POWER_CTL1_PDN);
183 case SND_SOC_DAPM_POST_PMD:
184 snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
185 CS42L51_POWER_CTL1_PDN, 0);
192 static const char *cs42l51_dac_names[] = {"Direct PCM",
194 static SOC_ENUM_SINGLE_DECL(cs42l51_dac_mux_enum,
195 CS42L51_DAC_CTL, 6, cs42l51_dac_names);
196 static const struct snd_kcontrol_new cs42l51_dac_mux_controls =
197 SOC_DAPM_ENUM("Route", cs42l51_dac_mux_enum);
199 static const char *cs42l51_adcl_names[] = {"AIN1 Left", "AIN2 Left",
200 "MIC Left", "MIC+preamp Left"};
201 static SOC_ENUM_SINGLE_DECL(cs42l51_adcl_mux_enum,
202 CS42L51_ADC_INPUT, 4, cs42l51_adcl_names);
203 static const struct snd_kcontrol_new cs42l51_adcl_mux_controls =
204 SOC_DAPM_ENUM("Route", cs42l51_adcl_mux_enum);
206 static const char *cs42l51_adcr_names[] = {"AIN1 Right", "AIN2 Right",
207 "MIC Right", "MIC+preamp Right"};
208 static SOC_ENUM_SINGLE_DECL(cs42l51_adcr_mux_enum,
209 CS42L51_ADC_INPUT, 6, cs42l51_adcr_names);
210 static const struct snd_kcontrol_new cs42l51_adcr_mux_controls =
211 SOC_DAPM_ENUM("Route", cs42l51_adcr_mux_enum);
213 static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = {
214 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L51_MIC_POWER_CTL, 1, 1, NULL,
215 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
216 SND_SOC_DAPM_PGA_E("Left PGA", CS42L51_POWER_CTL1, 3, 1, NULL, 0,
217 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
218 SND_SOC_DAPM_PGA_E("Right PGA", CS42L51_POWER_CTL1, 4, 1, NULL, 0,
219 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
220 SND_SOC_DAPM_ADC_E("Left ADC", "Left HiFi Capture",
221 CS42L51_POWER_CTL1, 1, 1,
222 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
223 SND_SOC_DAPM_ADC_E("Right ADC", "Right HiFi Capture",
224 CS42L51_POWER_CTL1, 2, 1,
225 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
226 SND_SOC_DAPM_DAC_E("Left DAC", NULL, CS42L51_POWER_CTL1, 5, 1,
227 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
228 SND_SOC_DAPM_DAC_E("Right DAC", NULL, CS42L51_POWER_CTL1, 6, 1,
229 cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
232 SND_SOC_DAPM_INPUT("AIN1L"),
233 SND_SOC_DAPM_INPUT("AIN1R"),
234 SND_SOC_DAPM_INPUT("AIN2L"),
235 SND_SOC_DAPM_INPUT("AIN2R"),
236 SND_SOC_DAPM_INPUT("MICL"),
237 SND_SOC_DAPM_INPUT("MICR"),
239 SND_SOC_DAPM_MIXER("Mic Preamp Left",
240 CS42L51_MIC_POWER_CTL, 2, 1, NULL, 0),
241 SND_SOC_DAPM_MIXER("Mic Preamp Right",
242 CS42L51_MIC_POWER_CTL, 3, 1, NULL, 0),
245 SND_SOC_DAPM_OUTPUT("HPL"),
246 SND_SOC_DAPM_OUTPUT("HPR"),
249 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
250 &cs42l51_dac_mux_controls),
251 SND_SOC_DAPM_MUX("PGA-ADC Mux Left", SND_SOC_NOPM, 0, 0,
252 &cs42l51_adcl_mux_controls),
253 SND_SOC_DAPM_MUX("PGA-ADC Mux Right", SND_SOC_NOPM, 0, 0,
254 &cs42l51_adcr_mux_controls),
257 static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = {
258 SND_SOC_DAPM_CLOCK_SUPPLY("MCLK")
261 static const struct snd_soc_dapm_route cs42l51_routes[] = {
262 {"HPL", NULL, "Left DAC"},
263 {"HPR", NULL, "Right DAC"},
265 {"Right DAC", NULL, "DAC Mux"},
266 {"Left DAC", NULL, "DAC Mux"},
268 {"DAC Mux", "Direct PCM", "Playback"},
269 {"DAC Mux", "DSP PCM", "Playback"},
271 {"Left ADC", NULL, "Left PGA"},
272 {"Right ADC", NULL, "Right PGA"},
274 {"Mic Preamp Left", NULL, "MICL"},
275 {"Mic Preamp Right", NULL, "MICR"},
277 {"PGA-ADC Mux Left", "AIN1 Left", "AIN1L" },
278 {"PGA-ADC Mux Left", "AIN2 Left", "AIN2L" },
279 {"PGA-ADC Mux Left", "MIC Left", "MICL" },
280 {"PGA-ADC Mux Left", "MIC+preamp Left", "Mic Preamp Left" },
281 {"PGA-ADC Mux Right", "AIN1 Right", "AIN1R" },
282 {"PGA-ADC Mux Right", "AIN2 Right", "AIN2R" },
283 {"PGA-ADC Mux Right", "MIC Right", "MICR" },
284 {"PGA-ADC Mux Right", "MIC+preamp Right", "Mic Preamp Right" },
286 {"Left PGA", NULL, "PGA-ADC Mux Left"},
287 {"Right PGA", NULL, "PGA-ADC Mux Right"},
290 static int cs42l51_set_dai_fmt(struct snd_soc_dai *codec_dai,
293 struct snd_soc_component *component = codec_dai->component;
294 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
296 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
297 case SND_SOC_DAIFMT_I2S:
298 case SND_SOC_DAIFMT_LEFT_J:
299 case SND_SOC_DAIFMT_RIGHT_J:
300 cs42l51->audio_mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
303 dev_err(component->dev, "invalid DAI format\n");
307 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
308 case SND_SOC_DAIFMT_CBM_CFM:
309 cs42l51->func = MODE_MASTER;
311 case SND_SOC_DAIFMT_CBS_CFS:
312 cs42l51->func = MODE_SLAVE_AUTO;
315 dev_err(component->dev, "Unknown master/slave configuration\n");
322 struct cs42l51_ratios {
324 unsigned char speed_mode;
328 static struct cs42l51_ratios slave_ratios[] = {
329 { 512, CS42L51_QSM_MODE, 0 }, { 768, CS42L51_QSM_MODE, 0 },
330 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
331 { 2048, CS42L51_QSM_MODE, 0 }, { 3072, CS42L51_QSM_MODE, 0 },
332 { 256, CS42L51_HSM_MODE, 0 }, { 384, CS42L51_HSM_MODE, 0 },
333 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
334 { 1024, CS42L51_HSM_MODE, 0 }, { 1536, CS42L51_HSM_MODE, 0 },
335 { 128, CS42L51_SSM_MODE, 0 }, { 192, CS42L51_SSM_MODE, 0 },
336 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
337 { 512, CS42L51_SSM_MODE, 0 }, { 768, CS42L51_SSM_MODE, 0 },
338 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
339 { 256, CS42L51_DSM_MODE, 0 }, { 384, CS42L51_DSM_MODE, 0 },
342 static struct cs42l51_ratios slave_auto_ratios[] = {
343 { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
344 { 2048, CS42L51_QSM_MODE, 1 }, { 3072, CS42L51_QSM_MODE, 1 },
345 { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
346 { 1024, CS42L51_HSM_MODE, 1 }, { 1536, CS42L51_HSM_MODE, 1 },
347 { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
348 { 512, CS42L51_SSM_MODE, 1 }, { 768, CS42L51_SSM_MODE, 1 },
349 { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
350 { 256, CS42L51_DSM_MODE, 1 }, { 384, CS42L51_DSM_MODE, 1 },
354 * Master mode mclk/fs ratios.
355 * Recommended configurations are SSM for 4-50khz and DSM for 50-100kHz ranges
356 * The table below provides support of following ratios:
357 * 128: SSM (%128) with div2 disabled
358 * 256: SSM (%128) with div2 enabled
359 * In both cases, if sampling rate is above 50kHz, SSM is overridden
360 * with DSM (%128) configuration
362 static struct cs42l51_ratios master_ratios[] = {
363 { 128, CS42L51_SSM_MODE, 0 }, { 256, CS42L51_SSM_MODE, 1 },
366 static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai,
367 int clk_id, unsigned int freq, int dir)
369 struct snd_soc_component *component = codec_dai->component;
370 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
372 cs42l51->mclk = freq;
376 static int cs42l51_hw_params(struct snd_pcm_substream *substream,
377 struct snd_pcm_hw_params *params,
378 struct snd_soc_dai *dai)
380 struct snd_soc_component *component = dai->component;
381 struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
386 struct cs42l51_ratios *ratios = NULL;
388 int intf_ctl, power_ctl, fmt, mode;
390 switch (cs42l51->func) {
392 ratios = master_ratios;
393 nr_ratios = ARRAY_SIZE(master_ratios);
396 ratios = slave_ratios;
397 nr_ratios = ARRAY_SIZE(slave_ratios);
399 case MODE_SLAVE_AUTO:
400 ratios = slave_auto_ratios;
401 nr_ratios = ARRAY_SIZE(slave_auto_ratios);
405 /* Figure out which MCLK/LRCK ratio to use */
406 rate = params_rate(params); /* Sampling rate, in Hz */
407 ratio = cs42l51->mclk / rate; /* MCLK/LRCK ratio */
408 for (i = 0; i < nr_ratios; i++) {
409 if (ratios[i].ratio == ratio)
413 if (i == nr_ratios) {
414 /* We did not find a matching ratio */
415 dev_err(component->dev, "could not find matching ratio\n");
419 intf_ctl = snd_soc_component_read(component, CS42L51_INTF_CTL);
420 power_ctl = snd_soc_component_read(component, CS42L51_MIC_POWER_CTL);
422 intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S
423 | CS42L51_INTF_CTL_DAC_FORMAT(7));
424 power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3)
425 | CS42L51_MIC_POWER_CTL_MCLK_DIV2);
427 switch (cs42l51->func) {
429 intf_ctl |= CS42L51_INTF_CTL_MASTER;
430 mode = ratios[i].speed_mode;
431 /* Force DSM mode if sampling rate is above 50kHz */
433 mode = CS42L51_DSM_MODE;
434 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(mode);
436 * Auto detect mode is not applicable for master mode and has to
437 * be disabled. Otherwise SPEED[1:0] bits will be ignored.
439 power_ctl &= ~CS42L51_MIC_POWER_CTL_AUTO;
442 power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(ratios[i].speed_mode);
444 case MODE_SLAVE_AUTO:
445 power_ctl |= CS42L51_MIC_POWER_CTL_AUTO;
449 switch (cs42l51->audio_mode) {
450 case SND_SOC_DAIFMT_I2S:
451 intf_ctl |= CS42L51_INTF_CTL_ADC_I2S;
452 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_I2S);
454 case SND_SOC_DAIFMT_LEFT_J:
455 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_LJ24);
457 case SND_SOC_DAIFMT_RIGHT_J:
458 switch (params_width(params)) {
460 fmt = CS42L51_DAC_DIF_RJ16;
463 fmt = CS42L51_DAC_DIF_RJ18;
466 fmt = CS42L51_DAC_DIF_RJ20;
469 fmt = CS42L51_DAC_DIF_RJ24;
472 dev_err(component->dev, "unknown format\n");
475 intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(fmt);
478 dev_err(component->dev, "unknown format\n");
483 power_ctl |= CS42L51_MIC_POWER_CTL_MCLK_DIV2;
485 ret = snd_soc_component_write(component, CS42L51_INTF_CTL, intf_ctl);
489 ret = snd_soc_component_write(component, CS42L51_MIC_POWER_CTL, power_ctl);
496 static int cs42l51_dai_mute(struct snd_soc_dai *dai, int mute, int direction)
498 struct snd_soc_component *component = dai->component;
500 int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE;
502 reg = snd_soc_component_read(component, CS42L51_DAC_OUT_CTL);
509 return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg);
512 static int cs42l51_of_xlate_dai_id(struct snd_soc_component *component,
513 struct device_node *endpoint)
515 /* return dai id 0, whatever the endpoint index */
519 static const struct snd_soc_dai_ops cs42l51_dai_ops = {
520 .hw_params = cs42l51_hw_params,
521 .set_sysclk = cs42l51_set_dai_sysclk,
522 .set_fmt = cs42l51_set_dai_fmt,
523 .mute_stream = cs42l51_dai_mute,
524 .no_capture_mute = 1,
527 static struct snd_soc_dai_driver cs42l51_dai = {
528 .name = "cs42l51-hifi",
530 .stream_name = "Playback",
533 .rates = SNDRV_PCM_RATE_8000_96000,
534 .formats = CS42L51_FORMATS,
537 .stream_name = "Capture",
540 .rates = SNDRV_PCM_RATE_8000_96000,
541 .formats = CS42L51_FORMATS,
543 .ops = &cs42l51_dai_ops,
546 static int cs42l51_component_probe(struct snd_soc_component *component)
549 struct snd_soc_dapm_context *dapm;
550 struct cs42l51_private *cs42l51;
552 cs42l51 = snd_soc_component_get_drvdata(component);
553 dapm = snd_soc_component_get_dapm(component);
555 if (cs42l51->mclk_handle)
556 snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1);
560 * - Use signal processor
562 * - vol changes immediate
565 reg = CS42L51_DAC_CTL_DATA_SEL(1)
566 | CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
567 ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg);
574 static const struct snd_soc_component_driver soc_component_device_cs42l51 = {
575 .probe = cs42l51_component_probe,
576 .controls = cs42l51_snd_controls,
577 .num_controls = ARRAY_SIZE(cs42l51_snd_controls),
578 .dapm_widgets = cs42l51_dapm_widgets,
579 .num_dapm_widgets = ARRAY_SIZE(cs42l51_dapm_widgets),
580 .dapm_routes = cs42l51_routes,
581 .num_dapm_routes = ARRAY_SIZE(cs42l51_routes),
582 .of_xlate_dai_id = cs42l51_of_xlate_dai_id,
584 .use_pmdown_time = 1,
586 .non_legacy_dai_naming = 1,
589 static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg)
592 case CS42L51_POWER_CTL1:
593 case CS42L51_MIC_POWER_CTL:
594 case CS42L51_INTF_CTL:
595 case CS42L51_MIC_CTL:
596 case CS42L51_ADC_CTL:
597 case CS42L51_ADC_INPUT:
598 case CS42L51_DAC_OUT_CTL:
599 case CS42L51_DAC_CTL:
600 case CS42L51_ALC_PGA_CTL:
601 case CS42L51_ALC_PGB_CTL:
602 case CS42L51_ADCA_ATT:
603 case CS42L51_ADCB_ATT:
604 case CS42L51_ADCA_VOL:
605 case CS42L51_ADCB_VOL:
606 case CS42L51_PCMA_VOL:
607 case CS42L51_PCMB_VOL:
608 case CS42L51_BEEP_FREQ:
609 case CS42L51_BEEP_VOL:
610 case CS42L51_BEEP_CONF:
611 case CS42L51_TONE_CTL:
612 case CS42L51_AOUTA_VOL:
613 case CS42L51_AOUTB_VOL:
614 case CS42L51_PCM_MIXER:
615 case CS42L51_LIMIT_THRES_DIS:
616 case CS42L51_LIMIT_REL:
617 case CS42L51_LIMIT_ATT:
619 case CS42L51_ALC_REL:
620 case CS42L51_ALC_THRES:
621 case CS42L51_NOISE_CONF:
622 case CS42L51_CHARGE_FREQ:
629 static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg)
639 static bool cs42l51_readable_reg(struct device *dev, unsigned int reg)
642 case CS42L51_CHIP_REV_ID:
643 case CS42L51_POWER_CTL1:
644 case CS42L51_MIC_POWER_CTL:
645 case CS42L51_INTF_CTL:
646 case CS42L51_MIC_CTL:
647 case CS42L51_ADC_CTL:
648 case CS42L51_ADC_INPUT:
649 case CS42L51_DAC_OUT_CTL:
650 case CS42L51_DAC_CTL:
651 case CS42L51_ALC_PGA_CTL:
652 case CS42L51_ALC_PGB_CTL:
653 case CS42L51_ADCA_ATT:
654 case CS42L51_ADCB_ATT:
655 case CS42L51_ADCA_VOL:
656 case CS42L51_ADCB_VOL:
657 case CS42L51_PCMA_VOL:
658 case CS42L51_PCMB_VOL:
659 case CS42L51_BEEP_FREQ:
660 case CS42L51_BEEP_VOL:
661 case CS42L51_BEEP_CONF:
662 case CS42L51_TONE_CTL:
663 case CS42L51_AOUTA_VOL:
664 case CS42L51_AOUTB_VOL:
665 case CS42L51_PCM_MIXER:
666 case CS42L51_LIMIT_THRES_DIS:
667 case CS42L51_LIMIT_REL:
668 case CS42L51_LIMIT_ATT:
670 case CS42L51_ALC_REL:
671 case CS42L51_ALC_THRES:
672 case CS42L51_NOISE_CONF:
674 case CS42L51_CHARGE_FREQ:
681 const struct regmap_config cs42l51_regmap = {
685 .use_single_write = true,
686 .readable_reg = cs42l51_readable_reg,
687 .volatile_reg = cs42l51_volatile_reg,
688 .writeable_reg = cs42l51_writeable_reg,
689 .max_register = CS42L51_CHARGE_FREQ,
690 .cache_type = REGCACHE_RBTREE,
692 EXPORT_SYMBOL_GPL(cs42l51_regmap);
694 int cs42l51_probe(struct device *dev, struct regmap *regmap)
696 struct cs42l51_private *cs42l51;
701 return PTR_ERR(regmap);
703 cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private),
708 dev_set_drvdata(dev, cs42l51);
709 cs42l51->regmap = regmap;
711 cs42l51->mclk_handle = devm_clk_get(dev, "MCLK");
712 if (IS_ERR(cs42l51->mclk_handle)) {
713 if (PTR_ERR(cs42l51->mclk_handle) != -ENOENT)
714 return PTR_ERR(cs42l51->mclk_handle);
715 cs42l51->mclk_handle = NULL;
718 for (i = 0; i < ARRAY_SIZE(cs42l51->supplies); i++)
719 cs42l51->supplies[i].supply = cs42l51_supply_names[i];
721 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs42l51->supplies),
724 dev_err(dev, "Failed to request supplies: %d\n", ret);
728 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l51->supplies),
731 dev_err(dev, "Failed to enable supplies: %d\n", ret);
735 cs42l51->reset_gpio = devm_gpiod_get_optional(dev, "reset",
737 if (IS_ERR(cs42l51->reset_gpio))
738 return PTR_ERR(cs42l51->reset_gpio);
740 if (cs42l51->reset_gpio) {
741 dev_dbg(dev, "Release reset gpio\n");
742 gpiod_set_value_cansleep(cs42l51->reset_gpio, 0);
746 /* Verify that we have a CS42L51 */
747 ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val);
749 dev_err(dev, "failed to read I2C\n");
753 if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
754 (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
755 dev_err(dev, "Invalid chip id: %x\n", val);
759 dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n",
760 val & CS42L51_CHIP_REV_MASK);
762 ret = devm_snd_soc_register_component(dev,
763 &soc_component_device_cs42l51, &cs42l51_dai, 1);
770 regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
774 EXPORT_SYMBOL_GPL(cs42l51_probe);
776 int cs42l51_remove(struct device *dev)
778 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
780 gpiod_set_value_cansleep(cs42l51->reset_gpio, 1);
782 return regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
785 EXPORT_SYMBOL_GPL(cs42l51_remove);
787 int __maybe_unused cs42l51_suspend(struct device *dev)
789 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
791 regcache_cache_only(cs42l51->regmap, true);
792 regcache_mark_dirty(cs42l51->regmap);
796 EXPORT_SYMBOL_GPL(cs42l51_suspend);
798 int __maybe_unused cs42l51_resume(struct device *dev)
800 struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
802 regcache_cache_only(cs42l51->regmap, false);
804 return regcache_sync(cs42l51->regmap);
806 EXPORT_SYMBOL_GPL(cs42l51_resume);
808 const struct of_device_id cs42l51_of_match[] = {
809 { .compatible = "cirrus,cs42l51", },
812 MODULE_DEVICE_TABLE(of, cs42l51_of_match);
813 EXPORT_SYMBOL_GPL(cs42l51_of_match);
815 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
816 MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
817 MODULE_LICENSE("GPL");