1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
14 #include <sound/pcm.h>
15 #include <sound/soc.h>
16 #include <sound/soc-acpi.h>
17 #include <sound/soc-dai.h>
19 #include "chip_offset_byte.h"
23 #define ACP63_DEV 0x63
25 #define DMIC_INSTANCE 0x00
26 #define I2S_SP_INSTANCE 0x01
27 #define I2S_BT_INSTANCE 0x02
28 #define I2S_HS_INSTANCE 0x03
30 #define MEM_WINDOW_START 0x4080000
32 #define ACP_I2S_REG_START 0x1242400
33 #define ACP_I2S_REG_END 0x1242810
34 #define ACP3x_I2STDM_REG_START 0x1242400
35 #define ACP3x_I2STDM_REG_END 0x1242410
36 #define ACP3x_BT_TDM_REG_START 0x1242800
37 #define ACP3x_BT_TDM_REG_END 0x1242810
39 #define THRESHOLD(bit, base) ((bit) + (base))
40 #define I2S_RX_THRESHOLD(base) THRESHOLD(7, base)
41 #define I2S_TX_THRESHOLD(base) THRESHOLD(8, base)
42 #define BT_TX_THRESHOLD(base) THRESHOLD(6, base)
43 #define BT_RX_THRESHOLD(base) THRESHOLD(5, base)
44 #define HS_TX_THRESHOLD(base) THRESHOLD(4, base)
45 #define HS_RX_THRESHOLD(base) THRESHOLD(3, base)
47 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
48 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
49 #define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
50 #define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
51 #define ACP_SRAM_PDM_PTE_OFFSET 0x400
52 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x500
53 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x600
54 #define PAGE_SIZE_4K_ENABLE 0x2
56 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
57 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
58 #define I2S_BT_TX_MEM_WINDOW_START 0x4040000
59 #define I2S_BT_RX_MEM_WINDOW_START 0x4060000
60 #define I2S_HS_TX_MEM_WINDOW_START 0x40A0000
61 #define I2S_HS_RX_MEM_WINDOW_START 0x40C0000
63 #define SP_PB_FIFO_ADDR_OFFSET 0x500
64 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
65 #define BT_PB_FIFO_ADDR_OFFSET 0x900
66 #define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
67 #define HS_PB_FIFO_ADDR_OFFSET 0xD00
68 #define HS_CAPT_FIFO_ADDR_OFFSET 0xF00
69 #define PLAYBACK_MIN_NUM_PERIODS 2
70 #define PLAYBACK_MAX_NUM_PERIODS 8
71 #define PLAYBACK_MAX_PERIOD_SIZE 8192
72 #define PLAYBACK_MIN_PERIOD_SIZE 1024
73 #define CAPTURE_MIN_NUM_PERIODS 2
74 #define CAPTURE_MAX_NUM_PERIODS 8
75 #define CAPTURE_MAX_PERIOD_SIZE 8192
76 #define CAPTURE_MIN_PERIOD_SIZE 1024
78 #define MAX_BUFFER 65536
79 #define MIN_BUFFER MAX_BUFFER
80 #define FIFO_SIZE 0x100
84 #define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
86 #define ACP_MAX_STREAM 8
91 #define SLOT_WIDTH_8 0x8
92 #define SLOT_WIDTH_16 0x10
93 #define SLOT_WIDTH_24 0x18
94 #define SLOT_WIDTH_32 0x20
96 #define ACP6X_PGFSM_CONTROL 0x1024
97 #define ACP6X_PGFSM_STATUS 0x1028
99 #define ACP63_PGFSM_CONTROL ACP6X_PGFSM_CONTROL
100 #define ACP63_PGFSM_STATUS ACP6X_PGFSM_STATUS
102 #define ACP_SOFT_RST_DONE_MASK 0x00010001
104 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
105 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
106 #define ACP_PGFSM_STATUS_MASK 0x03
107 #define ACP_POWERED_ON 0x00
108 #define ACP_POWER_ON_IN_PROGRESS 0x01
109 #define ACP_POWERED_OFF 0x02
110 #define ACP_POWER_OFF_IN_PROGRESS 0x03
112 #define ACP_ERROR_MASK 0x20000000
113 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xffffffff
115 #define ACP_TIMEOUT 500
117 #define ACP_SUSPEND_DELAY_MS 2000
119 #define PDM_DMA_STAT 0x10
120 #define PDM_DMA_INTR_MASK 0x10000
121 #define PDM_DEC_64 0x2
122 #define PDM_CLK_FREQ_MASK 0x07
123 #define PDM_MISC_CTRL_MASK 0x10
124 #define PDM_ENABLE 0x01
125 #define PDM_DISABLE 0x00
126 #define DMA_EN_MASK 0x02
128 #define PDM_TIMEOUT 1000
129 #define ACP_REGION2_OFFSET 0x02000000
131 struct acp_chip_info {
132 char *name; /* Platform name */
133 unsigned int acp_rev; /* ACP Revision id */
134 void __iomem *base; /* ACP memory PCI base */
135 struct platform_device *chip_pdev;
139 struct list_head list;
140 struct snd_pcm_substream *substream;
151 struct acp_resource {
157 u32 i2s_pin_cfg_offset;
159 u64 scratch_reg_offset;
163 struct acp_dev_data {
166 void __iomem *acp_base;
167 unsigned int i2s_irq;
170 /* SOC specific dais */
171 struct snd_soc_dai_driver *dai_driver;
174 struct list_head stream_list;
177 struct snd_soc_acpi_mach *machines;
178 struct platform_device *mach_dev;
183 struct acp_resource *rsrc;
187 u32 xfer_tx_resolution[3];
188 u32 xfer_rx_resolution[3];
191 union acp_i2stdm_mstrclkgen {
193 u32 i2stdm_master_mode : 1;
194 u32 i2stdm_format_mode : 1;
195 u32 i2stdm_lrclk_div_val : 9;
196 u32 i2stdm_bclk_div_val : 11;
202 extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
203 extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
205 int acp_platform_register(struct device *dev);
206 int acp_platform_unregister(struct device *dev);
208 int acp_machine_select(struct acp_dev_data *adata);
210 int smn_read(struct pci_dev *dev, u32 smn_addr);
211 int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data);
213 int acp_init(struct acp_chip_info *chip);
214 int acp_deinit(void __iomem *base);
215 void acp_enable_interrupts(struct acp_dev_data *adata);
216 void acp_disable_interrupts(struct acp_dev_data *adata);
217 /* Machine configuration */
218 int snd_amd_acp_find_config(struct pci_dev *pci);
220 void config_pte_for_stream(struct acp_dev_data *adata, struct acp_stream *stream);
221 void config_acp_dma(struct acp_dev_data *adata, struct acp_stream *stream, int size);
222 void restore_acp_pdm_params(struct snd_pcm_substream *substream,
223 struct acp_dev_data *adata);
225 int restore_acp_i2s_params(struct snd_pcm_substream *substream,
226 struct acp_dev_data *adata, struct acp_stream *stream);
228 static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
230 u64 byte_count = 0, low = 0, high = 0;
232 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
234 case I2S_BT_INSTANCE:
235 high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
236 low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
238 case I2S_SP_INSTANCE:
239 high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
240 low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
242 case I2S_HS_INSTANCE:
243 high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
244 low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
247 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
248 goto POINTER_RETURN_BYTES;
252 case I2S_BT_INSTANCE:
253 high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
254 low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
256 case I2S_SP_INSTANCE:
257 high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
258 low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
260 case I2S_HS_INSTANCE:
261 high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
262 low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
265 high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
266 low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
269 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
270 goto POINTER_RETURN_BYTES;
273 /* Get 64 bit value from two 32 bit registers */
274 byte_count = (high << 32) | low;
276 POINTER_RETURN_BYTES:
280 static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
282 union acp_i2stdm_mstrclkgen mclkgen;
286 case I2S_SP_INSTANCE:
287 master_reg = ACP_I2STDM0_MSTRCLKGEN;
289 case I2S_BT_INSTANCE:
290 master_reg = ACP_I2STDM1_MSTRCLKGEN;
292 case I2S_HS_INSTANCE:
293 master_reg = ACP_I2STDM2_MSTRCLKGEN;
296 master_reg = ACP_I2STDM0_MSTRCLKGEN;
300 mclkgen.bits.i2stdm_master_mode = 0x1;
301 mclkgen.bits.i2stdm_format_mode = 0x00;
303 mclkgen.bits.i2stdm_bclk_div_val = adata->bclk_div;
304 mclkgen.bits.i2stdm_lrclk_div_val = adata->lrclk_div;
305 writel(mclkgen.u32_all, adata->acp_base + master_reg);