Merge https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf
[sfrench/cifs-2.6.git] / sound / pci / hda / patch_hdmi.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *
4  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
5  *
6  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7  *  Copyright (c) 2006 ATI Technologies Inc.
8  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
9  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11  *
12  *  Authors:
13  *                      Wu Fengguang <wfg@linux.intel.com>
14  *
15  *  Maintained by:
16  *                      Wu Fengguang <wfg@linux.intel.com>
17  */
18
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
34 #include "hda_jack.h"
35 #include "hda_controller.h"
36
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41 static bool enable_acomp = true;
42 module_param(enable_acomp, bool, 0444);
43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45 static bool enable_silent_stream =
46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47 module_param(enable_silent_stream, bool, 0644);
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50 static bool enable_all_pins;
51 module_param(enable_all_pins, bool, 0444);
52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
53
54 struct hdmi_spec_per_cvt {
55         hda_nid_t cvt_nid;
56         int assigned;
57         unsigned int channels_min;
58         unsigned int channels_max;
59         u32 rates;
60         u64 formats;
61         unsigned int maxbps;
62 };
63
64 /* max. connections to a widget */
65 #define HDA_MAX_CONNECTIONS     32
66
67 struct hdmi_spec_per_pin {
68         hda_nid_t pin_nid;
69         int dev_id;
70         /* pin idx, different device entries on the same pin use the same idx */
71         int pin_nid_idx;
72         int num_mux_nids;
73         hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
74         int mux_idx;
75         hda_nid_t cvt_nid;
76
77         struct hda_codec *codec;
78         struct hdmi_eld sink_eld;
79         struct mutex lock;
80         struct delayed_work work;
81         struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
82         int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
83         int repoll_count;
84         bool setup; /* the stream has been set up by prepare callback */
85         bool silent_stream;
86         int channels; /* current number of channels */
87         bool non_pcm;
88         bool chmap_set;         /* channel-map override by ALSA API? */
89         unsigned char chmap[8]; /* ALSA API channel-map */
90 #ifdef CONFIG_SND_PROC_FS
91         struct snd_info_entry *proc_entry;
92 #endif
93 };
94
95 /* operations used by generic code that can be overridden by patches */
96 struct hdmi_ops {
97         int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
98                            int dev_id, unsigned char *buf, int *eld_size);
99
100         void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
101                                     int dev_id,
102                                     int ca, int active_channels, int conn_type);
103
104         /* enable/disable HBR (HD passthrough) */
105         int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
106                              int dev_id, bool hbr);
107
108         int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
109                             hda_nid_t pin_nid, int dev_id, u32 stream_tag,
110                             int format);
111
112         void (*pin_cvt_fixup)(struct hda_codec *codec,
113                               struct hdmi_spec_per_pin *per_pin,
114                               hda_nid_t cvt_nid);
115 };
116
117 struct hdmi_pcm {
118         struct hda_pcm *pcm;
119         struct snd_jack *jack;
120         struct snd_kcontrol *eld_ctl;
121 };
122
123 enum {
124         SILENT_STREAM_OFF = 0,
125         SILENT_STREAM_KAE,      /* use standard HDA Keep-Alive */
126         SILENT_STREAM_I915,     /* Intel i915 extension */
127 };
128
129 struct hdmi_spec {
130         struct hda_codec *codec;
131         int num_cvts;
132         struct snd_array cvts; /* struct hdmi_spec_per_cvt */
133         hda_nid_t cvt_nids[4]; /* only for haswell fix */
134
135         /*
136          * num_pins is the number of virtual pins
137          * for example, there are 3 pins, and each pin
138          * has 4 device entries, then the num_pins is 12
139          */
140         int num_pins;
141         /*
142          * num_nids is the number of real pins
143          * In the above example, num_nids is 3
144          */
145         int num_nids;
146         /*
147          * dev_num is the number of device entries
148          * on each pin.
149          * In the above example, dev_num is 4
150          */
151         int dev_num;
152         struct snd_array pins; /* struct hdmi_spec_per_pin */
153         struct hdmi_pcm pcm_rec[16];
154         struct mutex pcm_lock;
155         struct mutex bind_lock; /* for audio component binding */
156         /* pcm_bitmap means which pcms have been assigned to pins*/
157         unsigned long pcm_bitmap;
158         int pcm_used;   /* counter of pcm_rec[] */
159         /* bitmap shows whether the pcm is opened in user space
160          * bit 0 means the first playback PCM (PCM3);
161          * bit 1 means the second playback PCM, and so on.
162          */
163         unsigned long pcm_in_use;
164
165         struct hdmi_eld temp_eld;
166         struct hdmi_ops ops;
167
168         bool dyn_pin_out;
169         bool dyn_pcm_assign;
170         bool dyn_pcm_no_legacy;
171         /* hdmi interrupt trigger control flag for Nvidia codec */
172         bool hdmi_intr_trig_ctrl;
173         bool intel_hsw_fixup;   /* apply Intel platform-specific fixups */
174         /*
175          * Non-generic VIA/NVIDIA specific
176          */
177         struct hda_multi_out multiout;
178         struct hda_pcm_stream pcm_playback;
179
180         bool use_acomp_notifier; /* use eld_notify callback for hotplug */
181         bool acomp_registered; /* audio component registered in this driver */
182         bool force_connect; /* force connectivity */
183         struct drm_audio_component_audio_ops drm_audio_ops;
184         int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
185
186         struct hdac_chmap chmap;
187         hda_nid_t vendor_nid;
188         const int *port_map;
189         int port_num;
190         int silent_stream_type;
191 };
192
193 #ifdef CONFIG_SND_HDA_COMPONENT
194 static inline bool codec_has_acomp(struct hda_codec *codec)
195 {
196         struct hdmi_spec *spec = codec->spec;
197         return spec->use_acomp_notifier;
198 }
199 #else
200 #define codec_has_acomp(codec)  false
201 #endif
202
203 struct hdmi_audio_infoframe {
204         u8 type; /* 0x84 */
205         u8 ver;  /* 0x01 */
206         u8 len;  /* 0x0a */
207
208         u8 checksum;
209
210         u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
211         u8 SS01_SF24;
212         u8 CXT04;
213         u8 CA;
214         u8 LFEPBL01_LSV36_DM_INH7;
215 };
216
217 struct dp_audio_infoframe {
218         u8 type; /* 0x84 */
219         u8 len;  /* 0x1b */
220         u8 ver;  /* 0x11 << 2 */
221
222         u8 CC02_CT47;   /* match with HDMI infoframe from this on */
223         u8 SS01_SF24;
224         u8 CXT04;
225         u8 CA;
226         u8 LFEPBL01_LSV36_DM_INH7;
227 };
228
229 union audio_infoframe {
230         struct hdmi_audio_infoframe hdmi;
231         struct dp_audio_infoframe dp;
232         u8 bytes[0];
233 };
234
235 /*
236  * HDMI routines
237  */
238
239 #define get_pin(spec, idx) \
240         ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
241 #define get_cvt(spec, idx) \
242         ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
243 /* obtain hdmi_pcm object assigned to idx */
244 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
245 /* obtain hda_pcm object assigned to idx */
246 #define get_pcm_rec(spec, idx)  (get_hdmi_pcm(spec, idx)->pcm)
247
248 static int pin_id_to_pin_index(struct hda_codec *codec,
249                                hda_nid_t pin_nid, int dev_id)
250 {
251         struct hdmi_spec *spec = codec->spec;
252         int pin_idx;
253         struct hdmi_spec_per_pin *per_pin;
254
255         /*
256          * (dev_id == -1) means it is NON-MST pin
257          * return the first virtual pin on this port
258          */
259         if (dev_id == -1)
260                 dev_id = 0;
261
262         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
263                 per_pin = get_pin(spec, pin_idx);
264                 if ((per_pin->pin_nid == pin_nid) &&
265                         (per_pin->dev_id == dev_id))
266                         return pin_idx;
267         }
268
269         codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
270         return -EINVAL;
271 }
272
273 static int hinfo_to_pcm_index(struct hda_codec *codec,
274                         struct hda_pcm_stream *hinfo)
275 {
276         struct hdmi_spec *spec = codec->spec;
277         int pcm_idx;
278
279         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
280                 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
281                         return pcm_idx;
282
283         codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
284         return -EINVAL;
285 }
286
287 static int hinfo_to_pin_index(struct hda_codec *codec,
288                               struct hda_pcm_stream *hinfo)
289 {
290         struct hdmi_spec *spec = codec->spec;
291         struct hdmi_spec_per_pin *per_pin;
292         int pin_idx;
293
294         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
295                 per_pin = get_pin(spec, pin_idx);
296                 if (per_pin->pcm &&
297                         per_pin->pcm->pcm->stream == hinfo)
298                         return pin_idx;
299         }
300
301         codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
302                   hinfo_to_pcm_index(codec, hinfo));
303         return -EINVAL;
304 }
305
306 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
307                                                 int pcm_idx)
308 {
309         int i;
310         struct hdmi_spec_per_pin *per_pin;
311
312         for (i = 0; i < spec->num_pins; i++) {
313                 per_pin = get_pin(spec, i);
314                 if (per_pin->pcm_idx == pcm_idx)
315                         return per_pin;
316         }
317         return NULL;
318 }
319
320 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
321 {
322         struct hdmi_spec *spec = codec->spec;
323         int cvt_idx;
324
325         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
326                 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
327                         return cvt_idx;
328
329         codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
330         return -EINVAL;
331 }
332
333 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
334                         struct snd_ctl_elem_info *uinfo)
335 {
336         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
337         struct hdmi_spec *spec = codec->spec;
338         struct hdmi_spec_per_pin *per_pin;
339         struct hdmi_eld *eld;
340         int pcm_idx;
341
342         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
343
344         pcm_idx = kcontrol->private_value;
345         mutex_lock(&spec->pcm_lock);
346         per_pin = pcm_idx_to_pin(spec, pcm_idx);
347         if (!per_pin) {
348                 /* no pin is bound to the pcm */
349                 uinfo->count = 0;
350                 goto unlock;
351         }
352         eld = &per_pin->sink_eld;
353         uinfo->count = eld->eld_valid ? eld->eld_size : 0;
354
355  unlock:
356         mutex_unlock(&spec->pcm_lock);
357         return 0;
358 }
359
360 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
361                         struct snd_ctl_elem_value *ucontrol)
362 {
363         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
364         struct hdmi_spec *spec = codec->spec;
365         struct hdmi_spec_per_pin *per_pin;
366         struct hdmi_eld *eld;
367         int pcm_idx;
368         int err = 0;
369
370         pcm_idx = kcontrol->private_value;
371         mutex_lock(&spec->pcm_lock);
372         per_pin = pcm_idx_to_pin(spec, pcm_idx);
373         if (!per_pin) {
374                 /* no pin is bound to the pcm */
375                 memset(ucontrol->value.bytes.data, 0,
376                        ARRAY_SIZE(ucontrol->value.bytes.data));
377                 goto unlock;
378         }
379
380         eld = &per_pin->sink_eld;
381         if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
382             eld->eld_size > ELD_MAX_SIZE) {
383                 snd_BUG();
384                 err = -EINVAL;
385                 goto unlock;
386         }
387
388         memset(ucontrol->value.bytes.data, 0,
389                ARRAY_SIZE(ucontrol->value.bytes.data));
390         if (eld->eld_valid)
391                 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
392                        eld->eld_size);
393
394  unlock:
395         mutex_unlock(&spec->pcm_lock);
396         return err;
397 }
398
399 static const struct snd_kcontrol_new eld_bytes_ctl = {
400         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
401                 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
402         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
403         .name = "ELD",
404         .info = hdmi_eld_ctl_info,
405         .get = hdmi_eld_ctl_get,
406 };
407
408 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
409                         int device)
410 {
411         struct snd_kcontrol *kctl;
412         struct hdmi_spec *spec = codec->spec;
413         int err;
414
415         kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
416         if (!kctl)
417                 return -ENOMEM;
418         kctl->private_value = pcm_idx;
419         kctl->id.device = device;
420
421         /* no pin nid is associated with the kctl now
422          * tbd: associate pin nid to eld ctl later
423          */
424         err = snd_hda_ctl_add(codec, 0, kctl);
425         if (err < 0)
426                 return err;
427
428         get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
429         return 0;
430 }
431
432 #ifdef BE_PARANOID
433 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
434                                 int *packet_index, int *byte_index)
435 {
436         int val;
437
438         val = snd_hda_codec_read(codec, pin_nid, 0,
439                                  AC_VERB_GET_HDMI_DIP_INDEX, 0);
440
441         *packet_index = val >> 5;
442         *byte_index = val & 0x1f;
443 }
444 #endif
445
446 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
447                                 int packet_index, int byte_index)
448 {
449         int val;
450
451         val = (packet_index << 5) | (byte_index & 0x1f);
452
453         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
454 }
455
456 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
457                                 unsigned char val)
458 {
459         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
460 }
461
462 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
463 {
464         struct hdmi_spec *spec = codec->spec;
465         int pin_out;
466
467         /* Unmute */
468         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
469                 snd_hda_codec_write(codec, pin_nid, 0,
470                                 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
471
472         if (spec->dyn_pin_out)
473                 /* Disable pin out until stream is active */
474                 pin_out = 0;
475         else
476                 /* Enable pin out: some machines with GM965 gets broken output
477                  * when the pin is disabled or changed while using with HDMI
478                  */
479                 pin_out = PIN_OUT;
480
481         snd_hda_codec_write(codec, pin_nid, 0,
482                             AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
483 }
484
485 /*
486  * ELD proc files
487  */
488
489 #ifdef CONFIG_SND_PROC_FS
490 static void print_eld_info(struct snd_info_entry *entry,
491                            struct snd_info_buffer *buffer)
492 {
493         struct hdmi_spec_per_pin *per_pin = entry->private_data;
494
495         mutex_lock(&per_pin->lock);
496         snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
497         mutex_unlock(&per_pin->lock);
498 }
499
500 static void write_eld_info(struct snd_info_entry *entry,
501                            struct snd_info_buffer *buffer)
502 {
503         struct hdmi_spec_per_pin *per_pin = entry->private_data;
504
505         mutex_lock(&per_pin->lock);
506         snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
507         mutex_unlock(&per_pin->lock);
508 }
509
510 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
511 {
512         char name[32];
513         struct hda_codec *codec = per_pin->codec;
514         struct snd_info_entry *entry;
515         int err;
516
517         snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
518         err = snd_card_proc_new(codec->card, name, &entry);
519         if (err < 0)
520                 return err;
521
522         snd_info_set_text_ops(entry, per_pin, print_eld_info);
523         entry->c.text.write = write_eld_info;
524         entry->mode |= 0200;
525         per_pin->proc_entry = entry;
526
527         return 0;
528 }
529
530 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
531 {
532         if (!per_pin->codec->bus->shutdown) {
533                 snd_info_free_entry(per_pin->proc_entry);
534                 per_pin->proc_entry = NULL;
535         }
536 }
537 #else
538 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
539                                int index)
540 {
541         return 0;
542 }
543 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
544 {
545 }
546 #endif
547
548 /*
549  * Audio InfoFrame routines
550  */
551
552 /*
553  * Enable Audio InfoFrame Transmission
554  */
555 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
556                                        hda_nid_t pin_nid)
557 {
558         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
559         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
560                                                 AC_DIPXMIT_BEST);
561 }
562
563 /*
564  * Disable Audio InfoFrame Transmission
565  */
566 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
567                                       hda_nid_t pin_nid)
568 {
569         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
570         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
571                                                 AC_DIPXMIT_DISABLE);
572 }
573
574 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
575 {
576 #ifdef CONFIG_SND_DEBUG_VERBOSE
577         int i;
578         int size;
579
580         size = snd_hdmi_get_eld_size(codec, pin_nid);
581         codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
582
583         for (i = 0; i < 8; i++) {
584                 size = snd_hda_codec_read(codec, pin_nid, 0,
585                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
586                 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
587         }
588 #endif
589 }
590
591 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
592 {
593 #ifdef BE_PARANOID
594         int i, j;
595         int size;
596         int pi, bi;
597         for (i = 0; i < 8; i++) {
598                 size = snd_hda_codec_read(codec, pin_nid, 0,
599                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
600                 if (size == 0)
601                         continue;
602
603                 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
604                 for (j = 1; j < 1000; j++) {
605                         hdmi_write_dip_byte(codec, pin_nid, 0x0);
606                         hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
607                         if (pi != i)
608                                 codec_dbg(codec, "dip index %d: %d != %d\n",
609                                                 bi, pi, i);
610                         if (bi == 0) /* byte index wrapped around */
611                                 break;
612                 }
613                 codec_dbg(codec,
614                         "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
615                         i, size, j);
616         }
617 #endif
618 }
619
620 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
621 {
622         u8 *bytes = (u8 *)hdmi_ai;
623         u8 sum = 0;
624         int i;
625
626         hdmi_ai->checksum = 0;
627
628         for (i = 0; i < sizeof(*hdmi_ai); i++)
629                 sum += bytes[i];
630
631         hdmi_ai->checksum = -sum;
632 }
633
634 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
635                                       hda_nid_t pin_nid,
636                                       u8 *dip, int size)
637 {
638         int i;
639
640         hdmi_debug_dip_size(codec, pin_nid);
641         hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
642
643         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
644         for (i = 0; i < size; i++)
645                 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
646 }
647
648 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
649                                     u8 *dip, int size)
650 {
651         u8 val;
652         int i;
653
654         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
655         if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
656                                                             != AC_DIPXMIT_BEST)
657                 return false;
658
659         for (i = 0; i < size; i++) {
660                 val = snd_hda_codec_read(codec, pin_nid, 0,
661                                          AC_VERB_GET_HDMI_DIP_DATA, 0);
662                 if (val != dip[i])
663                         return false;
664         }
665
666         return true;
667 }
668
669 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
670                             int dev_id, unsigned char *buf, int *eld_size)
671 {
672         snd_hda_set_dev_select(codec, nid, dev_id);
673
674         return snd_hdmi_get_eld(codec, nid, buf, eld_size);
675 }
676
677 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
678                                      hda_nid_t pin_nid, int dev_id,
679                                      int ca, int active_channels,
680                                      int conn_type)
681 {
682         union audio_infoframe ai;
683
684         memset(&ai, 0, sizeof(ai));
685         if (conn_type == 0) { /* HDMI */
686                 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
687
688                 hdmi_ai->type           = 0x84;
689                 hdmi_ai->ver            = 0x01;
690                 hdmi_ai->len            = 0x0a;
691                 hdmi_ai->CC02_CT47      = active_channels - 1;
692                 hdmi_ai->CA             = ca;
693                 hdmi_checksum_audio_infoframe(hdmi_ai);
694         } else if (conn_type == 1) { /* DisplayPort */
695                 struct dp_audio_infoframe *dp_ai = &ai.dp;
696
697                 dp_ai->type             = 0x84;
698                 dp_ai->len              = 0x1b;
699                 dp_ai->ver              = 0x11 << 2;
700                 dp_ai->CC02_CT47        = active_channels - 1;
701                 dp_ai->CA               = ca;
702         } else {
703                 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
704                 return;
705         }
706
707         snd_hda_set_dev_select(codec, pin_nid, dev_id);
708
709         /*
710          * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
711          * sizeof(*dp_ai) to avoid partial match/update problems when
712          * the user switches between HDMI/DP monitors.
713          */
714         if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
715                                         sizeof(ai))) {
716                 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
717                           __func__, pin_nid, active_channels, ca);
718                 hdmi_stop_infoframe_trans(codec, pin_nid);
719                 hdmi_fill_audio_infoframe(codec, pin_nid,
720                                             ai.bytes, sizeof(ai));
721                 hdmi_start_infoframe_trans(codec, pin_nid);
722         }
723 }
724
725 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
726                                        struct hdmi_spec_per_pin *per_pin,
727                                        bool non_pcm)
728 {
729         struct hdmi_spec *spec = codec->spec;
730         struct hdac_chmap *chmap = &spec->chmap;
731         hda_nid_t pin_nid = per_pin->pin_nid;
732         int dev_id = per_pin->dev_id;
733         int channels = per_pin->channels;
734         int active_channels;
735         struct hdmi_eld *eld;
736         int ca;
737
738         if (!channels)
739                 return;
740
741         snd_hda_set_dev_select(codec, pin_nid, dev_id);
742
743         /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
744         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
745                 snd_hda_codec_write(codec, pin_nid, 0,
746                                             AC_VERB_SET_AMP_GAIN_MUTE,
747                                             AMP_OUT_UNMUTE);
748
749         eld = &per_pin->sink_eld;
750
751         ca = snd_hdac_channel_allocation(&codec->core,
752                         eld->info.spk_alloc, channels,
753                         per_pin->chmap_set, non_pcm, per_pin->chmap);
754
755         active_channels = snd_hdac_get_active_channels(ca);
756
757         chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
758                                                 active_channels);
759
760         /*
761          * always configure channel mapping, it may have been changed by the
762          * user in the meantime
763          */
764         snd_hdac_setup_channel_mapping(&spec->chmap,
765                                 pin_nid, non_pcm, ca, channels,
766                                 per_pin->chmap, per_pin->chmap_set);
767
768         spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
769                                       ca, active_channels, eld->info.conn_type);
770
771         per_pin->non_pcm = non_pcm;
772 }
773
774 /*
775  * Unsolicited events
776  */
777
778 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
779
780 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
781                                       int dev_id)
782 {
783         struct hdmi_spec *spec = codec->spec;
784         int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
785
786         if (pin_idx < 0)
787                 return;
788         mutex_lock(&spec->pcm_lock);
789         hdmi_present_sense(get_pin(spec, pin_idx), 1);
790         mutex_unlock(&spec->pcm_lock);
791 }
792
793 static void jack_callback(struct hda_codec *codec,
794                           struct hda_jack_callback *jack)
795 {
796         /* stop polling when notification is enabled */
797         if (codec_has_acomp(codec))
798                 return;
799
800         check_presence_and_report(codec, jack->nid, jack->dev_id);
801 }
802
803 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
804                                  struct hda_jack_tbl *jack)
805 {
806         jack->jack_dirty = 1;
807
808         codec_dbg(codec,
809                 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
810                 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
811                 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
812
813         check_presence_and_report(codec, jack->nid, jack->dev_id);
814 }
815
816 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
817 {
818         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
819         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
820         int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
821         int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
822
823         codec_info(codec,
824                 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
825                 codec->addr,
826                 tag,
827                 subtag,
828                 cp_state,
829                 cp_ready);
830
831         /* TODO */
832         if (cp_state) {
833                 ;
834         }
835         if (cp_ready) {
836                 ;
837         }
838 }
839
840
841 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
842 {
843         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
844         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
845         struct hda_jack_tbl *jack;
846
847         if (codec_has_acomp(codec))
848                 return;
849
850         if (codec->dp_mst) {
851                 int dev_entry =
852                         (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
853
854                 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
855         } else {
856                 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
857         }
858
859         if (!jack) {
860                 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
861                 return;
862         }
863
864         if (subtag == 0)
865                 hdmi_intrinsic_event(codec, res, jack);
866         else
867                 hdmi_non_intrinsic_event(codec, res);
868 }
869
870 static void haswell_verify_D0(struct hda_codec *codec,
871                 hda_nid_t cvt_nid, hda_nid_t nid)
872 {
873         int pwr;
874
875         /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
876          * thus pins could only choose converter 0 for use. Make sure the
877          * converters are in correct power state */
878         if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
879                 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
880
881         if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
882                 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
883                                     AC_PWRST_D0);
884                 msleep(40);
885                 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
886                 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
887                 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
888         }
889 }
890
891 /*
892  * Callbacks
893  */
894
895 /* HBR should be Non-PCM, 8 channels */
896 #define is_hbr_format(format) \
897         ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
898
899 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
900                               int dev_id, bool hbr)
901 {
902         int pinctl, new_pinctl;
903
904         if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
905                 snd_hda_set_dev_select(codec, pin_nid, dev_id);
906                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
907                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
908
909                 if (pinctl < 0)
910                         return hbr ? -EINVAL : 0;
911
912                 new_pinctl = pinctl & ~AC_PINCTL_EPT;
913                 if (hbr)
914                         new_pinctl |= AC_PINCTL_EPT_HBR;
915                 else
916                         new_pinctl |= AC_PINCTL_EPT_NATIVE;
917
918                 codec_dbg(codec,
919                           "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
920                             pin_nid,
921                             pinctl == new_pinctl ? "" : "new-",
922                             new_pinctl);
923
924                 if (pinctl != new_pinctl)
925                         snd_hda_codec_write(codec, pin_nid, 0,
926                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
927                                             new_pinctl);
928         } else if (hbr)
929                 return -EINVAL;
930
931         return 0;
932 }
933
934 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
935                               hda_nid_t pin_nid, int dev_id,
936                               u32 stream_tag, int format)
937 {
938         struct hdmi_spec *spec = codec->spec;
939         unsigned int param;
940         int err;
941
942         err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
943                                       is_hbr_format(format));
944
945         if (err) {
946                 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
947                 return err;
948         }
949
950         if (spec->intel_hsw_fixup) {
951
952                 /*
953                  * on recent platforms IEC Coding Type is required for HBR
954                  * support, read current Digital Converter settings and set
955                  * ICT bitfield if needed.
956                  */
957                 param = snd_hda_codec_read(codec, cvt_nid, 0,
958                                            AC_VERB_GET_DIGI_CONVERT_1, 0);
959
960                 param = (param >> 16) & ~(AC_DIG3_ICT);
961
962                 /* on recent platforms ICT mode is required for HBR support */
963                 if (is_hbr_format(format))
964                         param |= 0x1;
965
966                 snd_hda_codec_write(codec, cvt_nid, 0,
967                                     AC_VERB_SET_DIGI_CONVERT_3, param);
968         }
969
970         snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
971         return 0;
972 }
973
974 /* Try to find an available converter
975  * If pin_idx is less then zero, just try to find an available converter.
976  * Otherwise, try to find an available converter and get the cvt mux index
977  * of the pin.
978  */
979 static int hdmi_choose_cvt(struct hda_codec *codec,
980                            int pin_idx, int *cvt_id)
981 {
982         struct hdmi_spec *spec = codec->spec;
983         struct hdmi_spec_per_pin *per_pin;
984         struct hdmi_spec_per_cvt *per_cvt = NULL;
985         int cvt_idx, mux_idx = 0;
986
987         /* pin_idx < 0 means no pin will be bound to the converter */
988         if (pin_idx < 0)
989                 per_pin = NULL;
990         else
991                 per_pin = get_pin(spec, pin_idx);
992
993         if (per_pin && per_pin->silent_stream) {
994                 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
995                 if (cvt_id)
996                         *cvt_id = cvt_idx;
997                 return 0;
998         }
999
1000         /* Dynamically assign converter to stream */
1001         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1002                 per_cvt = get_cvt(spec, cvt_idx);
1003
1004                 /* Must not already be assigned */
1005                 if (per_cvt->assigned)
1006                         continue;
1007                 if (per_pin == NULL)
1008                         break;
1009                 /* Must be in pin's mux's list of converters */
1010                 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1011                         if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1012                                 break;
1013                 /* Not in mux list */
1014                 if (mux_idx == per_pin->num_mux_nids)
1015                         continue;
1016                 break;
1017         }
1018
1019         /* No free converters */
1020         if (cvt_idx == spec->num_cvts)
1021                 return -EBUSY;
1022
1023         if (per_pin != NULL)
1024                 per_pin->mux_idx = mux_idx;
1025
1026         if (cvt_id)
1027                 *cvt_id = cvt_idx;
1028
1029         return 0;
1030 }
1031
1032 /* Assure the pin select the right convetor */
1033 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1034                         struct hdmi_spec_per_pin *per_pin)
1035 {
1036         hda_nid_t pin_nid = per_pin->pin_nid;
1037         int mux_idx, curr;
1038
1039         mux_idx = per_pin->mux_idx;
1040         curr = snd_hda_codec_read(codec, pin_nid, 0,
1041                                           AC_VERB_GET_CONNECT_SEL, 0);
1042         if (curr != mux_idx)
1043                 snd_hda_codec_write_cache(codec, pin_nid, 0,
1044                                             AC_VERB_SET_CONNECT_SEL,
1045                                             mux_idx);
1046 }
1047
1048 /* get the mux index for the converter of the pins
1049  * converter's mux index is the same for all pins on Intel platform
1050  */
1051 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1052                         hda_nid_t cvt_nid)
1053 {
1054         int i;
1055
1056         for (i = 0; i < spec->num_cvts; i++)
1057                 if (spec->cvt_nids[i] == cvt_nid)
1058                         return i;
1059         return -EINVAL;
1060 }
1061
1062 /* Intel HDMI workaround to fix audio routing issue:
1063  * For some Intel display codecs, pins share the same connection list.
1064  * So a conveter can be selected by multiple pins and playback on any of these
1065  * pins will generate sound on the external display, because audio flows from
1066  * the same converter to the display pipeline. Also muting one pin may make
1067  * other pins have no sound output.
1068  * So this function assures that an assigned converter for a pin is not selected
1069  * by any other pins.
1070  */
1071 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1072                                          hda_nid_t pin_nid,
1073                                          int dev_id, int mux_idx)
1074 {
1075         struct hdmi_spec *spec = codec->spec;
1076         hda_nid_t nid;
1077         int cvt_idx, curr;
1078         struct hdmi_spec_per_cvt *per_cvt;
1079         struct hdmi_spec_per_pin *per_pin;
1080         int pin_idx;
1081
1082         /* configure the pins connections */
1083         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1084                 int dev_id_saved;
1085                 int dev_num;
1086
1087                 per_pin = get_pin(spec, pin_idx);
1088                 /*
1089                  * pin not connected to monitor
1090                  * no need to operate on it
1091                  */
1092                 if (!per_pin->pcm)
1093                         continue;
1094
1095                 if ((per_pin->pin_nid == pin_nid) &&
1096                         (per_pin->dev_id == dev_id))
1097                         continue;
1098
1099                 /*
1100                  * if per_pin->dev_id >= dev_num,
1101                  * snd_hda_get_dev_select() will fail,
1102                  * and the following operation is unpredictable.
1103                  * So skip this situation.
1104                  */
1105                 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1106                 if (per_pin->dev_id >= dev_num)
1107                         continue;
1108
1109                 nid = per_pin->pin_nid;
1110
1111                 /*
1112                  * Calling this function should not impact
1113                  * on the device entry selection
1114                  * So let's save the dev id for each pin,
1115                  * and restore it when return
1116                  */
1117                 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1118                 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1119                 curr = snd_hda_codec_read(codec, nid, 0,
1120                                           AC_VERB_GET_CONNECT_SEL, 0);
1121                 if (curr != mux_idx) {
1122                         snd_hda_set_dev_select(codec, nid, dev_id_saved);
1123                         continue;
1124                 }
1125
1126
1127                 /* choose an unassigned converter. The conveters in the
1128                  * connection list are in the same order as in the codec.
1129                  */
1130                 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1131                         per_cvt = get_cvt(spec, cvt_idx);
1132                         if (!per_cvt->assigned) {
1133                                 codec_dbg(codec,
1134                                           "choose cvt %d for pin NID 0x%x\n",
1135                                           cvt_idx, nid);
1136                                 snd_hda_codec_write_cache(codec, nid, 0,
1137                                             AC_VERB_SET_CONNECT_SEL,
1138                                             cvt_idx);
1139                                 break;
1140                         }
1141                 }
1142                 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1143         }
1144 }
1145
1146 /* A wrapper of intel_not_share_asigned_cvt() */
1147 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1148                         hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1149 {
1150         int mux_idx;
1151         struct hdmi_spec *spec = codec->spec;
1152
1153         /* On Intel platform, the mapping of converter nid to
1154          * mux index of the pins are always the same.
1155          * The pin nid may be 0, this means all pins will not
1156          * share the converter.
1157          */
1158         mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1159         if (mux_idx >= 0)
1160                 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1161 }
1162
1163 /* skeleton caller of pin_cvt_fixup ops */
1164 static void pin_cvt_fixup(struct hda_codec *codec,
1165                           struct hdmi_spec_per_pin *per_pin,
1166                           hda_nid_t cvt_nid)
1167 {
1168         struct hdmi_spec *spec = codec->spec;
1169
1170         if (spec->ops.pin_cvt_fixup)
1171                 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1172 }
1173
1174 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1175  * in dyn_pcm_assign mode.
1176  */
1177 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1178                          struct hda_codec *codec,
1179                          struct snd_pcm_substream *substream)
1180 {
1181         struct hdmi_spec *spec = codec->spec;
1182         struct snd_pcm_runtime *runtime = substream->runtime;
1183         int cvt_idx, pcm_idx;
1184         struct hdmi_spec_per_cvt *per_cvt = NULL;
1185         int err;
1186
1187         pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1188         if (pcm_idx < 0)
1189                 return -EINVAL;
1190
1191         err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1192         if (err)
1193                 return err;
1194
1195         per_cvt = get_cvt(spec, cvt_idx);
1196         per_cvt->assigned = 1;
1197         hinfo->nid = per_cvt->cvt_nid;
1198
1199         pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1200
1201         set_bit(pcm_idx, &spec->pcm_in_use);
1202         /* todo: setup spdif ctls assign */
1203
1204         /* Initially set the converter's capabilities */
1205         hinfo->channels_min = per_cvt->channels_min;
1206         hinfo->channels_max = per_cvt->channels_max;
1207         hinfo->rates = per_cvt->rates;
1208         hinfo->formats = per_cvt->formats;
1209         hinfo->maxbps = per_cvt->maxbps;
1210
1211         /* Store the updated parameters */
1212         runtime->hw.channels_min = hinfo->channels_min;
1213         runtime->hw.channels_max = hinfo->channels_max;
1214         runtime->hw.formats = hinfo->formats;
1215         runtime->hw.rates = hinfo->rates;
1216
1217         snd_pcm_hw_constraint_step(substream->runtime, 0,
1218                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1219         return 0;
1220 }
1221
1222 /*
1223  * HDA PCM callbacks
1224  */
1225 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1226                          struct hda_codec *codec,
1227                          struct snd_pcm_substream *substream)
1228 {
1229         struct hdmi_spec *spec = codec->spec;
1230         struct snd_pcm_runtime *runtime = substream->runtime;
1231         int pin_idx, cvt_idx, pcm_idx;
1232         struct hdmi_spec_per_pin *per_pin;
1233         struct hdmi_eld *eld;
1234         struct hdmi_spec_per_cvt *per_cvt = NULL;
1235         int err;
1236
1237         /* Validate hinfo */
1238         pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1239         if (pcm_idx < 0)
1240                 return -EINVAL;
1241
1242         mutex_lock(&spec->pcm_lock);
1243         pin_idx = hinfo_to_pin_index(codec, hinfo);
1244         if (!spec->dyn_pcm_assign) {
1245                 if (snd_BUG_ON(pin_idx < 0)) {
1246                         err = -EINVAL;
1247                         goto unlock;
1248                 }
1249         } else {
1250                 /* no pin is assigned to the PCM
1251                  * PA need pcm open successfully when probe
1252                  */
1253                 if (pin_idx < 0) {
1254                         err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1255                         goto unlock;
1256                 }
1257         }
1258
1259         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1260         if (err < 0)
1261                 goto unlock;
1262
1263         per_cvt = get_cvt(spec, cvt_idx);
1264         /* Claim converter */
1265         per_cvt->assigned = 1;
1266
1267         set_bit(pcm_idx, &spec->pcm_in_use);
1268         per_pin = get_pin(spec, pin_idx);
1269         per_pin->cvt_nid = per_cvt->cvt_nid;
1270         hinfo->nid = per_cvt->cvt_nid;
1271
1272         /* flip stripe flag for the assigned stream if supported */
1273         if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1274                 azx_stream(get_azx_dev(substream))->stripe = 1;
1275
1276         snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1277         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1278                             AC_VERB_SET_CONNECT_SEL,
1279                             per_pin->mux_idx);
1280
1281         /* configure unused pins to choose other converters */
1282         pin_cvt_fixup(codec, per_pin, 0);
1283
1284         snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1285
1286         /* Initially set the converter's capabilities */
1287         hinfo->channels_min = per_cvt->channels_min;
1288         hinfo->channels_max = per_cvt->channels_max;
1289         hinfo->rates = per_cvt->rates;
1290         hinfo->formats = per_cvt->formats;
1291         hinfo->maxbps = per_cvt->maxbps;
1292
1293         eld = &per_pin->sink_eld;
1294         /* Restrict capabilities by ELD if this isn't disabled */
1295         if (!static_hdmi_pcm && eld->eld_valid) {
1296                 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1297                 if (hinfo->channels_min > hinfo->channels_max ||
1298                     !hinfo->rates || !hinfo->formats) {
1299                         per_cvt->assigned = 0;
1300                         hinfo->nid = 0;
1301                         snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1302                         err = -ENODEV;
1303                         goto unlock;
1304                 }
1305         }
1306
1307         /* Store the updated parameters */
1308         runtime->hw.channels_min = hinfo->channels_min;
1309         runtime->hw.channels_max = hinfo->channels_max;
1310         runtime->hw.formats = hinfo->formats;
1311         runtime->hw.rates = hinfo->rates;
1312
1313         snd_pcm_hw_constraint_step(substream->runtime, 0,
1314                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1315  unlock:
1316         mutex_unlock(&spec->pcm_lock);
1317         return err;
1318 }
1319
1320 /*
1321  * HDA/HDMI auto parsing
1322  */
1323 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1324 {
1325         struct hdmi_spec *spec = codec->spec;
1326         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1327         hda_nid_t pin_nid = per_pin->pin_nid;
1328         int dev_id = per_pin->dev_id;
1329         int conns;
1330
1331         if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1332                 codec_warn(codec,
1333                            "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1334                            pin_nid, get_wcaps(codec, pin_nid));
1335                 return -EINVAL;
1336         }
1337
1338         snd_hda_set_dev_select(codec, pin_nid, dev_id);
1339
1340         if (spec->intel_hsw_fixup) {
1341                 conns = spec->num_cvts;
1342                 memcpy(per_pin->mux_nids, spec->cvt_nids,
1343                        sizeof(hda_nid_t) * conns);
1344         } else {
1345                 conns = snd_hda_get_raw_connections(codec, pin_nid,
1346                                                     per_pin->mux_nids,
1347                                                     HDA_MAX_CONNECTIONS);
1348         }
1349
1350         /* all the device entries on the same pin have the same conn list */
1351         per_pin->num_mux_nids = conns;
1352
1353         return 0;
1354 }
1355
1356 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1357                               struct hdmi_spec_per_pin *per_pin)
1358 {
1359         int i;
1360
1361         /* on the new machines, try to assign the pcm slot dynamically,
1362          * not use the preferred fixed map (legacy way) anymore.
1363          */
1364         if (spec->dyn_pcm_no_legacy)
1365                 goto last_try;
1366
1367         /*
1368          * generic_hdmi_build_pcms() may allocate extra PCMs on some
1369          * platforms (with maximum of 'num_nids + dev_num - 1')
1370          *
1371          * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1372          * if m==0. This guarantees that dynamic pcm assignments are compatible
1373          * with the legacy static per_pin-pcm assignment that existed in the
1374          * days before DP-MST.
1375          *
1376          * Intel DP-MST prefers this legacy behavior for compatibility, too.
1377          *
1378          * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1379          */
1380
1381         if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1382                 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1383                         return per_pin->pin_nid_idx;
1384         } else {
1385                 i = spec->num_nids + (per_pin->dev_id - 1);
1386                 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1387                         return i;
1388         }
1389
1390         /* have a second try; check the area over num_nids */
1391         for (i = spec->num_nids; i < spec->pcm_used; i++) {
1392                 if (!test_bit(i, &spec->pcm_bitmap))
1393                         return i;
1394         }
1395
1396  last_try:
1397         /* the last try; check the empty slots in pins */
1398         for (i = 0; i < spec->num_nids; i++) {
1399                 if (!test_bit(i, &spec->pcm_bitmap))
1400                         return i;
1401         }
1402         return -EBUSY;
1403 }
1404
1405 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1406                                 struct hdmi_spec_per_pin *per_pin)
1407 {
1408         int idx;
1409
1410         /* pcm already be attached to the pin */
1411         if (per_pin->pcm)
1412                 return;
1413         idx = hdmi_find_pcm_slot(spec, per_pin);
1414         if (idx == -EBUSY)
1415                 return;
1416         per_pin->pcm_idx = idx;
1417         per_pin->pcm = get_hdmi_pcm(spec, idx);
1418         set_bit(idx, &spec->pcm_bitmap);
1419 }
1420
1421 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1422                                 struct hdmi_spec_per_pin *per_pin)
1423 {
1424         int idx;
1425
1426         /* pcm already be detached from the pin */
1427         if (!per_pin->pcm)
1428                 return;
1429         idx = per_pin->pcm_idx;
1430         per_pin->pcm_idx = -1;
1431         per_pin->pcm = NULL;
1432         if (idx >= 0 && idx < spec->pcm_used)
1433                 clear_bit(idx, &spec->pcm_bitmap);
1434 }
1435
1436 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1437                 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1438 {
1439         int mux_idx;
1440
1441         for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1442                 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1443                         break;
1444         return mux_idx;
1445 }
1446
1447 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1448
1449 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1450                            struct hdmi_spec_per_pin *per_pin)
1451 {
1452         struct hda_codec *codec = per_pin->codec;
1453         struct hda_pcm *pcm;
1454         struct hda_pcm_stream *hinfo;
1455         struct snd_pcm_substream *substream;
1456         int mux_idx;
1457         bool non_pcm;
1458
1459         if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1460                 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1461         else
1462                 return;
1463         if (!pcm->pcm)
1464                 return;
1465         if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1466                 return;
1467
1468         /* hdmi audio only uses playback and one substream */
1469         hinfo = pcm->stream;
1470         substream = pcm->pcm->streams[0].substream;
1471
1472         per_pin->cvt_nid = hinfo->nid;
1473
1474         mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1475         if (mux_idx < per_pin->num_mux_nids) {
1476                 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1477                                    per_pin->dev_id);
1478                 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1479                                 AC_VERB_SET_CONNECT_SEL,
1480                                 mux_idx);
1481         }
1482         snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1483
1484         non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1485         if (substream->runtime)
1486                 per_pin->channels = substream->runtime->channels;
1487         per_pin->setup = true;
1488         per_pin->mux_idx = mux_idx;
1489
1490         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1491 }
1492
1493 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1494                            struct hdmi_spec_per_pin *per_pin)
1495 {
1496         if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1497                 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1498
1499         per_pin->chmap_set = false;
1500         memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1501
1502         per_pin->setup = false;
1503         per_pin->channels = 0;
1504 }
1505
1506 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1507                                             struct hdmi_spec_per_pin *per_pin)
1508 {
1509         struct hdmi_spec *spec = codec->spec;
1510
1511         if (per_pin->pcm_idx >= 0)
1512                 return spec->pcm_rec[per_pin->pcm_idx].jack;
1513         else
1514                 return NULL;
1515 }
1516
1517 /* update per_pin ELD from the given new ELD;
1518  * setup info frame and notification accordingly
1519  * also notify ELD kctl and report jack status changes
1520  */
1521 static void update_eld(struct hda_codec *codec,
1522                        struct hdmi_spec_per_pin *per_pin,
1523                        struct hdmi_eld *eld,
1524                        int repoll)
1525 {
1526         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1527         struct hdmi_spec *spec = codec->spec;
1528         struct snd_jack *pcm_jack;
1529         bool old_eld_valid = pin_eld->eld_valid;
1530         bool eld_changed;
1531         int pcm_idx;
1532
1533         if (eld->eld_valid) {
1534                 if (eld->eld_size <= 0 ||
1535                     snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1536                                        eld->eld_size) < 0) {
1537                         eld->eld_valid = false;
1538                         if (repoll) {
1539                                 schedule_delayed_work(&per_pin->work,
1540                                                       msecs_to_jiffies(300));
1541                                 return;
1542                         }
1543                 }
1544         }
1545
1546         if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
1547                 eld->eld_valid = false;
1548                 eld->eld_size = 0;
1549         }
1550
1551         /* for monitor disconnection, save pcm_idx firstly */
1552         pcm_idx = per_pin->pcm_idx;
1553
1554         /*
1555          * pcm_idx >=0 before update_eld() means it is in monitor
1556          * disconnected event. Jack must be fetched before update_eld().
1557          */
1558         pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1559
1560         if (spec->dyn_pcm_assign) {
1561                 if (eld->eld_valid) {
1562                         hdmi_attach_hda_pcm(spec, per_pin);
1563                         hdmi_pcm_setup_pin(spec, per_pin);
1564                 } else {
1565                         hdmi_pcm_reset_pin(spec, per_pin);
1566                         hdmi_detach_hda_pcm(spec, per_pin);
1567                 }
1568         }
1569         /* if pcm_idx == -1, it means this is in monitor connection event
1570          * we can get the correct pcm_idx now.
1571          */
1572         if (pcm_idx == -1)
1573                 pcm_idx = per_pin->pcm_idx;
1574         if (!pcm_jack)
1575                 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1576
1577         if (eld->eld_valid)
1578                 snd_hdmi_show_eld(codec, &eld->info);
1579
1580         eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1581         eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1582         if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1583                 if (pin_eld->eld_size != eld->eld_size ||
1584                     memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1585                            eld->eld_size) != 0)
1586                         eld_changed = true;
1587
1588         if (eld_changed) {
1589                 pin_eld->monitor_present = eld->monitor_present;
1590                 pin_eld->eld_valid = eld->eld_valid;
1591                 pin_eld->eld_size = eld->eld_size;
1592                 if (eld->eld_valid)
1593                         memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1594                                eld->eld_size);
1595                 pin_eld->info = eld->info;
1596         }
1597
1598         /*
1599          * Re-setup pin and infoframe. This is needed e.g. when
1600          * - sink is first plugged-in
1601          * - transcoder can change during stream playback on Haswell
1602          *   and this can make HW reset converter selection on a pin.
1603          */
1604         if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1605                 pin_cvt_fixup(codec, per_pin, 0);
1606                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1607         }
1608
1609         if (eld_changed && pcm_idx >= 0)
1610                 snd_ctl_notify(codec->card,
1611                                SNDRV_CTL_EVENT_MASK_VALUE |
1612                                SNDRV_CTL_EVENT_MASK_INFO,
1613                                &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1614
1615         if (eld_changed && pcm_jack)
1616                 snd_jack_report(pcm_jack,
1617                                 (eld->monitor_present && eld->eld_valid) ?
1618                                 SND_JACK_AVOUT : 0);
1619 }
1620
1621 /* update ELD and jack state via HD-audio verbs */
1622 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1623                                          int repoll)
1624 {
1625         struct hda_codec *codec = per_pin->codec;
1626         struct hdmi_spec *spec = codec->spec;
1627         struct hdmi_eld *eld = &spec->temp_eld;
1628         struct device *dev = hda_codec_dev(codec);
1629         hda_nid_t pin_nid = per_pin->pin_nid;
1630         int dev_id = per_pin->dev_id;
1631         /*
1632          * Always execute a GetPinSense verb here, even when called from
1633          * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1634          * response's PD bit is not the real PD value, but indicates that
1635          * the real PD value changed. An older version of the HD-audio
1636          * specification worked this way. Hence, we just ignore the data in
1637          * the unsolicited response to avoid custom WARs.
1638          */
1639         int present;
1640         int ret;
1641
1642 #ifdef  CONFIG_PM
1643         if (dev->power.runtime_status == RPM_SUSPENDING)
1644                 return;
1645 #endif
1646
1647         ret = snd_hda_power_up_pm(codec);
1648         if (ret < 0 && pm_runtime_suspended(dev))
1649                 goto out;
1650
1651         present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1652
1653         mutex_lock(&per_pin->lock);
1654         eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1655         if (eld->monitor_present)
1656                 eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1657         else
1658                 eld->eld_valid = false;
1659
1660         codec_dbg(codec,
1661                 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1662                 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1663
1664         if (eld->eld_valid) {
1665                 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1666                                           eld->eld_buffer, &eld->eld_size) < 0)
1667                         eld->eld_valid = false;
1668         }
1669
1670         update_eld(codec, per_pin, eld, repoll);
1671         mutex_unlock(&per_pin->lock);
1672  out:
1673         snd_hda_power_down_pm(codec);
1674 }
1675
1676 #define I915_SILENT_RATE                48000
1677 #define I915_SILENT_CHANNELS            2
1678 #define I915_SILENT_FORMAT              SNDRV_PCM_FORMAT_S16_LE
1679 #define I915_SILENT_FORMAT_BITS 16
1680 #define I915_SILENT_FMT_MASK            0xf
1681
1682 static void silent_stream_enable_i915(struct hda_codec *codec,
1683                                       struct hdmi_spec_per_pin *per_pin)
1684 {
1685         unsigned int format;
1686
1687         snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1688                                  per_pin->dev_id, I915_SILENT_RATE);
1689
1690         /* trigger silent stream generation in hw */
1691         format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS,
1692                                              I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0);
1693         snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1694                                    I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1695         usleep_range(100, 200);
1696         snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1697
1698         per_pin->channels = I915_SILENT_CHANNELS;
1699         hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1700 }
1701
1702 static void silent_stream_set_kae(struct hda_codec *codec,
1703                                   struct hdmi_spec_per_pin *per_pin,
1704                                   bool enable)
1705 {
1706         unsigned int param;
1707
1708         codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
1709
1710         param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
1711         param = (param >> 16) & 0xff;
1712
1713         if (enable)
1714                 param |= AC_DIG3_KAE;
1715         else
1716                 param &= ~AC_DIG3_KAE;
1717
1718         snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
1719 }
1720
1721 static void silent_stream_enable(struct hda_codec *codec,
1722                                  struct hdmi_spec_per_pin *per_pin)
1723 {
1724         struct hdmi_spec *spec = codec->spec;
1725         struct hdmi_spec_per_cvt *per_cvt;
1726         int cvt_idx, pin_idx, err;
1727         int keep_power = 0;
1728
1729         /*
1730          * Power-up will call hdmi_present_sense, so the PM calls
1731          * have to be done without mutex held.
1732          */
1733
1734         err = snd_hda_power_up_pm(codec);
1735         if (err < 0 && err != -EACCES) {
1736                 codec_err(codec,
1737                           "Failed to power up codec for silent stream enable ret=[%d]\n", err);
1738                 snd_hda_power_down_pm(codec);
1739                 return;
1740         }
1741
1742         mutex_lock(&per_pin->lock);
1743
1744         if (per_pin->setup) {
1745                 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1746                 err = -EBUSY;
1747                 goto unlock_out;
1748         }
1749
1750         pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1751         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1752         if (err) {
1753                 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1754                 goto unlock_out;
1755         }
1756
1757         per_cvt = get_cvt(spec, cvt_idx);
1758         per_cvt->assigned = 1;
1759         per_pin->cvt_nid = per_cvt->cvt_nid;
1760         per_pin->silent_stream = true;
1761
1762         codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1763                   per_pin->pin_nid, per_cvt->cvt_nid);
1764
1765         snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1766         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1767                                   AC_VERB_SET_CONNECT_SEL,
1768                                   per_pin->mux_idx);
1769
1770         /* configure unused pins to choose other converters */
1771         pin_cvt_fixup(codec, per_pin, 0);
1772
1773         switch (spec->silent_stream_type) {
1774         case SILENT_STREAM_KAE:
1775                 silent_stream_set_kae(codec, per_pin, true);
1776                 break;
1777         case SILENT_STREAM_I915:
1778                 silent_stream_enable_i915(codec, per_pin);
1779                 keep_power = 1;
1780                 break;
1781         default:
1782                 break;
1783         }
1784
1785  unlock_out:
1786         mutex_unlock(&per_pin->lock);
1787
1788         if (err || !keep_power)
1789                 snd_hda_power_down_pm(codec);
1790 }
1791
1792 static void silent_stream_disable(struct hda_codec *codec,
1793                                   struct hdmi_spec_per_pin *per_pin)
1794 {
1795         struct hdmi_spec *spec = codec->spec;
1796         struct hdmi_spec_per_cvt *per_cvt;
1797         int cvt_idx, err;
1798
1799         err = snd_hda_power_up_pm(codec);
1800         if (err < 0 && err != -EACCES) {
1801                 codec_err(codec,
1802                           "Failed to power up codec for silent stream disable ret=[%d]\n",
1803                           err);
1804                 snd_hda_power_down_pm(codec);
1805                 return;
1806         }
1807
1808         mutex_lock(&per_pin->lock);
1809         if (!per_pin->silent_stream)
1810                 goto unlock_out;
1811
1812         codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1813                   per_pin->pin_nid, per_pin->cvt_nid);
1814
1815         cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1816         if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1817                 per_cvt = get_cvt(spec, cvt_idx);
1818                 per_cvt->assigned = 0;
1819         }
1820
1821         if (spec->silent_stream_type == SILENT_STREAM_I915) {
1822                 /* release ref taken in silent_stream_enable() */
1823                 snd_hda_power_down_pm(codec);
1824         } else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
1825                 silent_stream_set_kae(codec, per_pin, false);
1826         }
1827
1828         per_pin->cvt_nid = 0;
1829         per_pin->silent_stream = false;
1830
1831  unlock_out:
1832         mutex_unlock(&per_pin->lock);
1833
1834         snd_hda_power_down_pm(codec);
1835 }
1836
1837 /* update ELD and jack state via audio component */
1838 static void sync_eld_via_acomp(struct hda_codec *codec,
1839                                struct hdmi_spec_per_pin *per_pin)
1840 {
1841         struct hdmi_spec *spec = codec->spec;
1842         struct hdmi_eld *eld = &spec->temp_eld;
1843         bool monitor_prev, monitor_next;
1844
1845         mutex_lock(&per_pin->lock);
1846         eld->monitor_present = false;
1847         monitor_prev = per_pin->sink_eld.monitor_present;
1848         eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1849                                       per_pin->dev_id, &eld->monitor_present,
1850                                       eld->eld_buffer, ELD_MAX_SIZE);
1851         eld->eld_valid = (eld->eld_size > 0);
1852         update_eld(codec, per_pin, eld, 0);
1853         monitor_next = per_pin->sink_eld.monitor_present;
1854         mutex_unlock(&per_pin->lock);
1855
1856         if (spec->silent_stream_type) {
1857                 if (!monitor_prev && monitor_next)
1858                         silent_stream_enable(codec, per_pin);
1859                 else if (monitor_prev && !monitor_next)
1860                         silent_stream_disable(codec, per_pin);
1861         }
1862 }
1863
1864 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1865 {
1866         struct hda_codec *codec = per_pin->codec;
1867
1868         if (!codec_has_acomp(codec))
1869                 hdmi_present_sense_via_verbs(per_pin, repoll);
1870         else
1871                 sync_eld_via_acomp(codec, per_pin);
1872 }
1873
1874 static void hdmi_repoll_eld(struct work_struct *work)
1875 {
1876         struct hdmi_spec_per_pin *per_pin =
1877         container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1878         struct hda_codec *codec = per_pin->codec;
1879         struct hdmi_spec *spec = codec->spec;
1880         struct hda_jack_tbl *jack;
1881
1882         jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1883                                         per_pin->dev_id);
1884         if (jack)
1885                 jack->jack_dirty = 1;
1886
1887         if (per_pin->repoll_count++ > 6)
1888                 per_pin->repoll_count = 0;
1889
1890         mutex_lock(&spec->pcm_lock);
1891         hdmi_present_sense(per_pin, per_pin->repoll_count);
1892         mutex_unlock(&spec->pcm_lock);
1893 }
1894
1895 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1896 {
1897         struct hdmi_spec *spec = codec->spec;
1898         unsigned int caps, config;
1899         int pin_idx;
1900         struct hdmi_spec_per_pin *per_pin;
1901         int err;
1902         int dev_num, i;
1903
1904         caps = snd_hda_query_pin_caps(codec, pin_nid);
1905         if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1906                 return 0;
1907
1908         /*
1909          * For DP MST audio, Configuration Default is the same for
1910          * all device entries on the same pin
1911          */
1912         config = snd_hda_codec_get_pincfg(codec, pin_nid);
1913         if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1914             !spec->force_connect)
1915                 return 0;
1916
1917         /*
1918          * To simplify the implementation, malloc all
1919          * the virtual pins in the initialization statically
1920          */
1921         if (spec->intel_hsw_fixup) {
1922                 /*
1923                  * On Intel platforms, device entries count returned
1924                  * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
1925                  * the type of receiver that is connected. Allocate pin
1926                  * structures based on worst case.
1927                  */
1928                 dev_num = spec->dev_num;
1929         } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1930                 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1931                 /*
1932                  * spec->dev_num is the maxinum number of device entries
1933                  * among all the pins
1934                  */
1935                 spec->dev_num = (spec->dev_num > dev_num) ?
1936                         spec->dev_num : dev_num;
1937         } else {
1938                 /*
1939                  * If the platform doesn't support DP MST,
1940                  * manually set dev_num to 1. This means
1941                  * the pin has only one device entry.
1942                  */
1943                 dev_num = 1;
1944                 spec->dev_num = 1;
1945         }
1946
1947         for (i = 0; i < dev_num; i++) {
1948                 pin_idx = spec->num_pins;
1949                 per_pin = snd_array_new(&spec->pins);
1950
1951                 if (!per_pin)
1952                         return -ENOMEM;
1953
1954                 if (spec->dyn_pcm_assign) {
1955                         per_pin->pcm = NULL;
1956                         per_pin->pcm_idx = -1;
1957                 } else {
1958                         per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1959                         per_pin->pcm_idx = pin_idx;
1960                 }
1961                 per_pin->pin_nid = pin_nid;
1962                 per_pin->pin_nid_idx = spec->num_nids;
1963                 per_pin->dev_id = i;
1964                 per_pin->non_pcm = false;
1965                 snd_hda_set_dev_select(codec, pin_nid, i);
1966                 err = hdmi_read_pin_conn(codec, pin_idx);
1967                 if (err < 0)
1968                         return err;
1969                 spec->num_pins++;
1970         }
1971         spec->num_nids++;
1972
1973         return 0;
1974 }
1975
1976 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1977 {
1978         struct hdmi_spec *spec = codec->spec;
1979         struct hdmi_spec_per_cvt *per_cvt;
1980         unsigned int chans;
1981         int err;
1982
1983         chans = get_wcaps(codec, cvt_nid);
1984         chans = get_wcaps_channels(chans);
1985
1986         per_cvt = snd_array_new(&spec->cvts);
1987         if (!per_cvt)
1988                 return -ENOMEM;
1989
1990         per_cvt->cvt_nid = cvt_nid;
1991         per_cvt->channels_min = 2;
1992         if (chans <= 16) {
1993                 per_cvt->channels_max = chans;
1994                 if (chans > spec->chmap.channels_max)
1995                         spec->chmap.channels_max = chans;
1996         }
1997
1998         err = snd_hda_query_supported_pcm(codec, cvt_nid,
1999                                           &per_cvt->rates,
2000                                           &per_cvt->formats,
2001                                           &per_cvt->maxbps);
2002         if (err < 0)
2003                 return err;
2004
2005         if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
2006                 spec->cvt_nids[spec->num_cvts] = cvt_nid;
2007         spec->num_cvts++;
2008
2009         return 0;
2010 }
2011
2012 static const struct snd_pci_quirk force_connect_list[] = {
2013         SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
2014         SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
2015         SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
2016         SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
2017         {}
2018 };
2019
2020 static int hdmi_parse_codec(struct hda_codec *codec)
2021 {
2022         struct hdmi_spec *spec = codec->spec;
2023         hda_nid_t start_nid;
2024         unsigned int caps;
2025         int i, nodes;
2026         const struct snd_pci_quirk *q;
2027
2028         nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
2029         if (!start_nid || nodes < 0) {
2030                 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
2031                 return -EINVAL;
2032         }
2033
2034         if (enable_all_pins)
2035                 spec->force_connect = true;
2036
2037         q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
2038
2039         if (q && q->value)
2040                 spec->force_connect = true;
2041
2042         /*
2043          * hdmi_add_pin() assumes total amount of converters to
2044          * be known, so first discover all converters
2045          */
2046         for (i = 0; i < nodes; i++) {
2047                 hda_nid_t nid = start_nid + i;
2048
2049                 caps = get_wcaps(codec, nid);
2050
2051                 if (!(caps & AC_WCAP_DIGITAL))
2052                         continue;
2053
2054                 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2055                         hdmi_add_cvt(codec, nid);
2056         }
2057
2058         /* discover audio pins */
2059         for (i = 0; i < nodes; i++) {
2060                 hda_nid_t nid = start_nid + i;
2061
2062                 caps = get_wcaps(codec, nid);
2063
2064                 if (!(caps & AC_WCAP_DIGITAL))
2065                         continue;
2066
2067                 if (get_wcaps_type(caps) == AC_WID_PIN)
2068                         hdmi_add_pin(codec, nid);
2069         }
2070
2071         return 0;
2072 }
2073
2074 /*
2075  */
2076 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2077 {
2078         struct hda_spdif_out *spdif;
2079         bool non_pcm;
2080
2081         mutex_lock(&codec->spdif_mutex);
2082         spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2083         /* Add sanity check to pass klockwork check.
2084          * This should never happen.
2085          */
2086         if (WARN_ON(spdif == NULL)) {
2087                 mutex_unlock(&codec->spdif_mutex);
2088                 return true;
2089         }
2090         non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2091         mutex_unlock(&codec->spdif_mutex);
2092         return non_pcm;
2093 }
2094
2095 /*
2096  * HDMI callbacks
2097  */
2098
2099 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2100                                            struct hda_codec *codec,
2101                                            unsigned int stream_tag,
2102                                            unsigned int format,
2103                                            struct snd_pcm_substream *substream)
2104 {
2105         hda_nid_t cvt_nid = hinfo->nid;
2106         struct hdmi_spec *spec = codec->spec;
2107         int pin_idx;
2108         struct hdmi_spec_per_pin *per_pin;
2109         struct snd_pcm_runtime *runtime = substream->runtime;
2110         bool non_pcm;
2111         int pinctl, stripe;
2112         int err = 0;
2113
2114         mutex_lock(&spec->pcm_lock);
2115         pin_idx = hinfo_to_pin_index(codec, hinfo);
2116         if (spec->dyn_pcm_assign && pin_idx < 0) {
2117                 /* when dyn_pcm_assign and pcm is not bound to a pin
2118                  * skip pin setup and return 0 to make audio playback
2119                  * be ongoing
2120                  */
2121                 pin_cvt_fixup(codec, NULL, cvt_nid);
2122                 snd_hda_codec_setup_stream(codec, cvt_nid,
2123                                         stream_tag, 0, format);
2124                 goto unlock;
2125         }
2126
2127         if (snd_BUG_ON(pin_idx < 0)) {
2128                 err = -EINVAL;
2129                 goto unlock;
2130         }
2131         per_pin = get_pin(spec, pin_idx);
2132
2133         /* Verify pin:cvt selections to avoid silent audio after S3.
2134          * After S3, the audio driver restores pin:cvt selections
2135          * but this can happen before gfx is ready and such selection
2136          * is overlooked by HW. Thus multiple pins can share a same
2137          * default convertor and mute control will affect each other,
2138          * which can cause a resumed audio playback become silent
2139          * after S3.
2140          */
2141         pin_cvt_fixup(codec, per_pin, 0);
2142
2143         /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2144         /* Todo: add DP1.2 MST audio support later */
2145         if (codec_has_acomp(codec))
2146                 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2147                                          per_pin->dev_id, runtime->rate);
2148
2149         non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2150         mutex_lock(&per_pin->lock);
2151         per_pin->channels = substream->runtime->channels;
2152         per_pin->setup = true;
2153
2154         if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2155                 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2156                                                         substream);
2157                 snd_hda_codec_write(codec, cvt_nid, 0,
2158                                     AC_VERB_SET_STRIPE_CONTROL,
2159                                     stripe);
2160         }
2161
2162         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2163         mutex_unlock(&per_pin->lock);
2164         if (spec->dyn_pin_out) {
2165                 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2166                                        per_pin->dev_id);
2167                 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2168                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2169                 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2170                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
2171                                     pinctl | PIN_OUT);
2172         }
2173
2174         /* snd_hda_set_dev_select() has been called before */
2175         err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2176                                      per_pin->dev_id, stream_tag, format);
2177  unlock:
2178         mutex_unlock(&spec->pcm_lock);
2179         return err;
2180 }
2181
2182 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2183                                              struct hda_codec *codec,
2184                                              struct snd_pcm_substream *substream)
2185 {
2186         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2187         return 0;
2188 }
2189
2190 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2191                           struct hda_codec *codec,
2192                           struct snd_pcm_substream *substream)
2193 {
2194         struct hdmi_spec *spec = codec->spec;
2195         int cvt_idx, pin_idx, pcm_idx;
2196         struct hdmi_spec_per_cvt *per_cvt;
2197         struct hdmi_spec_per_pin *per_pin;
2198         int pinctl;
2199         int err = 0;
2200
2201         mutex_lock(&spec->pcm_lock);
2202         if (hinfo->nid) {
2203                 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2204                 if (snd_BUG_ON(pcm_idx < 0)) {
2205                         err = -EINVAL;
2206                         goto unlock;
2207                 }
2208                 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2209                 if (snd_BUG_ON(cvt_idx < 0)) {
2210                         err = -EINVAL;
2211                         goto unlock;
2212                 }
2213                 per_cvt = get_cvt(spec, cvt_idx);
2214                 per_cvt->assigned = 0;
2215                 hinfo->nid = 0;
2216
2217                 azx_stream(get_azx_dev(substream))->stripe = 0;
2218
2219                 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2220                 clear_bit(pcm_idx, &spec->pcm_in_use);
2221                 pin_idx = hinfo_to_pin_index(codec, hinfo);
2222                 if (spec->dyn_pcm_assign && pin_idx < 0)
2223                         goto unlock;
2224
2225                 if (snd_BUG_ON(pin_idx < 0)) {
2226                         err = -EINVAL;
2227                         goto unlock;
2228                 }
2229                 per_pin = get_pin(spec, pin_idx);
2230
2231                 if (spec->dyn_pin_out) {
2232                         snd_hda_set_dev_select(codec, per_pin->pin_nid,
2233                                                per_pin->dev_id);
2234                         pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2235                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2236                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2237                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
2238                                             pinctl & ~PIN_OUT);
2239                 }
2240
2241                 mutex_lock(&per_pin->lock);
2242                 per_pin->chmap_set = false;
2243                 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2244
2245                 per_pin->setup = false;
2246                 per_pin->channels = 0;
2247                 mutex_unlock(&per_pin->lock);
2248         }
2249
2250 unlock:
2251         mutex_unlock(&spec->pcm_lock);
2252
2253         return err;
2254 }
2255
2256 static const struct hda_pcm_ops generic_ops = {
2257         .open = hdmi_pcm_open,
2258         .close = hdmi_pcm_close,
2259         .prepare = generic_hdmi_playback_pcm_prepare,
2260         .cleanup = generic_hdmi_playback_pcm_cleanup,
2261 };
2262
2263 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2264 {
2265         struct hda_codec *codec = hdac_to_hda_codec(hdac);
2266         struct hdmi_spec *spec = codec->spec;
2267         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2268
2269         if (!per_pin)
2270                 return 0;
2271
2272         return per_pin->sink_eld.info.spk_alloc;
2273 }
2274
2275 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2276                                         unsigned char *chmap)
2277 {
2278         struct hda_codec *codec = hdac_to_hda_codec(hdac);
2279         struct hdmi_spec *spec = codec->spec;
2280         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2281
2282         /* chmap is already set to 0 in caller */
2283         if (!per_pin)
2284                 return;
2285
2286         memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2287 }
2288
2289 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2290                                 unsigned char *chmap, int prepared)
2291 {
2292         struct hda_codec *codec = hdac_to_hda_codec(hdac);
2293         struct hdmi_spec *spec = codec->spec;
2294         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2295
2296         if (!per_pin)
2297                 return;
2298         mutex_lock(&per_pin->lock);
2299         per_pin->chmap_set = true;
2300         memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2301         if (prepared)
2302                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2303         mutex_unlock(&per_pin->lock);
2304 }
2305
2306 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2307 {
2308         struct hda_codec *codec = hdac_to_hda_codec(hdac);
2309         struct hdmi_spec *spec = codec->spec;
2310         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2311
2312         return per_pin ? true:false;
2313 }
2314
2315 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2316 {
2317         struct hdmi_spec *spec = codec->spec;
2318         int idx, pcm_num;
2319
2320         /*
2321          * for non-mst mode, pcm number is the same as before
2322          * for DP MST mode without extra PCM, pcm number is same
2323          * for DP MST mode with extra PCMs, pcm number is
2324          *  (nid number + dev_num - 1)
2325          * dev_num is the device entry number in a pin
2326          */
2327
2328         if (codec->mst_no_extra_pcms)
2329                 pcm_num = spec->num_nids;
2330         else
2331                 pcm_num = spec->num_nids + spec->dev_num - 1;
2332
2333         codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2334
2335         for (idx = 0; idx < pcm_num; idx++) {
2336                 struct hda_pcm *info;
2337                 struct hda_pcm_stream *pstr;
2338
2339                 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2340                 if (!info)
2341                         return -ENOMEM;
2342
2343                 spec->pcm_rec[idx].pcm = info;
2344                 spec->pcm_used++;
2345                 info->pcm_type = HDA_PCM_TYPE_HDMI;
2346                 info->own_chmap = true;
2347
2348                 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2349                 pstr->substreams = 1;
2350                 pstr->ops = generic_ops;
2351                 /* pcm number is less than 16 */
2352                 if (spec->pcm_used >= 16)
2353                         break;
2354                 /* other pstr fields are set in open */
2355         }
2356
2357         return 0;
2358 }
2359
2360 static void free_hdmi_jack_priv(struct snd_jack *jack)
2361 {
2362         struct hdmi_pcm *pcm = jack->private_data;
2363
2364         pcm->jack = NULL;
2365 }
2366
2367 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2368 {
2369         char hdmi_str[32] = "HDMI/DP";
2370         struct hdmi_spec *spec = codec->spec;
2371         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2372         struct snd_jack *jack;
2373         int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2374         int err;
2375
2376         if (pcmdev > 0)
2377                 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2378         if (!spec->dyn_pcm_assign &&
2379             !is_jack_detectable(codec, per_pin->pin_nid))
2380                 strncat(hdmi_str, " Phantom",
2381                         sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2382
2383         err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2384                            true, false);
2385         if (err < 0)
2386                 return err;
2387
2388         spec->pcm_rec[pcm_idx].jack = jack;
2389         jack->private_data = &spec->pcm_rec[pcm_idx];
2390         jack->private_free = free_hdmi_jack_priv;
2391         return 0;
2392 }
2393
2394 static int generic_hdmi_build_controls(struct hda_codec *codec)
2395 {
2396         struct hdmi_spec *spec = codec->spec;
2397         int dev, err;
2398         int pin_idx, pcm_idx;
2399
2400         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2401                 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2402                         /* no PCM: mark this for skipping permanently */
2403                         set_bit(pcm_idx, &spec->pcm_bitmap);
2404                         continue;
2405                 }
2406
2407                 err = generic_hdmi_build_jack(codec, pcm_idx);
2408                 if (err < 0)
2409                         return err;
2410
2411                 /* create the spdif for each pcm
2412                  * pin will be bound when monitor is connected
2413                  */
2414                 if (spec->dyn_pcm_assign)
2415                         err = snd_hda_create_dig_out_ctls(codec,
2416                                           0, spec->cvt_nids[0],
2417                                           HDA_PCM_TYPE_HDMI);
2418                 else {
2419                         struct hdmi_spec_per_pin *per_pin =
2420                                 get_pin(spec, pcm_idx);
2421                         err = snd_hda_create_dig_out_ctls(codec,
2422                                                   per_pin->pin_nid,
2423                                                   per_pin->mux_nids[0],
2424                                                   HDA_PCM_TYPE_HDMI);
2425                 }
2426                 if (err < 0)
2427                         return err;
2428                 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2429
2430                 dev = get_pcm_rec(spec, pcm_idx)->device;
2431                 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2432                         /* add control for ELD Bytes */
2433                         err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2434                         if (err < 0)
2435                                 return err;
2436                 }
2437         }
2438
2439         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2440                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2441                 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2442
2443                 pin_eld->eld_valid = false;
2444                 hdmi_present_sense(per_pin, 0);
2445         }
2446
2447         /* add channel maps */
2448         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2449                 struct hda_pcm *pcm;
2450
2451                 pcm = get_pcm_rec(spec, pcm_idx);
2452                 if (!pcm || !pcm->pcm)
2453                         break;
2454                 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2455                 if (err < 0)
2456                         return err;
2457         }
2458
2459         return 0;
2460 }
2461
2462 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2463 {
2464         struct hdmi_spec *spec = codec->spec;
2465         int pin_idx;
2466
2467         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2468                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2469
2470                 per_pin->codec = codec;
2471                 mutex_init(&per_pin->lock);
2472                 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2473                 eld_proc_new(per_pin, pin_idx);
2474         }
2475         return 0;
2476 }
2477
2478 static int generic_hdmi_init(struct hda_codec *codec)
2479 {
2480         struct hdmi_spec *spec = codec->spec;
2481         int pin_idx;
2482
2483         mutex_lock(&spec->bind_lock);
2484         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2485                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2486                 hda_nid_t pin_nid = per_pin->pin_nid;
2487                 int dev_id = per_pin->dev_id;
2488
2489                 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2490                 hdmi_init_pin(codec, pin_nid);
2491                 if (codec_has_acomp(codec))
2492                         continue;
2493                 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2494                                                         jack_callback);
2495         }
2496         mutex_unlock(&spec->bind_lock);
2497         return 0;
2498 }
2499
2500 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2501 {
2502         snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2503         snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2504 }
2505
2506 static void hdmi_array_free(struct hdmi_spec *spec)
2507 {
2508         snd_array_free(&spec->pins);
2509         snd_array_free(&spec->cvts);
2510 }
2511
2512 static void generic_spec_free(struct hda_codec *codec)
2513 {
2514         struct hdmi_spec *spec = codec->spec;
2515
2516         if (spec) {
2517                 hdmi_array_free(spec);
2518                 kfree(spec);
2519                 codec->spec = NULL;
2520         }
2521         codec->dp_mst = false;
2522 }
2523
2524 static void generic_hdmi_free(struct hda_codec *codec)
2525 {
2526         struct hdmi_spec *spec = codec->spec;
2527         int pin_idx, pcm_idx;
2528
2529         if (spec->acomp_registered) {
2530                 snd_hdac_acomp_exit(&codec->bus->core);
2531         } else if (codec_has_acomp(codec)) {
2532                 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2533         }
2534         codec->relaxed_resume = 0;
2535
2536         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2537                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2538                 cancel_delayed_work_sync(&per_pin->work);
2539                 eld_proc_free(per_pin);
2540         }
2541
2542         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2543                 if (spec->pcm_rec[pcm_idx].jack == NULL)
2544                         continue;
2545                 if (spec->dyn_pcm_assign)
2546                         snd_device_free(codec->card,
2547                                         spec->pcm_rec[pcm_idx].jack);
2548                 else
2549                         spec->pcm_rec[pcm_idx].jack = NULL;
2550         }
2551
2552         generic_spec_free(codec);
2553 }
2554
2555 #ifdef CONFIG_PM
2556 static int generic_hdmi_suspend(struct hda_codec *codec)
2557 {
2558         struct hdmi_spec *spec = codec->spec;
2559         int pin_idx;
2560
2561         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2562                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2563                 cancel_delayed_work_sync(&per_pin->work);
2564         }
2565         return 0;
2566 }
2567
2568 static int generic_hdmi_resume(struct hda_codec *codec)
2569 {
2570         struct hdmi_spec *spec = codec->spec;
2571         int pin_idx;
2572
2573         codec->patch_ops.init(codec);
2574         snd_hda_regmap_sync(codec);
2575
2576         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2577                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2578                 hdmi_present_sense(per_pin, 1);
2579         }
2580         return 0;
2581 }
2582 #endif
2583
2584 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2585         .init                   = generic_hdmi_init,
2586         .free                   = generic_hdmi_free,
2587         .build_pcms             = generic_hdmi_build_pcms,
2588         .build_controls         = generic_hdmi_build_controls,
2589         .unsol_event            = hdmi_unsol_event,
2590 #ifdef CONFIG_PM
2591         .suspend                = generic_hdmi_suspend,
2592         .resume                 = generic_hdmi_resume,
2593 #endif
2594 };
2595
2596 static const struct hdmi_ops generic_standard_hdmi_ops = {
2597         .pin_get_eld                            = hdmi_pin_get_eld,
2598         .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2599         .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2600         .setup_stream                           = hdmi_setup_stream,
2601 };
2602
2603 /* allocate codec->spec and assign/initialize generic parser ops */
2604 static int alloc_generic_hdmi(struct hda_codec *codec)
2605 {
2606         struct hdmi_spec *spec;
2607
2608         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2609         if (!spec)
2610                 return -ENOMEM;
2611
2612         spec->codec = codec;
2613         spec->ops = generic_standard_hdmi_ops;
2614         spec->dev_num = 1;      /* initialize to 1 */
2615         mutex_init(&spec->pcm_lock);
2616         mutex_init(&spec->bind_lock);
2617         snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2618
2619         spec->chmap.ops.get_chmap = hdmi_get_chmap;
2620         spec->chmap.ops.set_chmap = hdmi_set_chmap;
2621         spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2622         spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2623
2624         codec->spec = spec;
2625         hdmi_array_init(spec, 4);
2626
2627         codec->patch_ops = generic_hdmi_patch_ops;
2628
2629         return 0;
2630 }
2631
2632 /* generic HDMI parser */
2633 static int patch_generic_hdmi(struct hda_codec *codec)
2634 {
2635         int err;
2636
2637         err = alloc_generic_hdmi(codec);
2638         if (err < 0)
2639                 return err;
2640
2641         err = hdmi_parse_codec(codec);
2642         if (err < 0) {
2643                 generic_spec_free(codec);
2644                 return err;
2645         }
2646
2647         generic_hdmi_init_per_pins(codec);
2648         return 0;
2649 }
2650
2651 /*
2652  * generic audio component binding
2653  */
2654
2655 /* turn on / off the unsol event jack detection dynamically */
2656 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2657                                   int dev_id, bool use_acomp)
2658 {
2659         struct hda_jack_tbl *tbl;
2660
2661         tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2662         if (tbl) {
2663                 /* clear unsol even if component notifier is used, or re-enable
2664                  * if notifier is cleared
2665                  */
2666                 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2667                 snd_hda_codec_write_cache(codec, nid, 0,
2668                                           AC_VERB_SET_UNSOLICITED_ENABLE, val);
2669         }
2670 }
2671
2672 /* set up / clear component notifier dynamically */
2673 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2674                                        bool use_acomp)
2675 {
2676         struct hdmi_spec *spec;
2677         int i;
2678
2679         spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2680         mutex_lock(&spec->bind_lock);
2681         spec->use_acomp_notifier = use_acomp;
2682         spec->codec->relaxed_resume = use_acomp;
2683         spec->codec->bus->keep_power = 0;
2684         /* reprogram each jack detection logic depending on the notifier */
2685         for (i = 0; i < spec->num_pins; i++)
2686                 reprogram_jack_detect(spec->codec,
2687                                       get_pin(spec, i)->pin_nid,
2688                                       get_pin(spec, i)->dev_id,
2689                                       use_acomp);
2690         mutex_unlock(&spec->bind_lock);
2691 }
2692
2693 /* enable / disable the notifier via master bind / unbind */
2694 static int generic_acomp_master_bind(struct device *dev,
2695                                      struct drm_audio_component *acomp)
2696 {
2697         generic_acomp_notifier_set(acomp, true);
2698         return 0;
2699 }
2700
2701 static void generic_acomp_master_unbind(struct device *dev,
2702                                         struct drm_audio_component *acomp)
2703 {
2704         generic_acomp_notifier_set(acomp, false);
2705 }
2706
2707 /* check whether both HD-audio and DRM PCI devices belong to the same bus */
2708 static int match_bound_vga(struct device *dev, int subtype, void *data)
2709 {
2710         struct hdac_bus *bus = data;
2711         struct pci_dev *pci, *master;
2712
2713         if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2714                 return 0;
2715         master = to_pci_dev(bus->dev);
2716         pci = to_pci_dev(dev);
2717         return master->bus == pci->bus;
2718 }
2719
2720 /* audio component notifier for AMD/Nvidia HDMI codecs */
2721 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2722 {
2723         struct hda_codec *codec = audio_ptr;
2724         struct hdmi_spec *spec = codec->spec;
2725         hda_nid_t pin_nid = spec->port2pin(codec, port);
2726
2727         if (!pin_nid)
2728                 return;
2729         if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2730                 return;
2731         /* skip notification during system suspend (but not in runtime PM);
2732          * the state will be updated at resume
2733          */
2734         if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2735                 return;
2736         /* ditto during suspend/resume process itself */
2737         if (snd_hdac_is_in_pm(&codec->core))
2738                 return;
2739
2740         check_presence_and_report(codec, pin_nid, dev_id);
2741 }
2742
2743 /* set up the private drm_audio_ops from the template */
2744 static void setup_drm_audio_ops(struct hda_codec *codec,
2745                                 const struct drm_audio_component_audio_ops *ops)
2746 {
2747         struct hdmi_spec *spec = codec->spec;
2748
2749         spec->drm_audio_ops.audio_ptr = codec;
2750         /* intel_audio_codec_enable() or intel_audio_codec_disable()
2751          * will call pin_eld_notify with using audio_ptr pointer
2752          * We need make sure audio_ptr is really setup
2753          */
2754         wmb();
2755         spec->drm_audio_ops.pin2port = ops->pin2port;
2756         spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2757         spec->drm_audio_ops.master_bind = ops->master_bind;
2758         spec->drm_audio_ops.master_unbind = ops->master_unbind;
2759 }
2760
2761 /* initialize the generic HDMI audio component */
2762 static void generic_acomp_init(struct hda_codec *codec,
2763                                const struct drm_audio_component_audio_ops *ops,
2764                                int (*port2pin)(struct hda_codec *, int))
2765 {
2766         struct hdmi_spec *spec = codec->spec;
2767
2768         if (!enable_acomp) {
2769                 codec_info(codec, "audio component disabled by module option\n");
2770                 return;
2771         }
2772
2773         spec->port2pin = port2pin;
2774         setup_drm_audio_ops(codec, ops);
2775         if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2776                                  match_bound_vga, 0)) {
2777                 spec->acomp_registered = true;
2778         }
2779 }
2780
2781 /*
2782  * Intel codec parsers and helpers
2783  */
2784
2785 #define INTEL_GET_VENDOR_VERB   0xf81
2786 #define INTEL_SET_VENDOR_VERB   0x781
2787 #define INTEL_EN_DP12           0x02    /* enable DP 1.2 features */
2788 #define INTEL_EN_ALL_PIN_CVTS   0x01    /* enable 2nd & 3rd pins and convertors */
2789
2790 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2791                                           bool update_tree)
2792 {
2793         unsigned int vendor_param;
2794         struct hdmi_spec *spec = codec->spec;
2795
2796         vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2797                                 INTEL_GET_VENDOR_VERB, 0);
2798         if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2799                 return;
2800
2801         vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2802         vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2803                                 INTEL_SET_VENDOR_VERB, vendor_param);
2804         if (vendor_param == -1)
2805                 return;
2806
2807         if (update_tree)
2808                 snd_hda_codec_update_widgets(codec);
2809 }
2810
2811 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2812 {
2813         unsigned int vendor_param;
2814         struct hdmi_spec *spec = codec->spec;
2815
2816         vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2817                                 INTEL_GET_VENDOR_VERB, 0);
2818         if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2819                 return;
2820
2821         /* enable DP1.2 mode */
2822         vendor_param |= INTEL_EN_DP12;
2823         snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2824         snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2825                                 INTEL_SET_VENDOR_VERB, vendor_param);
2826 }
2827
2828 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2829  * Otherwise you may get severe h/w communication errors.
2830  */
2831 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2832                                 unsigned int power_state)
2833 {
2834         if (power_state == AC_PWRST_D0) {
2835                 intel_haswell_enable_all_pins(codec, false);
2836                 intel_haswell_fixup_enable_dp12(codec);
2837         }
2838
2839         snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2840         snd_hda_codec_set_power_to_all(codec, fg, power_state);
2841 }
2842
2843 /* There is a fixed mapping between audio pin node and display port.
2844  * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2845  * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2846  * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2847  * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2848  *
2849  * on VLV, ILK:
2850  * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2851  * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2852  * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2853  */
2854 static int intel_base_nid(struct hda_codec *codec)
2855 {
2856         switch (codec->core.vendor_id) {
2857         case 0x80860054: /* ILK */
2858         case 0x80862804: /* ILK */
2859         case 0x80862882: /* VLV */
2860                 return 4;
2861         default:
2862                 return 5;
2863         }
2864 }
2865
2866 static int intel_pin2port(void *audio_ptr, int pin_nid)
2867 {
2868         struct hda_codec *codec = audio_ptr;
2869         struct hdmi_spec *spec = codec->spec;
2870         int base_nid, i;
2871
2872         if (!spec->port_num) {
2873                 base_nid = intel_base_nid(codec);
2874                 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2875                         return -1;
2876                 return pin_nid - base_nid + 1;
2877         }
2878
2879         /*
2880          * looking for the pin number in the mapping table and return
2881          * the index which indicate the port number
2882          */
2883         for (i = 0; i < spec->port_num; i++) {
2884                 if (pin_nid == spec->port_map[i])
2885                         return i;
2886         }
2887
2888         codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2889         return -1;
2890 }
2891
2892 static int intel_port2pin(struct hda_codec *codec, int port)
2893 {
2894         struct hdmi_spec *spec = codec->spec;
2895
2896         if (!spec->port_num) {
2897                 /* we assume only from port-B to port-D */
2898                 if (port < 1 || port > 3)
2899                         return 0;
2900                 return port + intel_base_nid(codec) - 1;
2901         }
2902
2903         if (port < 0 || port >= spec->port_num)
2904                 return 0;
2905         return spec->port_map[port];
2906 }
2907
2908 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2909 {
2910         struct hda_codec *codec = audio_ptr;
2911         int pin_nid;
2912         int dev_id = pipe;
2913
2914         pin_nid = intel_port2pin(codec, port);
2915         if (!pin_nid)
2916                 return;
2917         /* skip notification during system suspend (but not in runtime PM);
2918          * the state will be updated at resume
2919          */
2920         if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2921                 return;
2922         /* ditto during suspend/resume process itself */
2923         if (snd_hdac_is_in_pm(&codec->core))
2924                 return;
2925
2926         snd_hdac_i915_set_bclk(&codec->bus->core);
2927         check_presence_and_report(codec, pin_nid, dev_id);
2928 }
2929
2930 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2931         .pin2port = intel_pin2port,
2932         .pin_eld_notify = intel_pin_eld_notify,
2933 };
2934
2935 /* register i915 component pin_eld_notify callback */
2936 static void register_i915_notifier(struct hda_codec *codec)
2937 {
2938         struct hdmi_spec *spec = codec->spec;
2939
2940         spec->use_acomp_notifier = true;
2941         spec->port2pin = intel_port2pin;
2942         setup_drm_audio_ops(codec, &intel_audio_ops);
2943         snd_hdac_acomp_register_notifier(&codec->bus->core,
2944                                         &spec->drm_audio_ops);
2945         /* no need for forcible resume for jack check thanks to notifier */
2946         codec->relaxed_resume = 1;
2947 }
2948
2949 /* setup_stream ops override for HSW+ */
2950 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2951                                  hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2952                                  int format)
2953 {
2954         haswell_verify_D0(codec, cvt_nid, pin_nid);
2955         return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2956                                  stream_tag, format);
2957 }
2958
2959 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2960 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2961                                struct hdmi_spec_per_pin *per_pin,
2962                                hda_nid_t cvt_nid)
2963 {
2964         if (per_pin) {
2965                 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2966                 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2967                                per_pin->dev_id);
2968                 intel_verify_pin_cvt_connect(codec, per_pin);
2969                 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2970                                      per_pin->dev_id, per_pin->mux_idx);
2971         } else {
2972                 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2973         }
2974 }
2975
2976 /* precondition and allocation for Intel codecs */
2977 static int alloc_intel_hdmi(struct hda_codec *codec)
2978 {
2979         int err;
2980
2981         /* requires i915 binding */
2982         if (!codec->bus->core.audio_component) {
2983                 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2984                 /* set probe_id here to prevent generic fallback binding */
2985                 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2986                 return -ENODEV;
2987         }
2988
2989         err = alloc_generic_hdmi(codec);
2990         if (err < 0)
2991                 return err;
2992         /* no need to handle unsol events */
2993         codec->patch_ops.unsol_event = NULL;
2994         return 0;
2995 }
2996
2997 /* parse and post-process for Intel codecs */
2998 static int parse_intel_hdmi(struct hda_codec *codec)
2999 {
3000         int err, retries = 3;
3001
3002         do {
3003                 err = hdmi_parse_codec(codec);
3004         } while (err < 0 && retries--);
3005
3006         if (err < 0) {
3007                 generic_spec_free(codec);
3008                 return err;
3009         }
3010
3011         generic_hdmi_init_per_pins(codec);
3012         register_i915_notifier(codec);
3013         return 0;
3014 }
3015
3016 /* Intel Haswell and onwards; audio component with eld notifier */
3017 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
3018                                  const int *port_map, int port_num, int dev_num,
3019                                  bool send_silent_stream)
3020 {
3021         struct hdmi_spec *spec;
3022         int err;
3023
3024         err = alloc_intel_hdmi(codec);
3025         if (err < 0)
3026                 return err;
3027         spec = codec->spec;
3028         codec->dp_mst = true;
3029         spec->dyn_pcm_assign = true;
3030         spec->vendor_nid = vendor_nid;
3031         spec->port_map = port_map;
3032         spec->port_num = port_num;
3033         spec->intel_hsw_fixup = true;
3034         spec->dev_num = dev_num;
3035
3036         intel_haswell_enable_all_pins(codec, true);
3037         intel_haswell_fixup_enable_dp12(codec);
3038
3039         codec->display_power_control = 1;
3040
3041         codec->patch_ops.set_power_state = haswell_set_power_state;
3042         codec->depop_delay = 0;
3043         codec->auto_runtime_pm = 1;
3044
3045         spec->ops.setup_stream = i915_hsw_setup_stream;
3046         spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3047
3048         /*
3049          * Enable silent stream feature, if it is enabled via
3050          * module param or Kconfig option
3051          */
3052         if (send_silent_stream)
3053                 spec->silent_stream_type = SILENT_STREAM_I915;
3054
3055         return parse_intel_hdmi(codec);
3056 }
3057
3058 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3059 {
3060         return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
3061                                      enable_silent_stream);
3062 }
3063
3064 static int patch_i915_glk_hdmi(struct hda_codec *codec)
3065 {
3066         /*
3067          * Silent stream calls audio component .get_power() from
3068          * .pin_eld_notify(). On GLK this will deadlock in i915 due
3069          * to the audio vs. CDCLK workaround.
3070          */
3071         return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3072 }
3073
3074 static int patch_i915_icl_hdmi(struct hda_codec *codec)
3075 {
3076         /*
3077          * pin to port mapping table where the value indicate the pin number and
3078          * the index indicate the port number.
3079          */
3080         static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3081
3082         return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
3083                                      enable_silent_stream);
3084 }
3085
3086 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3087 {
3088         /*
3089          * pin to port mapping table where the value indicate the pin number and
3090          * the index indicate the port number.
3091          */
3092         static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3093         int ret;
3094
3095         ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
3096                                     enable_silent_stream);
3097         if (!ret) {
3098                 struct hdmi_spec *spec = codec->spec;
3099
3100                 spec->dyn_pcm_no_legacy = true;
3101         }
3102
3103         return ret;
3104 }
3105
3106 static int patch_i915_adlp_hdmi(struct hda_codec *codec)
3107 {
3108         struct hdmi_spec *spec;
3109         int res;
3110
3111         res = patch_i915_tgl_hdmi(codec);
3112         if (!res) {
3113                 spec = codec->spec;
3114
3115                 if (spec->silent_stream_type)
3116                         spec->silent_stream_type = SILENT_STREAM_KAE;
3117         }
3118
3119         return res;
3120 }
3121
3122 /* Intel Baytrail and Braswell; with eld notifier */
3123 static int patch_i915_byt_hdmi(struct hda_codec *codec)
3124 {
3125         struct hdmi_spec *spec;
3126         int err;
3127
3128         err = alloc_intel_hdmi(codec);
3129         if (err < 0)
3130                 return err;
3131         spec = codec->spec;
3132
3133         /* For Valleyview/Cherryview, only the display codec is in the display
3134          * power well and can use link_power ops to request/release the power.
3135          */
3136         codec->display_power_control = 1;
3137
3138         codec->depop_delay = 0;
3139         codec->auto_runtime_pm = 1;
3140
3141         spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3142
3143         return parse_intel_hdmi(codec);
3144 }
3145
3146 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3147 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3148 {
3149         int err;
3150
3151         err = alloc_intel_hdmi(codec);
3152         if (err < 0)
3153                 return err;
3154         return parse_intel_hdmi(codec);
3155 }
3156
3157 /*
3158  * Shared non-generic implementations
3159  */
3160
3161 static int simple_playback_build_pcms(struct hda_codec *codec)
3162 {
3163         struct hdmi_spec *spec = codec->spec;
3164         struct hda_pcm *info;
3165         unsigned int chans;
3166         struct hda_pcm_stream *pstr;
3167         struct hdmi_spec_per_cvt *per_cvt;
3168
3169         per_cvt = get_cvt(spec, 0);
3170         chans = get_wcaps(codec, per_cvt->cvt_nid);
3171         chans = get_wcaps_channels(chans);
3172
3173         info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3174         if (!info)
3175                 return -ENOMEM;
3176         spec->pcm_rec[0].pcm = info;
3177         info->pcm_type = HDA_PCM_TYPE_HDMI;
3178         pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3179         *pstr = spec->pcm_playback;
3180         pstr->nid = per_cvt->cvt_nid;
3181         if (pstr->channels_max <= 2 && chans && chans <= 16)
3182                 pstr->channels_max = chans;
3183
3184         return 0;
3185 }
3186
3187 /* unsolicited event for jack sensing */
3188 static void simple_hdmi_unsol_event(struct hda_codec *codec,
3189                                     unsigned int res)
3190 {
3191         snd_hda_jack_set_dirty_all(codec);
3192         snd_hda_jack_report_sync(codec);
3193 }
3194
3195 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
3196  * as long as spec->pins[] is set correctly
3197  */
3198 #define simple_hdmi_build_jack  generic_hdmi_build_jack
3199
3200 static int simple_playback_build_controls(struct hda_codec *codec)
3201 {
3202         struct hdmi_spec *spec = codec->spec;
3203         struct hdmi_spec_per_cvt *per_cvt;
3204         int err;
3205
3206         per_cvt = get_cvt(spec, 0);
3207         err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3208                                           per_cvt->cvt_nid,
3209                                           HDA_PCM_TYPE_HDMI);
3210         if (err < 0)
3211                 return err;
3212         return simple_hdmi_build_jack(codec, 0);
3213 }
3214
3215 static int simple_playback_init(struct hda_codec *codec)
3216 {
3217         struct hdmi_spec *spec = codec->spec;
3218         struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3219         hda_nid_t pin = per_pin->pin_nid;
3220
3221         snd_hda_codec_write(codec, pin, 0,
3222                             AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3223         /* some codecs require to unmute the pin */
3224         if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3225                 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3226                                     AMP_OUT_UNMUTE);
3227         snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3228         return 0;
3229 }
3230
3231 static void simple_playback_free(struct hda_codec *codec)
3232 {
3233         struct hdmi_spec *spec = codec->spec;
3234
3235         hdmi_array_free(spec);
3236         kfree(spec);
3237 }
3238
3239 /*
3240  * Nvidia specific implementations
3241  */
3242
3243 #define Nv_VERB_SET_Channel_Allocation          0xF79
3244 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
3245 #define Nv_VERB_SET_Audio_Protection_On         0xF98
3246 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
3247
3248 #define nvhdmi_master_con_nid_7x        0x04
3249 #define nvhdmi_master_pin_nid_7x        0x05
3250
3251 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3252         /*front, rear, clfe, rear_surr */
3253         0x6, 0x8, 0xa, 0xc,
3254 };
3255
3256 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3257         /* set audio protect on */
3258         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3259         /* enable digital output on pin widget */
3260         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3261         {} /* terminator */
3262 };
3263
3264 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3265         /* set audio protect on */
3266         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3267         /* enable digital output on pin widget */
3268         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3269         { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3270         { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3271         { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3272         { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3273         {} /* terminator */
3274 };
3275
3276 #ifdef LIMITED_RATE_FMT_SUPPORT
3277 /* support only the safe format and rate */
3278 #define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
3279 #define SUPPORTED_MAXBPS        16
3280 #define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
3281 #else
3282 /* support all rates and formats */
3283 #define SUPPORTED_RATES \
3284         (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3285         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3286          SNDRV_PCM_RATE_192000)
3287 #define SUPPORTED_MAXBPS        24
3288 #define SUPPORTED_FORMATS \
3289         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3290 #endif
3291
3292 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3293 {
3294         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3295         return 0;
3296 }
3297
3298 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3299 {
3300         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3301         return 0;
3302 }
3303
3304 static const unsigned int channels_2_6_8[] = {
3305         2, 6, 8
3306 };
3307
3308 static const unsigned int channels_2_8[] = {
3309         2, 8
3310 };
3311
3312 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3313         .count = ARRAY_SIZE(channels_2_6_8),
3314         .list = channels_2_6_8,
3315         .mask = 0,
3316 };
3317
3318 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3319         .count = ARRAY_SIZE(channels_2_8),
3320         .list = channels_2_8,
3321         .mask = 0,
3322 };
3323
3324 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3325                                     struct hda_codec *codec,
3326                                     struct snd_pcm_substream *substream)
3327 {
3328         struct hdmi_spec *spec = codec->spec;
3329         const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3330
3331         switch (codec->preset->vendor_id) {
3332         case 0x10de0002:
3333         case 0x10de0003:
3334         case 0x10de0005:
3335         case 0x10de0006:
3336                 hw_constraints_channels = &hw_constraints_2_8_channels;
3337                 break;
3338         case 0x10de0007:
3339                 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3340                 break;
3341         default:
3342                 break;
3343         }
3344
3345         if (hw_constraints_channels != NULL) {
3346                 snd_pcm_hw_constraint_list(substream->runtime, 0,
3347                                 SNDRV_PCM_HW_PARAM_CHANNELS,
3348                                 hw_constraints_channels);
3349         } else {
3350                 snd_pcm_hw_constraint_step(substream->runtime, 0,
3351                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3352         }
3353
3354         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3355 }
3356
3357 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3358                                      struct hda_codec *codec,
3359                                      struct snd_pcm_substream *substream)
3360 {
3361         struct hdmi_spec *spec = codec->spec;
3362         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3363 }
3364
3365 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3366                                        struct hda_codec *codec,
3367                                        unsigned int stream_tag,
3368                                        unsigned int format,
3369                                        struct snd_pcm_substream *substream)
3370 {
3371         struct hdmi_spec *spec = codec->spec;
3372         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3373                                              stream_tag, format, substream);
3374 }
3375
3376 static const struct hda_pcm_stream simple_pcm_playback = {
3377         .substreams = 1,
3378         .channels_min = 2,
3379         .channels_max = 2,
3380         .ops = {
3381                 .open = simple_playback_pcm_open,
3382                 .close = simple_playback_pcm_close,
3383                 .prepare = simple_playback_pcm_prepare
3384         },
3385 };
3386
3387 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3388         .build_controls = simple_playback_build_controls,
3389         .build_pcms = simple_playback_build_pcms,
3390         .init = simple_playback_init,
3391         .free = simple_playback_free,
3392         .unsol_event = simple_hdmi_unsol_event,
3393 };
3394
3395 static int patch_simple_hdmi(struct hda_codec *codec,
3396                              hda_nid_t cvt_nid, hda_nid_t pin_nid)
3397 {
3398         struct hdmi_spec *spec;
3399         struct hdmi_spec_per_cvt *per_cvt;
3400         struct hdmi_spec_per_pin *per_pin;
3401
3402         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3403         if (!spec)
3404                 return -ENOMEM;
3405
3406         spec->codec = codec;
3407         codec->spec = spec;
3408         hdmi_array_init(spec, 1);
3409
3410         spec->multiout.num_dacs = 0;  /* no analog */
3411         spec->multiout.max_channels = 2;
3412         spec->multiout.dig_out_nid = cvt_nid;
3413         spec->num_cvts = 1;
3414         spec->num_pins = 1;
3415         per_pin = snd_array_new(&spec->pins);
3416         per_cvt = snd_array_new(&spec->cvts);
3417         if (!per_pin || !per_cvt) {
3418                 simple_playback_free(codec);
3419                 return -ENOMEM;
3420         }
3421         per_cvt->cvt_nid = cvt_nid;
3422         per_pin->pin_nid = pin_nid;
3423         spec->pcm_playback = simple_pcm_playback;
3424
3425         codec->patch_ops = simple_hdmi_patch_ops;
3426
3427         return 0;
3428 }
3429
3430 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3431                                                     int channels)
3432 {
3433         unsigned int chanmask;
3434         int chan = channels ? (channels - 1) : 1;
3435
3436         switch (channels) {
3437         default:
3438         case 0:
3439         case 2:
3440                 chanmask = 0x00;
3441                 break;
3442         case 4:
3443                 chanmask = 0x08;
3444                 break;
3445         case 6:
3446                 chanmask = 0x0b;
3447                 break;
3448         case 8:
3449                 chanmask = 0x13;
3450                 break;
3451         }
3452
3453         /* Set the audio infoframe channel allocation and checksum fields.  The
3454          * channel count is computed implicitly by the hardware. */
3455         snd_hda_codec_write(codec, 0x1, 0,
3456                         Nv_VERB_SET_Channel_Allocation, chanmask);
3457
3458         snd_hda_codec_write(codec, 0x1, 0,
3459                         Nv_VERB_SET_Info_Frame_Checksum,
3460                         (0x71 - chan - chanmask));
3461 }
3462
3463 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3464                                    struct hda_codec *codec,
3465                                    struct snd_pcm_substream *substream)
3466 {
3467         struct hdmi_spec *spec = codec->spec;
3468         int i;
3469
3470         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3471                         0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3472         for (i = 0; i < 4; i++) {
3473                 /* set the stream id */
3474                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3475                                 AC_VERB_SET_CHANNEL_STREAMID, 0);
3476                 /* set the stream format */
3477                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3478                                 AC_VERB_SET_STREAM_FORMAT, 0);
3479         }
3480
3481         /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3482          * streams are disabled. */
3483         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3484
3485         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3486 }
3487
3488 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3489                                      struct hda_codec *codec,
3490                                      unsigned int stream_tag,
3491                                      unsigned int format,
3492                                      struct snd_pcm_substream *substream)
3493 {
3494         int chs;
3495         unsigned int dataDCC2, channel_id;
3496         int i;
3497         struct hdmi_spec *spec = codec->spec;
3498         struct hda_spdif_out *spdif;
3499         struct hdmi_spec_per_cvt *per_cvt;
3500
3501         mutex_lock(&codec->spdif_mutex);
3502         per_cvt = get_cvt(spec, 0);
3503         spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3504
3505         chs = substream->runtime->channels;
3506
3507         dataDCC2 = 0x2;
3508
3509         /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3510         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3511                 snd_hda_codec_write(codec,
3512                                 nvhdmi_master_con_nid_7x,
3513                                 0,
3514                                 AC_VERB_SET_DIGI_CONVERT_1,
3515                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3516
3517         /* set the stream id */
3518         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3519                         AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3520
3521         /* set the stream format */
3522         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3523                         AC_VERB_SET_STREAM_FORMAT, format);
3524
3525         /* turn on again (if needed) */
3526         /* enable and set the channel status audio/data flag */
3527         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3528                 snd_hda_codec_write(codec,
3529                                 nvhdmi_master_con_nid_7x,
3530                                 0,
3531                                 AC_VERB_SET_DIGI_CONVERT_1,
3532                                 spdif->ctls & 0xff);
3533                 snd_hda_codec_write(codec,
3534                                 nvhdmi_master_con_nid_7x,
3535                                 0,
3536                                 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3537         }
3538
3539         for (i = 0; i < 4; i++) {
3540                 if (chs == 2)
3541                         channel_id = 0;
3542                 else
3543                         channel_id = i * 2;
3544
3545                 /* turn off SPDIF once;
3546                  *otherwise the IEC958 bits won't be updated
3547                  */
3548                 if (codec->spdif_status_reset &&
3549                 (spdif->ctls & AC_DIG1_ENABLE))
3550                         snd_hda_codec_write(codec,
3551                                 nvhdmi_con_nids_7x[i],
3552                                 0,
3553                                 AC_VERB_SET_DIGI_CONVERT_1,
3554                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3555                 /* set the stream id */
3556                 snd_hda_codec_write(codec,
3557                                 nvhdmi_con_nids_7x[i],
3558                                 0,
3559                                 AC_VERB_SET_CHANNEL_STREAMID,
3560                                 (stream_tag << 4) | channel_id);
3561                 /* set the stream format */
3562                 snd_hda_codec_write(codec,
3563                                 nvhdmi_con_nids_7x[i],
3564                                 0,
3565                                 AC_VERB_SET_STREAM_FORMAT,
3566                                 format);
3567                 /* turn on again (if needed) */
3568                 /* enable and set the channel status audio/data flag */
3569                 if (codec->spdif_status_reset &&
3570                 (spdif->ctls & AC_DIG1_ENABLE)) {
3571                         snd_hda_codec_write(codec,
3572                                         nvhdmi_con_nids_7x[i],
3573                                         0,
3574                                         AC_VERB_SET_DIGI_CONVERT_1,
3575                                         spdif->ctls & 0xff);
3576                         snd_hda_codec_write(codec,
3577                                         nvhdmi_con_nids_7x[i],
3578                                         0,
3579                                         AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3580                 }
3581         }
3582
3583         nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3584
3585         mutex_unlock(&codec->spdif_mutex);
3586         return 0;
3587 }
3588
3589 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3590         .substreams = 1,
3591         .channels_min = 2,
3592         .channels_max = 8,
3593         .nid = nvhdmi_master_con_nid_7x,
3594         .rates = SUPPORTED_RATES,
3595         .maxbps = SUPPORTED_MAXBPS,
3596         .formats = SUPPORTED_FORMATS,
3597         .ops = {
3598                 .open = simple_playback_pcm_open,
3599                 .close = nvhdmi_8ch_7x_pcm_close,
3600                 .prepare = nvhdmi_8ch_7x_pcm_prepare
3601         },
3602 };
3603
3604 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3605 {
3606         struct hdmi_spec *spec;
3607         int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3608                                     nvhdmi_master_pin_nid_7x);
3609         if (err < 0)
3610                 return err;
3611
3612         codec->patch_ops.init = nvhdmi_7x_init_2ch;
3613         /* override the PCM rates, etc, as the codec doesn't give full list */
3614         spec = codec->spec;
3615         spec->pcm_playback.rates = SUPPORTED_RATES;
3616         spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3617         spec->pcm_playback.formats = SUPPORTED_FORMATS;
3618         return 0;
3619 }
3620
3621 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3622 {
3623         struct hdmi_spec *spec = codec->spec;
3624         int err = simple_playback_build_pcms(codec);
3625         if (!err) {
3626                 struct hda_pcm *info = get_pcm_rec(spec, 0);
3627                 info->own_chmap = true;
3628         }
3629         return err;
3630 }
3631
3632 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3633 {
3634         struct hdmi_spec *spec = codec->spec;
3635         struct hda_pcm *info;
3636         struct snd_pcm_chmap *chmap;
3637         int err;
3638
3639         err = simple_playback_build_controls(codec);
3640         if (err < 0)
3641                 return err;
3642
3643         /* add channel maps */
3644         info = get_pcm_rec(spec, 0);
3645         err = snd_pcm_add_chmap_ctls(info->pcm,
3646                                      SNDRV_PCM_STREAM_PLAYBACK,
3647                                      snd_pcm_alt_chmaps, 8, 0, &chmap);
3648         if (err < 0)
3649                 return err;
3650         switch (codec->preset->vendor_id) {
3651         case 0x10de0002:
3652         case 0x10de0003:
3653         case 0x10de0005:
3654         case 0x10de0006:
3655                 chmap->channel_mask = (1U << 2) | (1U << 8);
3656                 break;
3657         case 0x10de0007:
3658                 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3659         }
3660         return 0;
3661 }
3662
3663 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3664 {
3665         struct hdmi_spec *spec;
3666         int err = patch_nvhdmi_2ch(codec);
3667         if (err < 0)
3668                 return err;
3669         spec = codec->spec;
3670         spec->multiout.max_channels = 8;
3671         spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3672         codec->patch_ops.init = nvhdmi_7x_init_8ch;
3673         codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3674         codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3675
3676         /* Initialize the audio infoframe channel mask and checksum to something
3677          * valid */
3678         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3679
3680         return 0;
3681 }
3682
3683 /*
3684  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3685  * - 0x10de0015
3686  * - 0x10de0040
3687  */
3688 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3689                 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3690 {
3691         if (cap->ca_index == 0x00 && channels == 2)
3692                 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3693
3694         /* If the speaker allocation matches the channel count, it is OK. */
3695         if (cap->channels != channels)
3696                 return -1;
3697
3698         /* all channels are remappable freely */
3699         return SNDRV_CTL_TLVT_CHMAP_VAR;
3700 }
3701
3702 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3703                 int ca, int chs, unsigned char *map)
3704 {
3705         if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3706                 return -EINVAL;
3707
3708         return 0;
3709 }
3710
3711 /* map from pin NID to port; port is 0-based */
3712 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3713 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3714 {
3715         return pin_nid - 4;
3716 }
3717
3718 /* reverse-map from port to pin NID: see above */
3719 static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3720 {
3721         return port + 4;
3722 }
3723
3724 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3725         .pin2port = nvhdmi_pin2port,
3726         .pin_eld_notify = generic_acomp_pin_eld_notify,
3727         .master_bind = generic_acomp_master_bind,
3728         .master_unbind = generic_acomp_master_unbind,
3729 };
3730
3731 static int patch_nvhdmi(struct hda_codec *codec)
3732 {
3733         struct hdmi_spec *spec;
3734         int err;
3735
3736         err = alloc_generic_hdmi(codec);
3737         if (err < 0)
3738                 return err;
3739         codec->dp_mst = true;
3740
3741         spec = codec->spec;
3742         spec->dyn_pcm_assign = true;
3743
3744         err = hdmi_parse_codec(codec);
3745         if (err < 0) {
3746                 generic_spec_free(codec);
3747                 return err;
3748         }
3749
3750         generic_hdmi_init_per_pins(codec);
3751
3752         spec->dyn_pin_out = true;
3753
3754         spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3755                 nvhdmi_chmap_cea_alloc_validate_get_type;
3756         spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3757
3758         codec->link_down_at_suspend = 1;
3759
3760         generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3761
3762         return 0;
3763 }
3764
3765 static int patch_nvhdmi_legacy(struct hda_codec *codec)
3766 {
3767         struct hdmi_spec *spec;
3768         int err;
3769
3770         err = patch_generic_hdmi(codec);
3771         if (err)
3772                 return err;
3773
3774         spec = codec->spec;
3775         spec->dyn_pin_out = true;
3776
3777         spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3778                 nvhdmi_chmap_cea_alloc_validate_get_type;
3779         spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3780
3781         codec->link_down_at_suspend = 1;
3782
3783         return 0;
3784 }
3785
3786 /*
3787  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3788  * accessed using vendor-defined verbs. These registers can be used for
3789  * interoperability between the HDA and HDMI drivers.
3790  */
3791
3792 /* Audio Function Group node */
3793 #define NVIDIA_AFG_NID 0x01
3794
3795 /*
3796  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3797  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3798  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3799  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3800  * additional bit (at position 30) to signal the validity of the format.
3801  *
3802  * | 31      | 30    | 29  16 | 15   0 |
3803  * +---------+-------+--------+--------+
3804  * | TRIGGER | VALID | UNUSED | FORMAT |
3805  * +-----------------------------------|
3806  *
3807  * Note that for the trigger bit to take effect it needs to change value
3808  * (i.e. it needs to be toggled). The trigger bit is not applicable from
3809  * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
3810  * trigger to hdmi.
3811  */
3812 #define NVIDIA_SET_HOST_INTR            0xf80
3813 #define NVIDIA_GET_SCRATCH0             0xfa6
3814 #define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
3815 #define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
3816 #define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
3817 #define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
3818 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3819 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3820
3821 #define NVIDIA_GET_SCRATCH1             0xfab
3822 #define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
3823 #define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
3824 #define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
3825 #define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
3826
3827 /*
3828  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3829  * the format is invalidated so that the HDMI codec can be disabled.
3830  */
3831 static void tegra_hdmi_set_format(struct hda_codec *codec,
3832                                   hda_nid_t cvt_nid,
3833                                   unsigned int format)
3834 {
3835         unsigned int value;
3836         unsigned int nid = NVIDIA_AFG_NID;
3837         struct hdmi_spec *spec = codec->spec;
3838
3839         /*
3840          * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
3841          * This resulted in moving scratch registers from audio function
3842          * group to converter widget context. So CVT NID should be used for
3843          * scratch register read/write for DP MST supported Tegra HDA codec.
3844          */
3845         if (codec->dp_mst)
3846                 nid = cvt_nid;
3847
3848         /* bits [31:30] contain the trigger and valid bits */
3849         value = snd_hda_codec_read(codec, nid, 0,
3850                                    NVIDIA_GET_SCRATCH0, 0);
3851         value = (value >> 24) & 0xff;
3852
3853         /* bits [15:0] are used to store the HDA format */
3854         snd_hda_codec_write(codec, nid, 0,
3855                             NVIDIA_SET_SCRATCH0_BYTE0,
3856                             (format >> 0) & 0xff);
3857         snd_hda_codec_write(codec, nid, 0,
3858                             NVIDIA_SET_SCRATCH0_BYTE1,
3859                             (format >> 8) & 0xff);
3860
3861         /* bits [16:24] are unused */
3862         snd_hda_codec_write(codec, nid, 0,
3863                             NVIDIA_SET_SCRATCH0_BYTE2, 0);
3864
3865         /*
3866          * Bit 30 signals that the data is valid and hence that HDMI audio can
3867          * be enabled.
3868          */
3869         if (format == 0)
3870                 value &= ~NVIDIA_SCRATCH_VALID;
3871         else
3872                 value |= NVIDIA_SCRATCH_VALID;
3873
3874         if (spec->hdmi_intr_trig_ctrl) {
3875                 /*
3876                  * For Tegra HDA Codec design from TEGRA234 onwards, the
3877                  * Interrupt to hdmi driver is triggered by writing
3878                  * non-zero values to verb 0xF80 instead of 31st bit of
3879                  * scratch register.
3880                  */
3881                 snd_hda_codec_write(codec, nid, 0,
3882                                 NVIDIA_SET_SCRATCH0_BYTE3, value);
3883                 snd_hda_codec_write(codec, nid, 0,
3884                                 NVIDIA_SET_HOST_INTR, 0x1);
3885         } else {
3886                 /*
3887                  * Whenever the 31st trigger bit is toggled, an interrupt is raised
3888                  * in the HDMI codec. The HDMI driver will use that as trigger
3889                  * to update its configuration.
3890                  */
3891                 value ^= NVIDIA_SCRATCH_TRIGGER;
3892
3893                 snd_hda_codec_write(codec, nid, 0,
3894                                 NVIDIA_SET_SCRATCH0_BYTE3, value);
3895         }
3896 }
3897
3898 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3899                                   struct hda_codec *codec,
3900                                   unsigned int stream_tag,
3901                                   unsigned int format,
3902                                   struct snd_pcm_substream *substream)
3903 {
3904         int err;
3905
3906         err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3907                                                 format, substream);
3908         if (err < 0)
3909                 return err;
3910
3911         /* notify the HDMI codec of the format change */
3912         tegra_hdmi_set_format(codec, hinfo->nid, format);
3913
3914         return 0;
3915 }
3916
3917 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3918                                   struct hda_codec *codec,
3919                                   struct snd_pcm_substream *substream)
3920 {
3921         /* invalidate the format in the HDMI codec */
3922         tegra_hdmi_set_format(codec, hinfo->nid, 0);
3923
3924         return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3925 }
3926
3927 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3928 {
3929         struct hdmi_spec *spec = codec->spec;
3930         unsigned int i;
3931
3932         for (i = 0; i < spec->num_pins; i++) {
3933                 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3934
3935                 if (pcm->pcm_type == type)
3936                         return pcm;
3937         }
3938
3939         return NULL;
3940 }
3941
3942 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3943 {
3944         struct hda_pcm_stream *stream;
3945         struct hda_pcm *pcm;
3946         int err;
3947
3948         err = generic_hdmi_build_pcms(codec);
3949         if (err < 0)
3950                 return err;
3951
3952         pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3953         if (!pcm)
3954                 return -ENODEV;
3955
3956         /*
3957          * Override ->prepare() and ->cleanup() operations to notify the HDMI
3958          * codec about format changes.
3959          */
3960         stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3961         stream->ops.prepare = tegra_hdmi_pcm_prepare;
3962         stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3963
3964         return 0;
3965 }
3966
3967 static int tegra_hdmi_init(struct hda_codec *codec)
3968 {
3969         struct hdmi_spec *spec = codec->spec;
3970         int i, err;
3971
3972         err = hdmi_parse_codec(codec);
3973         if (err < 0) {
3974                 generic_spec_free(codec);
3975                 return err;
3976         }
3977
3978         for (i = 0; i < spec->num_cvts; i++)
3979                 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
3980                                         AC_VERB_SET_DIGI_CONVERT_1,
3981                                         AC_DIG1_ENABLE);
3982
3983         generic_hdmi_init_per_pins(codec);
3984
3985         codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3986         spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3987                 nvhdmi_chmap_cea_alloc_validate_get_type;
3988         spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3989
3990         spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3991                 nvhdmi_chmap_cea_alloc_validate_get_type;
3992         spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3993
3994         return 0;
3995 }
3996
3997 static int patch_tegra_hdmi(struct hda_codec *codec)
3998 {
3999         int err;
4000
4001         err = alloc_generic_hdmi(codec);
4002         if (err < 0)
4003                 return err;
4004
4005         return tegra_hdmi_init(codec);
4006 }
4007
4008 static int patch_tegra234_hdmi(struct hda_codec *codec)
4009 {
4010         struct hdmi_spec *spec;
4011         int err;
4012
4013         err = alloc_generic_hdmi(codec);
4014         if (err < 0)
4015                 return err;
4016
4017         codec->dp_mst = true;
4018         codec->mst_no_extra_pcms = true;
4019         spec = codec->spec;
4020         spec->dyn_pin_out = true;
4021         spec->dyn_pcm_assign = true;
4022         spec->hdmi_intr_trig_ctrl = true;
4023
4024         return tegra_hdmi_init(codec);
4025 }
4026
4027 /*
4028  * ATI/AMD-specific implementations
4029  */
4030
4031 #define is_amdhdmi_rev3_or_later(codec) \
4032         ((codec)->core.vendor_id == 0x1002aa01 && \
4033          ((codec)->core.revision_id & 0xff00) >= 0x0300)
4034 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
4035
4036 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
4037 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
4038 #define ATI_VERB_SET_DOWNMIX_INFO       0x772
4039 #define ATI_VERB_SET_MULTICHANNEL_01    0x777
4040 #define ATI_VERB_SET_MULTICHANNEL_23    0x778
4041 #define ATI_VERB_SET_MULTICHANNEL_45    0x779
4042 #define ATI_VERB_SET_MULTICHANNEL_67    0x77a
4043 #define ATI_VERB_SET_HBR_CONTROL        0x77c
4044 #define ATI_VERB_SET_MULTICHANNEL_1     0x785
4045 #define ATI_VERB_SET_MULTICHANNEL_3     0x786
4046 #define ATI_VERB_SET_MULTICHANNEL_5     0x787
4047 #define ATI_VERB_SET_MULTICHANNEL_7     0x788
4048 #define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
4049 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
4050 #define ATI_VERB_GET_DOWNMIX_INFO       0xf72
4051 #define ATI_VERB_GET_MULTICHANNEL_01    0xf77
4052 #define ATI_VERB_GET_MULTICHANNEL_23    0xf78
4053 #define ATI_VERB_GET_MULTICHANNEL_45    0xf79
4054 #define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
4055 #define ATI_VERB_GET_HBR_CONTROL        0xf7c
4056 #define ATI_VERB_GET_MULTICHANNEL_1     0xf85
4057 #define ATI_VERB_GET_MULTICHANNEL_3     0xf86
4058 #define ATI_VERB_GET_MULTICHANNEL_5     0xf87
4059 #define ATI_VERB_GET_MULTICHANNEL_7     0xf88
4060 #define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
4061
4062 /* AMD specific HDA cvt verbs */
4063 #define ATI_VERB_SET_RAMP_RATE          0x770
4064 #define ATI_VERB_GET_RAMP_RATE          0xf70
4065
4066 #define ATI_OUT_ENABLE 0x1
4067
4068 #define ATI_MULTICHANNEL_MODE_PAIRED    0
4069 #define ATI_MULTICHANNEL_MODE_SINGLE    1
4070
4071 #define ATI_HBR_CAPABLE 0x01
4072 #define ATI_HBR_ENABLE 0x10
4073
4074 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4075                                int dev_id, unsigned char *buf, int *eld_size)
4076 {
4077         WARN_ON(dev_id != 0);
4078         /* call hda_eld.c ATI/AMD-specific function */
4079         return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
4080                                     is_amdhdmi_rev3_or_later(codec));
4081 }
4082
4083 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
4084                                         hda_nid_t pin_nid, int dev_id, int ca,
4085                                         int active_channels, int conn_type)
4086 {
4087         WARN_ON(dev_id != 0);
4088         snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
4089 }
4090
4091 static int atihdmi_paired_swap_fc_lfe(int pos)
4092 {
4093         /*
4094          * ATI/AMD have automatic FC/LFE swap built-in
4095          * when in pairwise mapping mode.
4096          */
4097
4098         switch (pos) {
4099                 /* see channel_allocations[].speakers[] */
4100                 case 2: return 3;
4101                 case 3: return 2;
4102                 default: break;
4103         }
4104
4105         return pos;
4106 }
4107
4108 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
4109                         int ca, int chs, unsigned char *map)
4110 {
4111         struct hdac_cea_channel_speaker_allocation *cap;
4112         int i, j;
4113
4114         /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
4115
4116         cap = snd_hdac_get_ch_alloc_from_ca(ca);
4117         for (i = 0; i < chs; ++i) {
4118                 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
4119                 bool ok = false;
4120                 bool companion_ok = false;
4121
4122                 if (!mask)
4123                         continue;
4124
4125                 for (j = 0 + i % 2; j < 8; j += 2) {
4126                         int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
4127                         if (cap->speakers[chan_idx] == mask) {
4128                                 /* channel is in a supported position */
4129                                 ok = true;
4130
4131                                 if (i % 2 == 0 && i + 1 < chs) {
4132                                         /* even channel, check the odd companion */
4133                                         int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
4134                                         int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4135                                         int comp_mask_act = cap->speakers[comp_chan_idx];
4136
4137                                         if (comp_mask_req == comp_mask_act)
4138                                                 companion_ok = true;
4139                                         else
4140                                                 return -EINVAL;
4141                                 }
4142                                 break;
4143                         }
4144                 }
4145
4146                 if (!ok)
4147                         return -EINVAL;
4148
4149                 if (companion_ok)
4150                         i++; /* companion channel already checked */
4151         }
4152
4153         return 0;
4154 }
4155
4156 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4157                 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4158 {
4159         struct hda_codec *codec = hdac_to_hda_codec(hdac);
4160         int verb;
4161         int ati_channel_setup = 0;
4162
4163         if (hdmi_slot > 7)
4164                 return -EINVAL;
4165
4166         if (!has_amd_full_remap_support(codec)) {
4167                 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4168
4169                 /* In case this is an odd slot but without stream channel, do not
4170                  * disable the slot since the corresponding even slot could have a
4171                  * channel. In case neither have a channel, the slot pair will be
4172                  * disabled when this function is called for the even slot. */
4173                 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4174                         return 0;
4175
4176                 hdmi_slot -= hdmi_slot % 2;
4177
4178                 if (stream_channel != 0xf)
4179                         stream_channel -= stream_channel % 2;
4180         }
4181
4182         verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4183
4184         /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4185
4186         if (stream_channel != 0xf)
4187                 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4188
4189         return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4190 }
4191
4192 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4193                                 hda_nid_t pin_nid, int asp_slot)
4194 {
4195         struct hda_codec *codec = hdac_to_hda_codec(hdac);
4196         bool was_odd = false;
4197         int ati_asp_slot = asp_slot;
4198         int verb;
4199         int ati_channel_setup;
4200
4201         if (asp_slot > 7)
4202                 return -EINVAL;
4203
4204         if (!has_amd_full_remap_support(codec)) {
4205                 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4206                 if (ati_asp_slot % 2 != 0) {
4207                         ati_asp_slot -= 1;
4208                         was_odd = true;
4209                 }
4210         }
4211
4212         verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4213
4214         ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4215
4216         if (!(ati_channel_setup & ATI_OUT_ENABLE))
4217                 return 0xf;
4218
4219         return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4220 }
4221
4222 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4223                 struct hdac_chmap *chmap,
4224                 struct hdac_cea_channel_speaker_allocation *cap,
4225                 int channels)
4226 {
4227         int c;
4228
4229         /*
4230          * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4231          * we need to take that into account (a single channel may take 2
4232          * channel slots if we need to carry a silent channel next to it).
4233          * On Rev3+ AMD codecs this function is not used.
4234          */
4235         int chanpairs = 0;
4236
4237         /* We only produce even-numbered channel count TLVs */
4238         if ((channels % 2) != 0)
4239                 return -1;
4240
4241         for (c = 0; c < 7; c += 2) {
4242                 if (cap->speakers[c] || cap->speakers[c+1])
4243                         chanpairs++;
4244         }
4245
4246         if (chanpairs * 2 != channels)
4247                 return -1;
4248
4249         return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4250 }
4251
4252 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4253                 struct hdac_cea_channel_speaker_allocation *cap,
4254                 unsigned int *chmap, int channels)
4255 {
4256         /* produce paired maps for pre-rev3 ATI/AMD codecs */
4257         int count = 0;
4258         int c;
4259
4260         for (c = 7; c >= 0; c--) {
4261                 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4262                 int spk = cap->speakers[chan];
4263                 if (!spk) {
4264                         /* add N/A channel if the companion channel is occupied */
4265                         if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4266                                 chmap[count++] = SNDRV_CHMAP_NA;
4267
4268                         continue;
4269                 }
4270
4271                 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4272         }
4273
4274         WARN_ON(count != channels);
4275 }
4276
4277 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4278                                  int dev_id, bool hbr)
4279 {
4280         int hbr_ctl, hbr_ctl_new;
4281
4282         WARN_ON(dev_id != 0);
4283
4284         hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4285         if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4286                 if (hbr)
4287                         hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4288                 else
4289                         hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4290
4291                 codec_dbg(codec,
4292                           "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4293                                 pin_nid,
4294                                 hbr_ctl == hbr_ctl_new ? "" : "new-",
4295                                 hbr_ctl_new);
4296
4297                 if (hbr_ctl != hbr_ctl_new)
4298                         snd_hda_codec_write(codec, pin_nid, 0,
4299                                                 ATI_VERB_SET_HBR_CONTROL,
4300                                                 hbr_ctl_new);
4301
4302         } else if (hbr)
4303                 return -EINVAL;
4304
4305         return 0;
4306 }
4307
4308 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4309                                 hda_nid_t pin_nid, int dev_id,
4310                                 u32 stream_tag, int format)
4311 {
4312         if (is_amdhdmi_rev3_or_later(codec)) {
4313                 int ramp_rate = 180; /* default as per AMD spec */
4314                 /* disable ramp-up/down for non-pcm as per AMD spec */
4315                 if (format & AC_FMT_TYPE_NON_PCM)
4316                         ramp_rate = 0;
4317
4318                 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4319         }
4320
4321         return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4322                                  stream_tag, format);
4323 }
4324
4325
4326 static int atihdmi_init(struct hda_codec *codec)
4327 {
4328         struct hdmi_spec *spec = codec->spec;
4329         int pin_idx, err;
4330
4331         err = generic_hdmi_init(codec);
4332
4333         if (err)
4334                 return err;
4335
4336         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4337                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4338
4339                 /* make sure downmix information in infoframe is zero */
4340                 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4341
4342                 /* enable channel-wise remap mode if supported */
4343                 if (has_amd_full_remap_support(codec))
4344                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4345                                             ATI_VERB_SET_MULTICHANNEL_MODE,
4346                                             ATI_MULTICHANNEL_MODE_SINGLE);
4347         }
4348         codec->auto_runtime_pm = 1;
4349
4350         return 0;
4351 }
4352
4353 /* map from pin NID to port; port is 0-based */
4354 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4355 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4356 {
4357         return pin_nid / 2 - 1;
4358 }
4359
4360 /* reverse-map from port to pin NID: see above */
4361 static int atihdmi_port2pin(struct hda_codec *codec, int port)
4362 {
4363         return port * 2 + 3;
4364 }
4365
4366 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4367         .pin2port = atihdmi_pin2port,
4368         .pin_eld_notify = generic_acomp_pin_eld_notify,
4369         .master_bind = generic_acomp_master_bind,
4370         .master_unbind = generic_acomp_master_unbind,
4371 };
4372
4373 static int patch_atihdmi(struct hda_codec *codec)
4374 {
4375         struct hdmi_spec *spec;
4376         struct hdmi_spec_per_cvt *per_cvt;
4377         int err, cvt_idx;
4378
4379         err = patch_generic_hdmi(codec);
4380
4381         if (err)
4382                 return err;
4383
4384         codec->patch_ops.init = atihdmi_init;
4385
4386         spec = codec->spec;
4387
4388         spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4389         spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4390         spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4391         spec->ops.setup_stream = atihdmi_setup_stream;
4392
4393         spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4394         spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4395
4396         if (!has_amd_full_remap_support(codec)) {
4397                 /* override to ATI/AMD-specific versions with pairwise mapping */
4398                 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4399                         atihdmi_paired_chmap_cea_alloc_validate_get_type;
4400                 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4401                                 atihdmi_paired_cea_alloc_to_tlv_chmap;
4402                 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4403         }
4404
4405         /* ATI/AMD converters do not advertise all of their capabilities */
4406         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4407                 per_cvt = get_cvt(spec, cvt_idx);
4408                 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4409                 per_cvt->rates |= SUPPORTED_RATES;
4410                 per_cvt->formats |= SUPPORTED_FORMATS;
4411                 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4412         }
4413
4414         spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4415
4416         /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4417          * the link-down as is.  Tell the core to allow it.
4418          */
4419         codec->link_down_at_suspend = 1;
4420
4421         generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4422
4423         return 0;
4424 }
4425
4426 /* VIA HDMI Implementation */
4427 #define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
4428 #define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
4429
4430 static int patch_via_hdmi(struct hda_codec *codec)
4431 {
4432         return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4433 }
4434
4435 /*
4436  * patch entries
4437  */
4438 static const struct hda_device_id snd_hda_id_hdmi[] = {
4439 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",       patch_atihdmi),
4440 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",       patch_atihdmi),
4441 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",   patch_atihdmi),
4442 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",        patch_atihdmi),
4443 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",     patch_generic_hdmi),
4444 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",     patch_generic_hdmi),
4445 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",    patch_generic_hdmi),
4446 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI",       patch_nvhdmi_2ch),
4447 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
4448 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
4449 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI",      patch_nvhdmi_8ch_7x),
4450 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
4451 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
4452 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",    patch_nvhdmi_8ch_7x),
4453 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP",   patch_nvhdmi_legacy),
4454 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP",   patch_nvhdmi_legacy),
4455 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",   patch_nvhdmi_legacy),
4456 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",   patch_nvhdmi_legacy),
4457 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",       patch_nvhdmi_legacy),
4458 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",   patch_nvhdmi_legacy),
4459 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",   patch_nvhdmi_legacy),
4460 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",   patch_nvhdmi_legacy),
4461 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",   patch_nvhdmi_legacy),
4462 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",   patch_nvhdmi_legacy),
4463 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",   patch_nvhdmi_legacy),
4464 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",   patch_nvhdmi_legacy),
4465 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",   patch_nvhdmi_legacy),
4466 /* 17 is known to be absent */
4467 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",   patch_nvhdmi_legacy),
4468 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",   patch_nvhdmi_legacy),
4469 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",   patch_nvhdmi_legacy),
4470 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",   patch_nvhdmi_legacy),
4471 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",   patch_nvhdmi_legacy),
4472 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",     patch_tegra_hdmi),
4473 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",    patch_tegra_hdmi),
4474 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",    patch_tegra_hdmi),
4475 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4476 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4477 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4478 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4479 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4480 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
4481 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",   patch_nvhdmi),
4482 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",   patch_nvhdmi),
4483 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",   patch_nvhdmi),
4484 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",   patch_nvhdmi),
4485 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",   patch_nvhdmi),
4486 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP",   patch_nvhdmi),
4487 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP",   patch_nvhdmi),
4488 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",   patch_nvhdmi),
4489 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP",   patch_nvhdmi),
4490 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",   patch_nvhdmi),
4491 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP",   patch_nvhdmi),
4492 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP",   patch_nvhdmi),
4493 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",       patch_nvhdmi_2ch),
4494 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",   patch_nvhdmi),
4495 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",   patch_nvhdmi),
4496 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",   patch_nvhdmi),
4497 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP",   patch_nvhdmi),
4498 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP",   patch_nvhdmi),
4499 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP",   patch_nvhdmi),
4500 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP",   patch_nvhdmi),
4501 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP",   patch_nvhdmi),
4502 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",   patch_nvhdmi),
4503 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP",   patch_nvhdmi),
4504 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP",   patch_nvhdmi),
4505 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP",   patch_nvhdmi),
4506 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP",   patch_nvhdmi),
4507 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP",   patch_nvhdmi),
4508 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP",   patch_nvhdmi),
4509 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP",   patch_nvhdmi),
4510 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP",   patch_nvhdmi),
4511 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP",   patch_nvhdmi),
4512 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP",   patch_nvhdmi),
4513 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP",   patch_nvhdmi),
4514 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP",   patch_nvhdmi),
4515 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP",   patch_nvhdmi),
4516 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP",   patch_nvhdmi),
4517 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP",   patch_nvhdmi),
4518 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP",   patch_nvhdmi),
4519 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP",   patch_nvhdmi),
4520 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP",   patch_nvhdmi),
4521 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP",   patch_nvhdmi),
4522 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP",   patch_nvhdmi),
4523 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",       patch_nvhdmi_2ch),
4524 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI",    patch_nvhdmi_2ch),
4525 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",    patch_via_hdmi),
4526 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",    patch_via_hdmi),
4527 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",     patch_generic_hdmi),
4528 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",     patch_generic_hdmi),
4529 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
4530 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI",  patch_i915_glk_hdmi),
4531 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",    patch_generic_hdmi),
4532 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",     patch_generic_hdmi),
4533 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",   patch_generic_hdmi),
4534 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
4535 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4536 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4537 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",     patch_i915_hsw_hdmi),
4538 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",   patch_i915_hsw_hdmi),
4539 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",     patch_i915_hsw_hdmi),
4540 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",     patch_i915_hsw_hdmi),
4541 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",    patch_i915_hsw_hdmi),
4542 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI",  patch_i915_glk_hdmi),
4543 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI",  patch_i915_glk_hdmi),
4544 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI",     patch_i915_icl_hdmi),
4545 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI",   patch_i915_tgl_hdmi),
4546 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4547 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI",   patch_i915_tgl_hdmi),
4548 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI",  patch_i915_tgl_hdmi),
4549 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI",  patch_i915_tgl_hdmi),
4550 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi),
4551 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI",  patch_i915_icl_hdmi),
4552 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4553 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
4554 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",  patch_generic_hdmi),
4555 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4556 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",    patch_i915_byt_hdmi),
4557 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",   patch_generic_hdmi),
4558 /* special ID for generic HDMI */
4559 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4560 {} /* terminator */
4561 };
4562 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4563
4564 MODULE_LICENSE("GPL");
4565 MODULE_DESCRIPTION("HDMI HD-audio codec");
4566 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4567 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4568 MODULE_ALIAS("snd-hda-codec-atihdmi");
4569
4570 static struct hda_codec_driver hdmi_driver = {
4571         .id = snd_hda_id_hdmi,
4572 };
4573
4574 module_hda_codec_driver(hdmi_driver);