sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pgtable.h>
  40
  41 #ifdef CONFIG_X86
  42 /* for snoop control */
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/firmware.h>
  54 #include <sound/hda_codec.h>
  55 #include "hda_controller.h"
  56 #include "hda_intel.h"
  57
  58 #define CREATE_TRACE_POINTS
  59 #include "hda_intel_trace.h"
  60
  61 /* position fix mode */
  62 enum {
  63         POS_FIX_AUTO,
  64         POS_FIX_LPIB,
  65         POS_FIX_POSBUF,
  66         POS_FIX_VIACOMBO,
  67         POS_FIX_COMBO,
  68         POS_FIX_SKL,
  69         POS_FIX_FIFO,
  70 };
  71
  72 /* Defines for ATI HD Audio support in SB450 south bridge */
  73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  75
  76 /* Defines for Nvidia HDA support */
  77 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  78 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  79 #define NVIDIA_HDA_ISTRM_COH          0x4d
  80 #define NVIDIA_HDA_OSTRM_COH          0x4c
  81 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  82
  83 /* Defines for Intel SCH HDA snoop control */
  84 #define INTEL_HDA_CGCTL  0x48
  85 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  86 #define INTEL_SCH_HDA_DEVC      0x78
  87 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  88
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = 1;
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
 165                              "(0=off, 1=on) (default=1); "
 166                  "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
 167
 168 #ifdef CONFIG_PM
 169 static int param_set_xint(const char *val, const struct kernel_param *kp);
 170 static const struct kernel_param_ops param_ops_xint = {
 171         .set = param_set_xint,
 172         .get = param_get_int,
 173 };
 174 #define param_check_xint param_check_int
 175
 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 177 module_param(power_save, xint, 0644);
 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 179                  "(in second, 0 = disable).");
 180
 181 static bool pm_blacklist = true;
 182 module_param(pm_blacklist, bool, 0644);
 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 184
 185 /* reset the HD-audio controller in power save mode.
 186  * this may give more power-saving, but will take longer time to
 187  * wake up.
 188  */
 189 static bool power_save_controller = 1;
 190 module_param(power_save_controller, bool, 0644);
 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 192 #else
 193 #define power_save      0
 194 #endif /* CONFIG_PM */
 195
 196 static int align_buffer_size = -1;
 197 module_param(align_buffer_size, bint, 0644);
 198 MODULE_PARM_DESC(align_buffer_size,
 199                 "Force buffer and period sizes to be multiple of 128 bytes.");
 200
 201 #ifdef CONFIG_X86
 202 static int hda_snoop = -1;
 203 module_param_named(snoop, hda_snoop, bint, 0444);
 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 205 #else
 206 #define hda_snoop               true
 207 #endif
 208
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 212                          "{Intel, ICH6M},"
 213                          "{Intel, ICH7},"
 214                          "{Intel, ESB2},"
 215                          "{Intel, ICH8},"
 216                          "{Intel, ICH9},"
 217                          "{Intel, ICH10},"
 218                          "{Intel, PCH},"
 219                          "{Intel, CPT},"
 220                          "{Intel, PPT},"
 221                          "{Intel, LPT},"
 222                          "{Intel, LPT_LP},"
 223                          "{Intel, WPT_LP},"
 224                          "{Intel, SPT},"
 225                          "{Intel, SPT_LP},"
 226                          "{Intel, HPT},"
 227                          "{Intel, PBG},"
 228                          "{Intel, SCH},"
 229                          "{ATI, SB450},"
 230                          "{ATI, SB600},"
 231                          "{ATI, RS600},"
 232                          "{ATI, RS690},"
 233                          "{ATI, RS780},"
 234                          "{ATI, R600},"
 235                          "{ATI, RV630},"
 236                          "{ATI, RV610},"
 237                          "{ATI, RV670},"
 238                          "{ATI, RV635},"
 239                          "{ATI, RV620},"
 240                          "{ATI, RV770},"
 241                          "{VIA, VT8251},"
 242                          "{VIA, VT8237A},"
 243                          "{SiS, SIS966},"
 244                          "{ULI, M5461}}");
 245 MODULE_DESCRIPTION("Intel HDA driver");
 246
 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 249 #define SUPPORT_VGA_SWITCHEROO
 250 #endif
 251 #endif
 252
 253
 254 /*
 255  */
 256
 257 /* driver types */
 258 enum {
 259         AZX_DRIVER_ICH,
 260         AZX_DRIVER_PCH,
 261         AZX_DRIVER_SCH,
 262         AZX_DRIVER_SKL,
 263         AZX_DRIVER_HDMI,
 264         AZX_DRIVER_ATI,
 265         AZX_DRIVER_ATIHDMI,
 266         AZX_DRIVER_ATIHDMI_NS,
 267         AZX_DRIVER_VIA,
 268         AZX_DRIVER_SIS,
 269         AZX_DRIVER_ULI,
 270         AZX_DRIVER_NVIDIA,
 271         AZX_DRIVER_TERA,
 272         AZX_DRIVER_CTX,
 273         AZX_DRIVER_CTHDA,
 274         AZX_DRIVER_CMEDIA,
 275         AZX_DRIVER_ZHAOXIN,
 276         AZX_DRIVER_GENERIC,
 277         AZX_NUM_DRIVERS, /* keep this as last entry */
 278 };
 279
 280 #define azx_get_snoop_type(chip) \
 281         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 283
 284 /* quirks for old Intel chipsets */
 285 #define AZX_DCAPS_INTEL_ICH \
 286         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
 287          AZX_DCAPS_SYNC_WRITE)
 288
 289 /* quirks for Intel PCH */
 290 #define AZX_DCAPS_INTEL_PCH_BASE \
 291         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 292          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 293
 294 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 295 #define AZX_DCAPS_INTEL_PCH_NOPM \
 296         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 297
 298 /* PCH for HSW/BDW; with runtime PM */
 299 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 300 #define AZX_DCAPS_INTEL_PCH \
 301         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 302
 303 /* HSW HDMI */
 304 #define AZX_DCAPS_INTEL_HASWELL \
 305         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 306          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 307          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 308
 309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 310 #define AZX_DCAPS_INTEL_BROADWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 313          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 314
 315 #define AZX_DCAPS_INTEL_BAYTRAIL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 317
 318 #define AZX_DCAPS_INTEL_BRASWELL \
 319         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 320          AZX_DCAPS_I915_COMPONENT)
 321
 322 #define AZX_DCAPS_INTEL_SKYLAKE \
 323         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 324          AZX_DCAPS_SYNC_WRITE |\
 325          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 326
 327 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 328
 329 /* quirks for ATI SB / AMD Hudson */
 330 #define AZX_DCAPS_PRESET_ATI_SB \
 331         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 332          AZX_DCAPS_SNOOP_TYPE(ATI))
 333
 334 /* quirks for ATI/AMD HDMI */
 335 #define AZX_DCAPS_PRESET_ATI_HDMI \
 336         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 337          AZX_DCAPS_NO_MSI64)
 338
 339 /* quirks for ATI HDMI with snoop off */
 340 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 341         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 342
 343 /* quirks for AMD SB */
 344 #define AZX_DCAPS_PRESET_AMD_SB \
 345         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 346          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 347
 348 /* quirks for Nvidia */
 349 #define AZX_DCAPS_PRESET_NVIDIA \
 350         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 351          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 352
 353 #define AZX_DCAPS_PRESET_CTHDA \
 354         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 355          AZX_DCAPS_NO_64BIT |\
 356          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 357
 358 /*
 359  * vga_switcheroo support
 360  */
 361 #ifdef SUPPORT_VGA_SWITCHEROO
 362 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 363 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 364 #else
 365 #define use_vga_switcheroo(chip)        0
 366 #define needs_eld_notify_link(chip)     false
 367 #endif
 368
 369 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 370                                         ((pci)->device == 0x0c0c) || \
 371                                         ((pci)->device == 0x0d0c) || \
 372                                         ((pci)->device == 0x160c))
 373
 374 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 375
 376 static const char * const driver_short_names[] = {
 377         [AZX_DRIVER_ICH] = "HDA Intel",
 378         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 379         [AZX_DRIVER_SCH] = "HDA Intel MID",
 380         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 381         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 382         [AZX_DRIVER_ATI] = "HDA ATI SB",
 383         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 384         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 385         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 386         [AZX_DRIVER_SIS] = "HDA SIS966",
 387         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 388         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 389         [AZX_DRIVER_TERA] = "HDA Teradici",
 390         [AZX_DRIVER_CTX] = "HDA Creative",
 391         [AZX_DRIVER_CTHDA] = "HDA Creative",
 392         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 393         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 394         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 395 };
 396
 397 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 398 static void set_default_power_save(struct azx *chip);
 399
 400 /*
 401  * initialize the PCI registers
 402  */
 403 /* update bits in a PCI register byte */
 404 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 405                             unsigned char mask, unsigned char val)
 406 {
 407         unsigned char data;
 408
 409         pci_read_config_byte(pci, reg, &data);
 410         data &= ~mask;
 411         data |= (val & mask);
 412         pci_write_config_byte(pci, reg, data);
 413 }
 414
 415 static void azx_init_pci(struct azx *chip)
 416 {
 417         int snoop_type = azx_get_snoop_type(chip);
 418
 419         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 420          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 421          * Ensuring these bits are 0 clears playback static on some HD Audio
 422          * codecs.
 423          * The PCI register TCSEL is defined in the Intel manuals.
 424          */
 425         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 426                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 427                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 428         }
 429
 430         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 431          * we need to enable snoop.
 432          */
 433         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 434                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 435                         azx_snoop(chip));
 436                 update_pci_byte(chip->pci,
 437                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 438                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 439         }
 440
 441         /* For NVIDIA HDA, enable snoop */
 442         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 443                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 444                         azx_snoop(chip));
 445                 update_pci_byte(chip->pci,
 446                                 NVIDIA_HDA_TRANSREG_ADDR,
 447                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 448                 update_pci_byte(chip->pci,
 449                                 NVIDIA_HDA_ISTRM_COH,
 450                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 451                 update_pci_byte(chip->pci,
 452                                 NVIDIA_HDA_OSTRM_COH,
 453                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 454         }
 455
 456         /* Enable SCH/PCH snoop if needed */
 457         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 458                 unsigned short snoop;
 459                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 460                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 461                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 462                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 463                         if (!azx_snoop(chip))
 464                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 465                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 466                         pci_read_config_word(chip->pci,
 467                                 INTEL_SCH_HDA_DEVC, &snoop);
 468                 }
 469                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 470                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 471                         "Disabled" : "Enabled");
 472         }
 473 }
 474
 475 /*
 476  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 477  * and makes an audio stream sensitive to system latencies when
 478  * 24/32 bits are playing.
 479  * Adjusting threshold of DMA fifo to force the DMA request
 480  * sooner to improve latency tolerance at the expense of power.
 481  */
 482 static void bxt_reduce_dma_latency(struct azx *chip)
 483 {
 484         u32 val;
 485
 486         val = azx_readl(chip, VS_EM4L);
 487         val &= (0x3 << 20);
 488         azx_writel(chip, VS_EM4L, val);
 489 }
 490
 491 /*
 492  * ML_LCAP bits:
 493  *  bit 0: 6 MHz Supported
 494  *  bit 1: 12 MHz Supported
 495  *  bit 2: 24 MHz Supported
 496  *  bit 3: 48 MHz Supported
 497  *  bit 4: 96 MHz Supported
 498  *  bit 5: 192 MHz Supported
 499  */
 500 static int intel_get_lctl_scf(struct azx *chip)
 501 {
 502         struct hdac_bus *bus = azx_bus(chip);
 503         static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
 504         u32 val, t;
 505         int i;
 506
 507         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 508
 509         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 510                 t = preferred_bits[i];
 511                 if (val & (1 << t))
 512                         return t;
 513         }
 514
 515         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 516         return 0;
 517 }
 518
 519 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 520 {
 521         struct hdac_bus *bus = azx_bus(chip);
 522         u32 val;
 523         int timeout;
 524
 525         /*
 526          * the codecs are sharing the first link setting by default
 527          * If other links are enabled for stream, they need similar fix
 528          */
 529         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 530         val &= ~AZX_MLCTL_SPA;
 531         val |= state << AZX_MLCTL_SPA_SHIFT;
 532         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 533         /* wait for CPA */
 534         timeout = 50;
 535         while (timeout) {
 536                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 537                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 538                         return 0;
 539                 timeout--;
 540                 udelay(10);
 541         }
 542
 543         return -1;
 544 }
 545
 546 static void intel_init_lctl(struct azx *chip)
 547 {
 548         struct hdac_bus *bus = azx_bus(chip);
 549         u32 val;
 550         int ret;
 551
 552         /* 0. check lctl register value is correct or not */
 553         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 554         /* if SCF is already set, let's use it */
 555         if ((val & ML_LCTL_SCF_MASK) != 0)
 556                 return;
 557
 558         /*
 559          * Before operating on SPA, CPA must match SPA.
 560          * Any deviation may result in undefined behavior.
 561          */
 562         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 563                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 564                 return;
 565
 566         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 567         ret = intel_ml_lctl_set_power(chip, 0);
 568         udelay(100);
 569         if (ret)
 570                 goto set_spa;
 571
 572         /* 2. update SCF to select a properly audio clock*/
 573         val &= ~ML_LCTL_SCF_MASK;
 574         val |= intel_get_lctl_scf(chip);
 575         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 576
 577 set_spa:
 578         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 579         intel_ml_lctl_set_power(chip, 1);
 580         udelay(100);
 581 }
 582
 583 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 584 {
 585         struct hdac_bus *bus = azx_bus(chip);
 586         struct pci_dev *pci = chip->pci;
 587         u32 val;
 588
 589         snd_hdac_set_codec_wakeup(bus, true);
 590         if (chip->driver_type == AZX_DRIVER_SKL) {
 591                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 592                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 593                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 594         }
 595         azx_init_chip(chip, full_reset);
 596         if (chip->driver_type == AZX_DRIVER_SKL) {
 597                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 598                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 599                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 600         }
 601
 602         snd_hdac_set_codec_wakeup(bus, false);
 603
 604         /* reduce dma latency to avoid noise */
 605         if (IS_BXT(pci))
 606                 bxt_reduce_dma_latency(chip);
 607
 608         if (bus->mlcap != NULL)
 609                 intel_init_lctl(chip);
 610 }
 611
 612 /* calculate runtime delay from LPIB */
 613 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 614                                    unsigned int pos)
 615 {
 616         struct snd_pcm_substream *substream = azx_dev->core.substream;
 617         int stream = substream->stream;
 618         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 619         int delay;
 620
 621         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 622                 delay = pos - lpib_pos;
 623         else
 624                 delay = lpib_pos - pos;
 625         if (delay < 0) {
 626                 if (delay >= azx_dev->core.delay_negative_threshold)
 627                         delay = 0;
 628                 else
 629                         delay += azx_dev->core.bufsize;
 630         }
 631
 632         if (delay >= azx_dev->core.period_bytes) {
 633                 dev_info(chip->card->dev,
 634                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 635                          delay, azx_dev->core.period_bytes);
 636                 delay = 0;
 637                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 638                 chip->get_delay[stream] = NULL;
 639         }
 640
 641         return bytes_to_frames(substream->runtime, delay);
 642 }
 643
 644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 645
 646 /* called from IRQ */
 647 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 648 {
 649         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 650         int ok;
 651
 652         ok = azx_position_ok(chip, azx_dev);
 653         if (ok == 1) {
 654                 azx_dev->irq_pending = 0;
 655                 return ok;
 656         } else if (ok == 0) {
 657                 /* bogus IRQ, process it later */
 658                 azx_dev->irq_pending = 1;
 659                 schedule_work(&hda->irq_pending_work);
 660         }
 661         return 0;
 662 }
 663
 664 #define display_power(chip, enable) \
 665         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 666
 667 /*
 668  * Check whether the current DMA position is acceptable for updating
 669  * periods.  Returns non-zero if it's OK.
 670  *
 671  * Many HD-audio controllers appear pretty inaccurate about
 672  * the update-IRQ timing.  The IRQ is issued before actually the
 673  * data is processed.  So, we need to process it afterwords in a
 674  * workqueue.
 675  */
 676 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 677 {
 678         struct snd_pcm_substream *substream = azx_dev->core.substream;
 679         int stream = substream->stream;
 680         u32 wallclk;
 681         unsigned int pos;
 682
 683         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 684         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 685                 return -1;      /* bogus (too early) interrupt */
 686
 687         if (chip->get_position[stream])
 688                 pos = chip->get_position[stream](chip, azx_dev);
 689         else { /* use the position buffer as default */
 690                 pos = azx_get_pos_posbuf(chip, azx_dev);
 691                 if (!pos || pos == (u32)-1) {
 692                         dev_info(chip->card->dev,
 693                                  "Invalid position buffer, using LPIB read method instead.\n");
 694                         chip->get_position[stream] = azx_get_pos_lpib;
 695                         if (chip->get_position[0] == azx_get_pos_lpib &&
 696                             chip->get_position[1] == azx_get_pos_lpib)
 697                                 azx_bus(chip)->use_posbuf = false;
 698                         pos = azx_get_pos_lpib(chip, azx_dev);
 699                         chip->get_delay[stream] = NULL;
 700                 } else {
 701                         chip->get_position[stream] = azx_get_pos_posbuf;
 702                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 703                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 704                 }
 705         }
 706
 707         if (pos >= azx_dev->core.bufsize)
 708                 pos = 0;
 709
 710         if (WARN_ONCE(!azx_dev->core.period_bytes,
 711                       "hda-intel: zero azx_dev->period_bytes"))
 712                 return -1; /* this shouldn't happen! */
 713         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 714             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 715                 /* NG - it's below the first next period boundary */
 716                 return chip->bdl_pos_adj ? 0 : -1;
 717         azx_dev->core.start_wallclk += wallclk;
 718         return 1; /* OK, it's fine */
 719 }
 720
 721 /*
 722  * The work for pending PCM period updates.
 723  */
 724 static void azx_irq_pending_work(struct work_struct *work)
 725 {
 726         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 727         struct azx *chip = &hda->chip;
 728         struct hdac_bus *bus = azx_bus(chip);
 729         struct hdac_stream *s;
 730         int pending, ok;
 731
 732         if (!hda->irq_pending_warned) {
 733                 dev_info(chip->card->dev,
 734                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 735                          chip->card->number);
 736                 hda->irq_pending_warned = 1;
 737         }
 738
 739         for (;;) {
 740                 pending = 0;
 741                 spin_lock_irq(&bus->reg_lock);
 742                 list_for_each_entry(s, &bus->stream_list, list) {
 743                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 744                         if (!azx_dev->irq_pending ||
 745                             !s->substream ||
 746                             !s->running)
 747                                 continue;
 748                         ok = azx_position_ok(chip, azx_dev);
 749                         if (ok > 0) {
 750                                 azx_dev->irq_pending = 0;
 751                                 spin_unlock(&bus->reg_lock);
 752                                 snd_pcm_period_elapsed(s->substream);
 753                                 spin_lock(&bus->reg_lock);
 754                         } else if (ok < 0) {
 755                                 pending = 0;    /* too early */
 756                         } else
 757                                 pending++;
 758                 }
 759                 spin_unlock_irq(&bus->reg_lock);
 760                 if (!pending)
 761                         return;
 762                 msleep(1);
 763         }
 764 }
 765
 766 /* clear irq_pending flags and assure no on-going workq */
 767 static void azx_clear_irq_pending(struct azx *chip)
 768 {
 769         struct hdac_bus *bus = azx_bus(chip);
 770         struct hdac_stream *s;
 771
 772         spin_lock_irq(&bus->reg_lock);
 773         list_for_each_entry(s, &bus->stream_list, list) {
 774                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 775                 azx_dev->irq_pending = 0;
 776         }
 777         spin_unlock_irq(&bus->reg_lock);
 778 }
 779
 780 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 781 {
 782         struct hdac_bus *bus = azx_bus(chip);
 783
 784         if (request_irq(chip->pci->irq, azx_interrupt,
 785                         chip->msi ? 0 : IRQF_SHARED,
 786                         chip->card->irq_descr, chip)) {
 787                 dev_err(chip->card->dev,
 788                         "unable to grab IRQ %d, disabling device\n",
 789                         chip->pci->irq);
 790                 if (do_disconnect)
 791                         snd_card_disconnect(chip->card);
 792                 return -1;
 793         }
 794         bus->irq = chip->pci->irq;
 795         chip->card->sync_irq = bus->irq;
 796         pci_intx(chip->pci, !chip->msi);
 797         return 0;
 798 }
 799
 800 /* get the current DMA position with correction on VIA chips */
 801 static unsigned int azx_via_get_position(struct azx *chip,
 802                                          struct azx_dev *azx_dev)
 803 {
 804         unsigned int link_pos, mini_pos, bound_pos;
 805         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 806         unsigned int fifo_size;
 807
 808         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 809         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 810                 /* Playback, no problem using link position */
 811                 return link_pos;
 812         }
 813
 814         /* Capture */
 815         /* For new chipset,
 816          * use mod to get the DMA position just like old chipset
 817          */
 818         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 819         mod_dma_pos %= azx_dev->core.period_bytes;
 820
 821         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 822
 823         if (azx_dev->insufficient) {
 824                 /* Link position never gather than FIFO size */
 825                 if (link_pos <= fifo_size)
 826                         return 0;
 827
 828                 azx_dev->insufficient = 0;
 829         }
 830
 831         if (link_pos <= fifo_size)
 832                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 833         else
 834                 mini_pos = link_pos - fifo_size;
 835
 836         /* Find nearest previous boudary */
 837         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 838         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 839         if (mod_link_pos >= fifo_size)
 840                 bound_pos = link_pos - mod_link_pos;
 841         else if (mod_dma_pos >= mod_mini_pos)
 842                 bound_pos = mini_pos - mod_mini_pos;
 843         else {
 844                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 845                 if (bound_pos >= azx_dev->core.bufsize)
 846                         bound_pos = 0;
 847         }
 848
 849         /* Calculate real DMA position we want */
 850         return bound_pos + mod_dma_pos;
 851 }
 852
 853 #define AMD_FIFO_SIZE   32
 854
 855 /* get the current DMA position with FIFO size correction */
 856 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 857 {
 858         struct snd_pcm_substream *substream = azx_dev->core.substream;
 859         struct snd_pcm_runtime *runtime = substream->runtime;
 860         unsigned int pos, delay;
 861
 862         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 863         if (!runtime)
 864                 return pos;
 865
 866         runtime->delay = AMD_FIFO_SIZE;
 867         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 868         if (azx_dev->insufficient) {
 869                 if (pos < delay) {
 870                         delay = pos;
 871                         runtime->delay = bytes_to_frames(runtime, pos);
 872                 } else {
 873                         azx_dev->insufficient = 0;
 874                 }
 875         }
 876
 877         /* correct the DMA position for capture stream */
 878         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 879                 if (pos < delay)
 880                         pos += azx_dev->core.bufsize;
 881                 pos -= delay;
 882         }
 883
 884         return pos;
 885 }
 886
 887 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 888                                    unsigned int pos)
 889 {
 890         struct snd_pcm_substream *substream = azx_dev->core.substream;
 891
 892         /* just read back the calculated value in the above */
 893         return substream->runtime->delay;
 894 }
 895
 896 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 897                                          struct azx_dev *azx_dev)
 898 {
 899         return _snd_hdac_chip_readl(azx_bus(chip),
 900                                     AZX_REG_VS_SDXDPIB_XBASE +
 901                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 902                                      azx_dev->core.index));
 903 }
 904
 905 /* get the current DMA position with correction on SKL+ chips */
 906 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 907 {
 908         /* DPIB register gives a more accurate position for playback */
 909         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 910                 return azx_skl_get_dpib_pos(chip, azx_dev);
 911
 912         /* For capture, we need to read posbuf, but it requires a delay
 913          * for the possible boundary overlap; the read of DPIB fetches the
 914          * actual posbuf
 915          */
 916         udelay(20);
 917         azx_skl_get_dpib_pos(chip, azx_dev);
 918         return azx_get_pos_posbuf(chip, azx_dev);
 919 }
 920
 921 #ifdef CONFIG_PM
 922 static DEFINE_MUTEX(card_list_lock);
 923 static LIST_HEAD(card_list);
 924
 925 static void azx_add_card_list(struct azx *chip)
 926 {
 927         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 928         mutex_lock(&card_list_lock);
 929         list_add(&hda->list, &card_list);
 930         mutex_unlock(&card_list_lock);
 931 }
 932
 933 static void azx_del_card_list(struct azx *chip)
 934 {
 935         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 936         mutex_lock(&card_list_lock);
 937         list_del_init(&hda->list);
 938         mutex_unlock(&card_list_lock);
 939 }
 940
 941 /* trigger power-save check at writing parameter */
 942 static int param_set_xint(const char *val, const struct kernel_param *kp)
 943 {
 944         struct hda_intel *hda;
 945         struct azx *chip;
 946         int prev = power_save;
 947         int ret = param_set_int(val, kp);
 948
 949         if (ret || prev == power_save)
 950                 return ret;
 951
 952         mutex_lock(&card_list_lock);
 953         list_for_each_entry(hda, &card_list, list) {
 954                 chip = &hda->chip;
 955                 if (!hda->probe_continued || chip->disabled)
 956                         continue;
 957                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 958         }
 959         mutex_unlock(&card_list_lock);
 960         return 0;
 961 }
 962
 963 /*
 964  * power management
 965  */
 966 static bool azx_is_pm_ready(struct snd_card *card)
 967 {
 968         struct azx *chip;
 969         struct hda_intel *hda;
 970
 971         if (!card)
 972                 return false;
 973         chip = card->private_data;
 974         hda = container_of(chip, struct hda_intel, chip);
 975         if (chip->disabled || hda->init_failed || !chip->running)
 976                 return false;
 977         return true;
 978 }
 979
 980 static void __azx_runtime_suspend(struct azx *chip)
 981 {
 982         azx_stop_chip(chip);
 983         azx_enter_link_reset(chip);
 984         azx_clear_irq_pending(chip);
 985         display_power(chip, false);
 986 }
 987
 988 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 989 {
 990         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 991         struct hdac_bus *bus = azx_bus(chip);
 992         struct hda_codec *codec;
 993         int status;
 994
 995         display_power(chip, true);
 996         if (hda->need_i915_power)
 997                 snd_hdac_i915_set_bclk(bus);
 998
 999         /* Read STATESTS before controller reset */
1000         status = azx_readw(chip, STATESTS);
1001
1002         azx_init_pci(chip);
1003         hda_intel_init_chip(chip, true);
1004
1005         if (status && from_rt) {
1006                 list_for_each_codec(codec, &chip->bus)
1007                         if (!codec->relaxed_resume &&
1008                             (status & (1 << codec->addr)))
1009                                 schedule_delayed_work(&codec->jackpoll_work,
1010                                                       codec->jackpoll_interval);
1011         }
1012
1013         /* power down again for link-controlled chips */
1014         if (!hda->need_i915_power)
1015                 display_power(chip, false);
1016 }
1017
1018 #ifdef CONFIG_PM_SLEEP
1019 static int azx_suspend(struct device *dev)
1020 {
1021         struct snd_card *card = dev_get_drvdata(dev);
1022         struct azx *chip;
1023         struct hdac_bus *bus;
1024
1025         if (!azx_is_pm_ready(card))
1026                 return 0;
1027
1028         chip = card->private_data;
1029         bus = azx_bus(chip);
1030         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1031         pm_runtime_force_suspend(dev);
1032         if (bus->irq >= 0) {
1033                 free_irq(bus->irq, chip);
1034                 bus->irq = -1;
1035                 chip->card->sync_irq = -1;
1036         }
1037
1038         if (chip->msi)
1039                 pci_disable_msi(chip->pci);
1040
1041         trace_azx_suspend(chip);
1042         return 0;
1043 }
1044
1045 static int azx_resume(struct device *dev)
1046 {
1047         struct snd_card *card = dev_get_drvdata(dev);
1048         struct azx *chip;
1049
1050         if (!azx_is_pm_ready(card))
1051                 return 0;
1052
1053         chip = card->private_data;
1054         if (chip->msi)
1055                 if (pci_enable_msi(chip->pci) < 0)
1056                         chip->msi = 0;
1057         if (azx_acquire_irq(chip, 1) < 0)
1058                 return -EIO;
1059
1060         pm_runtime_force_resume(dev);
1061         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1062
1063         trace_azx_resume(chip);
1064         return 0;
1065 }
1066
1067 /* put codec down to D3 at hibernation for Intel SKL+;
1068  * otherwise BIOS may still access the codec and screw up the driver
1069  */
1070 static int azx_freeze_noirq(struct device *dev)
1071 {
1072         struct snd_card *card = dev_get_drvdata(dev);
1073         struct azx *chip = card->private_data;
1074         struct pci_dev *pci = to_pci_dev(dev);
1075
1076         if (!azx_is_pm_ready(card))
1077                 return 0;
1078         if (chip->driver_type == AZX_DRIVER_SKL)
1079                 pci_set_power_state(pci, PCI_D3hot);
1080
1081         return 0;
1082 }
1083
1084 static int azx_thaw_noirq(struct device *dev)
1085 {
1086         struct snd_card *card = dev_get_drvdata(dev);
1087         struct azx *chip = card->private_data;
1088         struct pci_dev *pci = to_pci_dev(dev);
1089
1090         if (!azx_is_pm_ready(card))
1091                 return 0;
1092         if (chip->driver_type == AZX_DRIVER_SKL)
1093                 pci_set_power_state(pci, PCI_D0);
1094
1095         return 0;
1096 }
1097 #endif /* CONFIG_PM_SLEEP */
1098
1099 static int azx_runtime_suspend(struct device *dev)
1100 {
1101         struct snd_card *card = dev_get_drvdata(dev);
1102         struct azx *chip;
1103
1104         if (!azx_is_pm_ready(card))
1105                 return 0;
1106         chip = card->private_data;
1107
1108         /* enable controller wake up event */
1109         if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) {
1110                 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1111                            STATESTS_INT_MASK);
1112         }
1113
1114         __azx_runtime_suspend(chip);
1115         trace_azx_runtime_suspend(chip);
1116         return 0;
1117 }
1118
1119 static int azx_runtime_resume(struct device *dev)
1120 {
1121         struct snd_card *card = dev_get_drvdata(dev);
1122         struct azx *chip;
1123         bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0;
1124
1125         if (!azx_is_pm_ready(card))
1126                 return 0;
1127         chip = card->private_data;
1128         __azx_runtime_resume(chip, from_rt);
1129
1130         /* disable controller Wake Up event*/
1131         if (from_rt) {
1132                 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1133                            ~STATESTS_INT_MASK);
1134         }
1135
1136         trace_azx_runtime_resume(chip);
1137         return 0;
1138 }
1139
1140 static int azx_runtime_idle(struct device *dev)
1141 {
1142         struct snd_card *card = dev_get_drvdata(dev);
1143         struct azx *chip;
1144         struct hda_intel *hda;
1145
1146         if (!card)
1147                 return 0;
1148
1149         chip = card->private_data;
1150         hda = container_of(chip, struct hda_intel, chip);
1151         if (chip->disabled || hda->init_failed)
1152                 return 0;
1153
1154         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1155             azx_bus(chip)->codec_powered || !chip->running)
1156                 return -EBUSY;
1157
1158         /* ELD notification gets broken when HD-audio bus is off */
1159         if (needs_eld_notify_link(chip))
1160                 return -EBUSY;
1161
1162         return 0;
1163 }
1164
1165 static const struct dev_pm_ops azx_pm = {
1166         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1167 #ifdef CONFIG_PM_SLEEP
1168         .freeze_noirq = azx_freeze_noirq,
1169         .thaw_noirq = azx_thaw_noirq,
1170 #endif
1171         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1172 };
1173
1174 #define AZX_PM_OPS      &azx_pm
1175 #else
1176 #define azx_add_card_list(chip) /* NOP */
1177 #define azx_del_card_list(chip) /* NOP */
1178 #define AZX_PM_OPS      NULL
1179 #endif /* CONFIG_PM */
1180
1181
1182 static int azx_probe_continue(struct azx *chip);
1183
1184 #ifdef SUPPORT_VGA_SWITCHEROO
1185 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1186
1187 static void azx_vs_set_state(struct pci_dev *pci,
1188                              enum vga_switcheroo_state state)
1189 {
1190         struct snd_card *card = pci_get_drvdata(pci);
1191         struct azx *chip = card->private_data;
1192         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1193         struct hda_codec *codec;
1194         bool disabled;
1195
1196         wait_for_completion(&hda->probe_wait);
1197         if (hda->init_failed)
1198                 return;
1199
1200         disabled = (state == VGA_SWITCHEROO_OFF);
1201         if (chip->disabled == disabled)
1202                 return;
1203
1204         if (!hda->probe_continued) {
1205                 chip->disabled = disabled;
1206                 if (!disabled) {
1207                         dev_info(chip->card->dev,
1208                                  "Start delayed initialization\n");
1209                         if (azx_probe_continue(chip) < 0)
1210                                 dev_err(chip->card->dev, "initialization error\n");
1211                 }
1212         } else {
1213                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1214                          disabled ? "Disabling" : "Enabling");
1215                 if (disabled) {
1216                         list_for_each_codec(codec, &chip->bus) {
1217                                 pm_runtime_suspend(hda_codec_dev(codec));
1218                                 pm_runtime_disable(hda_codec_dev(codec));
1219                         }
1220                         pm_runtime_suspend(card->dev);
1221                         pm_runtime_disable(card->dev);
1222                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1223                          * however we have no ACPI handle, so pci/acpi can't put us there,
1224                          * put ourselves there */
1225                         pci->current_state = PCI_D3cold;
1226                         chip->disabled = true;
1227                         if (snd_hda_lock_devices(&chip->bus))
1228                                 dev_warn(chip->card->dev,
1229                                          "Cannot lock devices!\n");
1230                 } else {
1231                         snd_hda_unlock_devices(&chip->bus);
1232                         chip->disabled = false;
1233                         pm_runtime_enable(card->dev);
1234                         list_for_each_codec(codec, &chip->bus) {
1235                                 pm_runtime_enable(hda_codec_dev(codec));
1236                                 pm_runtime_resume(hda_codec_dev(codec));
1237                         }
1238                 }
1239         }
1240 }
1241
1242 static bool azx_vs_can_switch(struct pci_dev *pci)
1243 {
1244         struct snd_card *card = pci_get_drvdata(pci);
1245         struct azx *chip = card->private_data;
1246         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1247
1248         wait_for_completion(&hda->probe_wait);
1249         if (hda->init_failed)
1250                 return false;
1251         if (chip->disabled || !hda->probe_continued)
1252                 return true;
1253         if (snd_hda_lock_devices(&chip->bus))
1254                 return false;
1255         snd_hda_unlock_devices(&chip->bus);
1256         return true;
1257 }
1258
1259 /*
1260  * The discrete GPU cannot power down unless the HDA controller runtime
1261  * suspends, so activate runtime PM on codecs even if power_save == 0.
1262  */
1263 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1264 {
1265         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1266         struct hda_codec *codec;
1267
1268         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1269                 list_for_each_codec(codec, &chip->bus)
1270                         codec->auto_runtime_pm = 1;
1271                 /* reset the power save setup */
1272                 if (chip->running)
1273                         set_default_power_save(chip);
1274         }
1275 }
1276
1277 static void azx_vs_gpu_bound(struct pci_dev *pci,
1278                              enum vga_switcheroo_client_id client_id)
1279 {
1280         struct snd_card *card = pci_get_drvdata(pci);
1281         struct azx *chip = card->private_data;
1282
1283         if (client_id == VGA_SWITCHEROO_DIS)
1284                 chip->bus.keep_power = 0;
1285         setup_vga_switcheroo_runtime_pm(chip);
1286 }
1287
1288 static void init_vga_switcheroo(struct azx *chip)
1289 {
1290         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1291         struct pci_dev *p = get_bound_vga(chip->pci);
1292         struct pci_dev *parent;
1293         if (p) {
1294                 dev_info(chip->card->dev,
1295                          "Handle vga_switcheroo audio client\n");
1296                 hda->use_vga_switcheroo = 1;
1297
1298                 /* cleared in either gpu_bound op or codec probe, or when its
1299                  * upstream port has _PR3 (i.e. dGPU).
1300                  */
1301                 parent = pci_upstream_bridge(p);
1302                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1303                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1304                 pci_dev_put(p);
1305         }
1306 }
1307
1308 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1309         .set_gpu_state = azx_vs_set_state,
1310         .can_switch = azx_vs_can_switch,
1311         .gpu_bound = azx_vs_gpu_bound,
1312 };
1313
1314 static int register_vga_switcheroo(struct azx *chip)
1315 {
1316         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1317         struct pci_dev *p;
1318         int err;
1319
1320         if (!hda->use_vga_switcheroo)
1321                 return 0;
1322
1323         p = get_bound_vga(chip->pci);
1324         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1325         pci_dev_put(p);
1326
1327         if (err < 0)
1328                 return err;
1329         hda->vga_switcheroo_registered = 1;
1330
1331         return 0;
1332 }
1333 #else
1334 #define init_vga_switcheroo(chip)               /* NOP */
1335 #define register_vga_switcheroo(chip)           0
1336 #define check_hdmi_disabled(pci)        false
1337 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1338 #endif /* SUPPORT_VGA_SWITCHER */
1339
1340 /*
1341  * destructor
1342  */
1343 static void azx_free(struct azx *chip)
1344 {
1345         struct pci_dev *pci = chip->pci;
1346         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1347         struct hdac_bus *bus = azx_bus(chip);
1348
1349         if (hda->freed)
1350                 return;
1351
1352         if (azx_has_pm_runtime(chip) && chip->running)
1353                 pm_runtime_get_noresume(&pci->dev);
1354         chip->running = 0;
1355
1356         azx_del_card_list(chip);
1357
1358         hda->init_failed = 1; /* to be sure */
1359         complete_all(&hda->probe_wait);
1360
1361         if (use_vga_switcheroo(hda)) {
1362                 if (chip->disabled && hda->probe_continued)
1363                         snd_hda_unlock_devices(&chip->bus);
1364                 if (hda->vga_switcheroo_registered)
1365                         vga_switcheroo_unregister_client(chip->pci);
1366         }
1367
1368         if (bus->chip_init) {
1369                 azx_clear_irq_pending(chip);
1370                 azx_stop_all_streams(chip);
1371                 azx_stop_chip(chip);
1372         }
1373
1374         if (bus->irq >= 0)
1375                 free_irq(bus->irq, (void*)chip);
1376         if (chip->msi)
1377                 pci_disable_msi(chip->pci);
1378         iounmap(bus->remap_addr);
1379
1380         azx_free_stream_pages(chip);
1381         azx_free_streams(chip);
1382         snd_hdac_bus_exit(bus);
1383
1384         if (chip->region_requested)
1385                 pci_release_regions(chip->pci);
1386
1387         pci_disable_device(chip->pci);
1388 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1389         release_firmware(chip->fw);
1390 #endif
1391         display_power(chip, false);
1392
1393         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1394                 snd_hdac_i915_exit(bus);
1395
1396         hda->freed = 1;
1397 }
1398
1399 static int azx_dev_disconnect(struct snd_device *device)
1400 {
1401         struct azx *chip = device->device_data;
1402         struct hdac_bus *bus = azx_bus(chip);
1403
1404         chip->bus.shutdown = 1;
1405         cancel_work_sync(&bus->unsol_work);
1406
1407         return 0;
1408 }
1409
1410 static int azx_dev_free(struct snd_device *device)
1411 {
1412         azx_free(device->device_data);
1413         return 0;
1414 }
1415
1416 #ifdef SUPPORT_VGA_SWITCHEROO
1417 #ifdef CONFIG_ACPI
1418 /* ATPX is in the integrated GPU's namespace */
1419 static bool atpx_present(void)
1420 {
1421         struct pci_dev *pdev = NULL;
1422         acpi_handle dhandle, atpx_handle;
1423         acpi_status status;
1424
1425         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1426                 dhandle = ACPI_HANDLE(&pdev->dev);
1427                 if (dhandle) {
1428                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1429                         if (!ACPI_FAILURE(status)) {
1430                                 pci_dev_put(pdev);
1431                                 return true;
1432                         }
1433                 }
1434         }
1435         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1436                 dhandle = ACPI_HANDLE(&pdev->dev);
1437                 if (dhandle) {
1438                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1439                         if (!ACPI_FAILURE(status)) {
1440                                 pci_dev_put(pdev);
1441                                 return true;
1442                         }
1443                 }
1444         }
1445         return false;
1446 }
1447 #else
1448 static bool atpx_present(void)
1449 {
1450         return false;
1451 }
1452 #endif
1453
1454 /*
1455  * Check of disabled HDMI controller by vga_switcheroo
1456  */
1457 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1458 {
1459         struct pci_dev *p;
1460
1461         /* check only discrete GPU */
1462         switch (pci->vendor) {
1463         case PCI_VENDOR_ID_ATI:
1464         case PCI_VENDOR_ID_AMD:
1465                 if (pci->devfn == 1) {
1466                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1467                                                         pci->bus->number, 0);
1468                         if (p) {
1469                                 /* ATPX is in the integrated GPU's ACPI namespace
1470                                  * rather than the dGPU's namespace. However,
1471                                  * the dGPU is the one who is involved in
1472                                  * vgaswitcheroo.
1473                                  */
1474                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1475                                     atpx_present())
1476                                         return p;
1477                                 pci_dev_put(p);
1478                         }
1479                 }
1480                 break;
1481         case PCI_VENDOR_ID_NVIDIA:
1482                 if (pci->devfn == 1) {
1483                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1484                                                         pci->bus->number, 0);
1485                         if (p) {
1486                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1487                                         return p;
1488                                 pci_dev_put(p);
1489                         }
1490                 }
1491                 break;
1492         }
1493         return NULL;
1494 }
1495
1496 static bool check_hdmi_disabled(struct pci_dev *pci)
1497 {
1498         bool vga_inactive = false;
1499         struct pci_dev *p = get_bound_vga(pci);
1500
1501         if (p) {
1502                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1503                         vga_inactive = true;
1504                 pci_dev_put(p);
1505         }
1506         return vga_inactive;
1507 }
1508 #endif /* SUPPORT_VGA_SWITCHEROO */
1509
1510 /*
1511  * white/black-listing for position_fix
1512  */
1513 static const struct snd_pci_quirk position_fix_list[] = {
1514         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1515         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1516         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1517         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1518         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1519         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1520         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1521         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1522         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1523         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1524         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1525         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1526         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1527         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1528         {}
1529 };
1530
1531 static int check_position_fix(struct azx *chip, int fix)
1532 {
1533         const struct snd_pci_quirk *q;
1534
1535         switch (fix) {
1536         case POS_FIX_AUTO:
1537         case POS_FIX_LPIB:
1538         case POS_FIX_POSBUF:
1539         case POS_FIX_VIACOMBO:
1540         case POS_FIX_COMBO:
1541         case POS_FIX_SKL:
1542         case POS_FIX_FIFO:
1543                 return fix;
1544         }
1545
1546         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1547         if (q) {
1548                 dev_info(chip->card->dev,
1549                          "position_fix set to %d for device %04x:%04x\n",
1550                          q->value, q->subvendor, q->subdevice);
1551                 return q->value;
1552         }
1553
1554         /* Check VIA/ATI HD Audio Controller exist */
1555         if (chip->driver_type == AZX_DRIVER_VIA) {
1556                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1557                 return POS_FIX_VIACOMBO;
1558         }
1559         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1560                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1561                 return POS_FIX_FIFO;
1562         }
1563         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1564                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1565                 return POS_FIX_LPIB;
1566         }
1567         if (chip->driver_type == AZX_DRIVER_SKL) {
1568                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1569                 return POS_FIX_SKL;
1570         }
1571         return POS_FIX_AUTO;
1572 }
1573
1574 static void assign_position_fix(struct azx *chip, int fix)
1575 {
1576         static const azx_get_pos_callback_t callbacks[] = {
1577                 [POS_FIX_AUTO] = NULL,
1578                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1579                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1580                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1581                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1582                 [POS_FIX_SKL] = azx_get_pos_skl,
1583                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1584         };
1585
1586         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1587
1588         /* combo mode uses LPIB only for playback */
1589         if (fix == POS_FIX_COMBO)
1590                 chip->get_position[1] = NULL;
1591
1592         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1593             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1594                 chip->get_delay[0] = chip->get_delay[1] =
1595                         azx_get_delay_from_lpib;
1596         }
1597
1598         if (fix == POS_FIX_FIFO)
1599                 chip->get_delay[0] = chip->get_delay[1] =
1600                         azx_get_delay_from_fifo;
1601 }
1602
1603 /*
1604  * black-lists for probe_mask
1605  */
1606 static const struct snd_pci_quirk probe_mask_list[] = {
1607         /* Thinkpad often breaks the controller communication when accessing
1608          * to the non-working (or non-existing) modem codec slot.
1609          */
1610         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1611         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1612         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1613         /* broken BIOS */
1614         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1615         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1616         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1617         /* forced codec slots */
1618         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1619         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1620         /* WinFast VP200 H (Teradici) user reported broken communication */
1621         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1622         {}
1623 };
1624
1625 #define AZX_FORCE_CODEC_MASK    0x100
1626
1627 static void check_probe_mask(struct azx *chip, int dev)
1628 {
1629         const struct snd_pci_quirk *q;
1630
1631         chip->codec_probe_mask = probe_mask[dev];
1632         if (chip->codec_probe_mask == -1) {
1633                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1634                 if (q) {
1635                         dev_info(chip->card->dev,
1636                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1637                                  q->value, q->subvendor, q->subdevice);
1638                         chip->codec_probe_mask = q->value;
1639                 }
1640         }
1641
1642         /* check forced option */
1643         if (chip->codec_probe_mask != -1 &&
1644             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1645                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1646                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1647                          (int)azx_bus(chip)->codec_mask);
1648         }
1649 }
1650
1651 /*
1652  * white/black-list for enable_msi
1653  */
1654 static const struct snd_pci_quirk msi_black_list[] = {
1655         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1656         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1657         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1658         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1659         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1660         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1661         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1662         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1663         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1664         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1665         {}
1666 };
1667
1668 static void check_msi(struct azx *chip)
1669 {
1670         const struct snd_pci_quirk *q;
1671
1672         if (enable_msi >= 0) {
1673                 chip->msi = !!enable_msi;
1674                 return;
1675         }
1676         chip->msi = 1;  /* enable MSI as default */
1677         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1678         if (q) {
1679                 dev_info(chip->card->dev,
1680                          "msi for device %04x:%04x set to %d\n",
1681                          q->subvendor, q->subdevice, q->value);
1682                 chip->msi = q->value;
1683                 return;
1684         }
1685
1686         /* NVidia chipsets seem to cause troubles with MSI */
1687         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1688                 dev_info(chip->card->dev, "Disabling MSI\n");
1689                 chip->msi = 0;
1690         }
1691 }
1692
1693 /* check the snoop mode availability */
1694 static void azx_check_snoop_available(struct azx *chip)
1695 {
1696         int snoop = hda_snoop;
1697
1698         if (snoop >= 0) {
1699                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1700                          snoop ? "snoop" : "non-snoop");
1701                 chip->snoop = snoop;
1702                 chip->uc_buffer = !snoop;
1703                 return;
1704         }
1705
1706         snoop = true;
1707         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1708             chip->driver_type == AZX_DRIVER_VIA) {
1709                 /* force to non-snoop mode for a new VIA controller
1710                  * when BIOS is set
1711                  */
1712                 u8 val;
1713                 pci_read_config_byte(chip->pci, 0x42, &val);
1714                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1715                                       chip->pci->revision == 0x20))
1716                         snoop = false;
1717         }
1718
1719         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1720                 snoop = false;
1721
1722         chip->snoop = snoop;
1723         if (!snoop) {
1724                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1725                 /* C-Media requires non-cached pages only for CORB/RIRB */
1726                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1727                         chip->uc_buffer = true;
1728         }
1729 }
1730
1731 static void azx_probe_work(struct work_struct *work)
1732 {
1733         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1734         azx_probe_continue(&hda->chip);
1735 }
1736
1737 static int default_bdl_pos_adj(struct azx *chip)
1738 {
1739         /* some exceptions: Atoms seem problematic with value 1 */
1740         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1741                 switch (chip->pci->device) {
1742                 case 0x0f04: /* Baytrail */
1743                 case 0x2284: /* Braswell */
1744                         return 32;
1745                 }
1746         }
1747
1748         switch (chip->driver_type) {
1749         case AZX_DRIVER_ICH:
1750         case AZX_DRIVER_PCH:
1751                 return 1;
1752         default:
1753                 return 32;
1754         }
1755 }
1756
1757 /*
1758  * constructor
1759  */
1760 static const struct hda_controller_ops pci_hda_ops;
1761
1762 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1763                       int dev, unsigned int driver_caps,
1764                       struct azx **rchip)
1765 {
1766         static const struct snd_device_ops ops = {
1767                 .dev_disconnect = azx_dev_disconnect,
1768                 .dev_free = azx_dev_free,
1769         };
1770         struct hda_intel *hda;
1771         struct azx *chip;
1772         int err;
1773
1774         *rchip = NULL;
1775
1776         err = pci_enable_device(pci);
1777         if (err < 0)
1778                 return err;
1779
1780         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1781         if (!hda) {
1782                 pci_disable_device(pci);
1783                 return -ENOMEM;
1784         }
1785
1786         chip = &hda->chip;
1787         mutex_init(&chip->open_mutex);
1788         chip->card = card;
1789         chip->pci = pci;
1790         chip->ops = &pci_hda_ops;
1791         chip->driver_caps = driver_caps;
1792         chip->driver_type = driver_caps & 0xff;
1793         check_msi(chip);
1794         chip->dev_index = dev;
1795         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1796                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1797         INIT_LIST_HEAD(&chip->pcm_list);
1798         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1799         INIT_LIST_HEAD(&hda->list);
1800         init_vga_switcheroo(chip);
1801         init_completion(&hda->probe_wait);
1802
1803         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1804
1805         check_probe_mask(chip, dev);
1806
1807         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1808                 chip->fallback_to_single_cmd = 1;
1809         else /* explicitly set to single_cmd or not */
1810                 chip->single_cmd = single_cmd;
1811
1812         azx_check_snoop_available(chip);
1813
1814         if (bdl_pos_adj[dev] < 0)
1815                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1816         else
1817                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1818
1819         err = azx_bus_init(chip, model[dev]);
1820         if (err < 0) {
1821                 pci_disable_device(pci);
1822                 return err;
1823         }
1824
1825         /* use the non-cached pages in non-snoop mode */
1826         if (!azx_snoop(chip))
1827                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1828
1829         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1830                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1831                 chip->bus.core.needs_damn_long_delay = 1;
1832         }
1833
1834         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1835         if (err < 0) {
1836                 dev_err(card->dev, "Error creating device [card]!\n");
1837                 azx_free(chip);
1838                 return err;
1839         }
1840
1841         /* continue probing in work context as may trigger request module */
1842         INIT_WORK(&hda->probe_work, azx_probe_work);
1843
1844         *rchip = chip;
1845
1846         return 0;
1847 }
1848
1849 static int azx_first_init(struct azx *chip)
1850 {
1851         int dev = chip->dev_index;
1852         struct pci_dev *pci = chip->pci;
1853         struct snd_card *card = chip->card;
1854         struct hdac_bus *bus = azx_bus(chip);
1855         int err;
1856         unsigned short gcap;
1857         unsigned int dma_bits = 64;
1858
1859 #if BITS_PER_LONG != 64
1860         /* Fix up base address on ULI M5461 */
1861         if (chip->driver_type == AZX_DRIVER_ULI) {
1862                 u16 tmp3;
1863                 pci_read_config_word(pci, 0x40, &tmp3);
1864                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1865                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1866         }
1867 #endif
1868
1869         err = pci_request_regions(pci, "ICH HD audio");
1870         if (err < 0)
1871                 return err;
1872         chip->region_requested = 1;
1873
1874         bus->addr = pci_resource_start(pci, 0);
1875         bus->remap_addr = pci_ioremap_bar(pci, 0);
1876         if (bus->remap_addr == NULL) {
1877                 dev_err(card->dev, "ioremap error\n");
1878                 return -ENXIO;
1879         }
1880
1881         if (chip->driver_type == AZX_DRIVER_SKL)
1882                 snd_hdac_bus_parse_capabilities(bus);
1883
1884         /*
1885          * Some Intel CPUs has always running timer (ART) feature and
1886          * controller may have Global time sync reporting capability, so
1887          * check both of these before declaring synchronized time reporting
1888          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1889          */
1890         chip->gts_present = false;
1891
1892 #ifdef CONFIG_X86
1893         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1894                 chip->gts_present = true;
1895 #endif
1896
1897         if (chip->msi) {
1898                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1899                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1900                         pci->no_64bit_msi = true;
1901                 }
1902                 if (pci_enable_msi(pci) < 0)
1903                         chip->msi = 0;
1904         }
1905
1906         pci_set_master(pci);
1907
1908         gcap = azx_readw(chip, GCAP);
1909         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1910
1911         /* AMD devices support 40 or 48bit DMA, take the safe one */
1912         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1913                 dma_bits = 40;
1914
1915         /* disable SB600 64bit support for safety */
1916         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1917                 struct pci_dev *p_smbus;
1918                 dma_bits = 40;
1919                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1920                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1921                                          NULL);
1922                 if (p_smbus) {
1923                         if (p_smbus->revision < 0x30)
1924                                 gcap &= ~AZX_GCAP_64OK;
1925                         pci_dev_put(p_smbus);
1926                 }
1927         }
1928
1929         /* NVidia hardware normally only supports up to 40 bits of DMA */
1930         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1931                 dma_bits = 40;
1932
1933         /* disable 64bit DMA address on some devices */
1934         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1935                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1936                 gcap &= ~AZX_GCAP_64OK;
1937         }
1938
1939         /* disable buffer size rounding to 128-byte multiples if supported */
1940         if (align_buffer_size >= 0)
1941                 chip->align_buffer_size = !!align_buffer_size;
1942         else {
1943                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1944                         chip->align_buffer_size = 0;
1945                 else
1946                         chip->align_buffer_size = 1;
1947         }
1948
1949         /* allow 64bit DMA address if supported by H/W */
1950         if (!(gcap & AZX_GCAP_64OK))
1951                 dma_bits = 32;
1952         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1953                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1954         } else {
1955                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1956                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1957         }
1958
1959         /* read number of streams from GCAP register instead of using
1960          * hardcoded value
1961          */
1962         chip->capture_streams = (gcap >> 8) & 0x0f;
1963         chip->playback_streams = (gcap >> 12) & 0x0f;
1964         if (!chip->playback_streams && !chip->capture_streams) {
1965                 /* gcap didn't give any info, switching to old method */
1966
1967                 switch (chip->driver_type) {
1968                 case AZX_DRIVER_ULI:
1969                         chip->playback_streams = ULI_NUM_PLAYBACK;
1970                         chip->capture_streams = ULI_NUM_CAPTURE;
1971                         break;
1972                 case AZX_DRIVER_ATIHDMI:
1973                 case AZX_DRIVER_ATIHDMI_NS:
1974                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1975                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1976                         break;
1977                 case AZX_DRIVER_GENERIC:
1978                 default:
1979                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1980                         chip->capture_streams = ICH6_NUM_CAPTURE;
1981                         break;
1982                 }
1983         }
1984         chip->capture_index_offset = 0;
1985         chip->playback_index_offset = chip->capture_streams;
1986         chip->num_streams = chip->playback_streams + chip->capture_streams;
1987
1988         /* sanity check for the SDxCTL.STRM field overflow */
1989         if (chip->num_streams > 15 &&
1990             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1991                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1992                          "forcing separate stream tags", chip->num_streams);
1993                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1994         }
1995
1996         /* initialize streams */
1997         err = azx_init_streams(chip);
1998         if (err < 0)
1999                 return err;
2000
2001         err = azx_alloc_stream_pages(chip);
2002         if (err < 0)
2003                 return err;
2004
2005         /* initialize chip */
2006         azx_init_pci(chip);
2007
2008         snd_hdac_i915_set_bclk(bus);
2009
2010         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2011
2012         /* codec detection */
2013         if (!azx_bus(chip)->codec_mask) {
2014                 dev_err(card->dev, "no codecs found!\n");
2015                 /* keep running the rest for the runtime PM */
2016         }
2017
2018         if (azx_acquire_irq(chip, 0) < 0)
2019                 return -EBUSY;
2020
2021         strcpy(card->driver, "HDA-Intel");
2022         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2023                 sizeof(card->shortname));
2024         snprintf(card->longname, sizeof(card->longname),
2025                  "%s at 0x%lx irq %i",
2026                  card->shortname, bus->addr, bus->irq);
2027
2028         return 0;
2029 }
2030
2031 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2032 /* callback from request_firmware_nowait() */
2033 static void azx_firmware_cb(const struct firmware *fw, void *context)
2034 {
2035         struct snd_card *card = context;
2036         struct azx *chip = card->private_data;
2037
2038         if (fw)
2039                 chip->fw = fw;
2040         else
2041                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2042         if (!chip->disabled) {
2043                 /* continue probing */
2044                 azx_probe_continue(chip);
2045         }
2046 }
2047 #endif
2048
2049 static int disable_msi_reset_irq(struct azx *chip)
2050 {
2051         struct hdac_bus *bus = azx_bus(chip);
2052         int err;
2053
2054         free_irq(bus->irq, chip);
2055         bus->irq = -1;
2056         chip->card->sync_irq = -1;
2057         pci_disable_msi(chip->pci);
2058         chip->msi = 0;
2059         err = azx_acquire_irq(chip, 1);
2060         if (err < 0)
2061                 return err;
2062
2063         return 0;
2064 }
2065
2066 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2067                              struct vm_area_struct *area)
2068 {
2069 #ifdef CONFIG_X86
2070         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2071         struct azx *chip = apcm->chip;
2072         if (chip->uc_buffer)
2073                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2074 #endif
2075 }
2076
2077 /* Blacklist for skipping the whole probe:
2078  * some HD-audio PCI entries are exposed without any codecs, and such devices
2079  * should be ignored from the beginning.
2080  */
2081 static const struct pci_device_id driver_blacklist[] = {
2082         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2083         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2084         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2085         {}
2086 };
2087
2088 static const struct hda_controller_ops pci_hda_ops = {
2089         .disable_msi_reset_irq = disable_msi_reset_irq,
2090         .pcm_mmap_prepare = pcm_mmap_prepare,
2091         .position_check = azx_position_check,
2092 };
2093
2094 static int azx_probe(struct pci_dev *pci,
2095                      const struct pci_device_id *pci_id)
2096 {
2097         static int dev;
2098         struct snd_card *card;
2099         struct hda_intel *hda;
2100         struct azx *chip;
2101         bool schedule_probe;
2102         int err;
2103
2104         if (pci_match_id(driver_blacklist, pci)) {
2105                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2106                 return -ENODEV;
2107         }
2108
2109         if (dev >= SNDRV_CARDS)
2110                 return -ENODEV;
2111         if (!enable[dev]) {
2112                 dev++;
2113                 return -ENOENT;
2114         }
2115
2116         /*
2117          * stop probe if another Intel's DSP driver should be activated
2118          */
2119         if (dmic_detect) {
2120                 err = snd_intel_dsp_driver_probe(pci);
2121                 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2122                     err != SND_INTEL_DSP_DRIVER_LEGACY)
2123                         return -ENODEV;
2124         } else {
2125                 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2126         }
2127
2128         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2129                            0, &card);
2130         if (err < 0) {
2131                 dev_err(&pci->dev, "Error creating card!\n");
2132                 return err;
2133         }
2134
2135         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2136         if (err < 0)
2137                 goto out_free;
2138         card->private_data = chip;
2139         hda = container_of(chip, struct hda_intel, chip);
2140
2141         pci_set_drvdata(pci, card);
2142
2143         err = register_vga_switcheroo(chip);
2144         if (err < 0) {
2145                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2146                 goto out_free;
2147         }
2148
2149         if (check_hdmi_disabled(pci)) {
2150                 dev_info(card->dev, "VGA controller is disabled\n");
2151                 dev_info(card->dev, "Delaying initialization\n");
2152                 chip->disabled = true;
2153         }
2154
2155         schedule_probe = !chip->disabled;
2156
2157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2158         if (patch[dev] && *patch[dev]) {
2159                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2160                          patch[dev]);
2161                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2162                                               &pci->dev, GFP_KERNEL, card,
2163                                               azx_firmware_cb);
2164                 if (err < 0)
2165                         goto out_free;
2166                 schedule_probe = false; /* continued in azx_firmware_cb() */
2167         }
2168 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2169
2170 #ifndef CONFIG_SND_HDA_I915
2171         if (CONTROLLER_IN_GPU(pci))
2172                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2173 #endif
2174
2175         if (schedule_probe)
2176                 schedule_work(&hda->probe_work);
2177
2178         dev++;
2179         if (chip->disabled)
2180                 complete_all(&hda->probe_wait);
2181         return 0;
2182
2183 out_free:
2184         snd_card_free(card);
2185         return err;
2186 }
2187
2188 #ifdef CONFIG_PM
2189 /* On some boards setting power_save to a non 0 value leads to clicking /
2190  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2191  * figure out how to avoid these sounds, but that is not always feasible.
2192  * So we keep a list of devices where we disable powersaving as its known
2193  * to causes problems on these devices.
2194  */
2195 static const struct snd_pci_quirk power_save_blacklist[] = {
2196         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2197         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2198         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2199         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2200         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2201         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2202         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2203         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2204         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2205         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2206         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2207         SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2208         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2209         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2210         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2211         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2212         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2213         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2214         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2215         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2216         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2217         /* https://bugs.launchpad.net/bugs/1821663 */
2218         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2219         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2220         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2221         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2222         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2223         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2224         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2225         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2226         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2227         /* https://bugs.launchpad.net/bugs/1821663 */
2228         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2229         {}
2230 };
2231 #endif /* CONFIG_PM */
2232
2233 static void set_default_power_save(struct azx *chip)
2234 {
2235         int val = power_save;
2236
2237 #ifdef CONFIG_PM
2238         if (pm_blacklist) {
2239                 const struct snd_pci_quirk *q;
2240
2241                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2242                 if (q && val) {
2243                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2244                                  q->subvendor, q->subdevice);
2245                         val = 0;
2246                 }
2247         }
2248 #endif /* CONFIG_PM */
2249         snd_hda_set_power_save(&chip->bus, val * 1000);
2250 }
2251
2252 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2253 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2254         [AZX_DRIVER_NVIDIA] = 8,
2255         [AZX_DRIVER_TERA] = 1,
2256 };
2257
2258 static int azx_probe_continue(struct azx *chip)
2259 {
2260         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2261         struct hdac_bus *bus = azx_bus(chip);
2262         struct pci_dev *pci = chip->pci;
2263         int dev = chip->dev_index;
2264         int err;
2265
2266         to_hda_bus(bus)->bus_probing = 1;
2267         hda->probe_continued = 1;
2268
2269         /* bind with i915 if needed */
2270         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2271                 err = snd_hdac_i915_init(bus);
2272                 if (err < 0) {
2273                         /* if the controller is bound only with HDMI/DP
2274                          * (for HSW and BDW), we need to abort the probe;
2275                          * for other chips, still continue probing as other
2276                          * codecs can be on the same link.
2277                          */
2278                         if (CONTROLLER_IN_GPU(pci)) {
2279                                 dev_err(chip->card->dev,
2280                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2281                                 goto out_free;
2282                         } else {
2283                                 /* don't bother any longer */
2284                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2285                         }
2286                 }
2287
2288                 /* HSW/BDW controllers need this power */
2289                 if (CONTROLLER_IN_GPU(pci))
2290                         hda->need_i915_power = 1;
2291         }
2292
2293         /* Request display power well for the HDA controller or codec. For
2294          * Haswell/Broadwell, both the display HDA controller and codec need
2295          * this power. For other platforms, like Baytrail/Braswell, only the
2296          * display codec needs the power and it can be released after probe.
2297          */
2298         display_power(chip, true);
2299
2300         err = azx_first_init(chip);
2301         if (err < 0)
2302                 goto out_free;
2303
2304 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2305         chip->beep_mode = beep_mode[dev];
2306 #endif
2307
2308         /* create codec instances */
2309         if (bus->codec_mask) {
2310                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2311                 if (err < 0)
2312                         goto out_free;
2313         }
2314
2315 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2316         if (chip->fw) {
2317                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2318                                          chip->fw->data);
2319                 if (err < 0)
2320                         goto out_free;
2321 #ifndef CONFIG_PM
2322                 release_firmware(chip->fw); /* no longer needed */
2323                 chip->fw = NULL;
2324 #endif
2325         }
2326 #endif
2327         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2328                 err = azx_codec_configure(chip);
2329                 if (err < 0)
2330                         goto out_free;
2331         }
2332
2333         err = snd_card_register(chip->card);
2334         if (err < 0)
2335                 goto out_free;
2336
2337         setup_vga_switcheroo_runtime_pm(chip);
2338
2339         chip->running = 1;
2340         azx_add_card_list(chip);
2341
2342         set_default_power_save(chip);
2343
2344         if (azx_has_pm_runtime(chip)) {
2345                 pm_runtime_use_autosuspend(&pci->dev);
2346                 pm_runtime_allow(&pci->dev);
2347                 pm_runtime_put_autosuspend(&pci->dev);
2348         }
2349
2350 out_free:
2351         if (err < 0) {
2352                 azx_free(chip);
2353                 return err;
2354         }
2355
2356         if (!hda->need_i915_power)
2357                 display_power(chip, false);
2358         complete_all(&hda->probe_wait);
2359         to_hda_bus(bus)->bus_probing = 0;
2360         return 0;
2361 }
2362
2363 static void azx_remove(struct pci_dev *pci)
2364 {
2365         struct snd_card *card = pci_get_drvdata(pci);
2366         struct azx *chip;
2367         struct hda_intel *hda;
2368
2369         if (card) {
2370                 /* cancel the pending probing work */
2371                 chip = card->private_data;
2372                 hda = container_of(chip, struct hda_intel, chip);
2373                 /* FIXME: below is an ugly workaround.
2374                  * Both device_release_driver() and driver_probe_device()
2375                  * take *both* the device's and its parent's lock before
2376                  * calling the remove() and probe() callbacks.  The codec
2377                  * probe takes the locks of both the codec itself and its
2378                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2379                  * the PCI controller is unbound, it takes its lock, too
2380                  * ==> ouch, a deadlock!
2381                  * As a workaround, we unlock temporarily here the controller
2382                  * device during cancel_work_sync() call.
2383                  */
2384                 device_unlock(&pci->dev);
2385                 cancel_work_sync(&hda->probe_work);
2386                 device_lock(&pci->dev);
2387
2388                 snd_card_free(card);
2389         }
2390 }
2391
2392 static void azx_shutdown(struct pci_dev *pci)
2393 {
2394         struct snd_card *card = pci_get_drvdata(pci);
2395         struct azx *chip;
2396
2397         if (!card)
2398                 return;
2399         chip = card->private_data;
2400         if (chip && chip->running)
2401                 azx_stop_chip(chip);
2402 }
2403
2404 /* PCI IDs */
2405 static const struct pci_device_id azx_ids[] = {
2406         /* CPT */
2407         { PCI_DEVICE(0x8086, 0x1c20),
2408           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2409         /* PBG */
2410         { PCI_DEVICE(0x8086, 0x1d20),
2411           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2412         /* Panther Point */
2413         { PCI_DEVICE(0x8086, 0x1e20),
2414           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2415         /* Lynx Point */
2416         { PCI_DEVICE(0x8086, 0x8c20),
2417           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2418         /* 9 Series */
2419         { PCI_DEVICE(0x8086, 0x8ca0),
2420           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2421         /* Wellsburg */
2422         { PCI_DEVICE(0x8086, 0x8d20),
2423           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2424         { PCI_DEVICE(0x8086, 0x8d21),
2425           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2426         /* Lewisburg */
2427         { PCI_DEVICE(0x8086, 0xa1f0),
2428           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2429         { PCI_DEVICE(0x8086, 0xa270),
2430           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2431         /* Lynx Point-LP */
2432         { PCI_DEVICE(0x8086, 0x9c20),
2433           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2434         /* Lynx Point-LP */
2435         { PCI_DEVICE(0x8086, 0x9c21),
2436           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2437         /* Wildcat Point-LP */
2438         { PCI_DEVICE(0x8086, 0x9ca0),
2439           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2440         /* Sunrise Point */
2441         { PCI_DEVICE(0x8086, 0xa170),
2442           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2443         /* Sunrise Point-LP */
2444         { PCI_DEVICE(0x8086, 0x9d70),
2445           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2446         /* Kabylake */
2447         { PCI_DEVICE(0x8086, 0xa171),
2448           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2449         /* Kabylake-LP */
2450         { PCI_DEVICE(0x8086, 0x9d71),
2451           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2452         /* Kabylake-H */
2453         { PCI_DEVICE(0x8086, 0xa2f0),
2454           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2455         /* Coffelake */
2456         { PCI_DEVICE(0x8086, 0xa348),
2457           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2458         /* Cannonlake */
2459         { PCI_DEVICE(0x8086, 0x9dc8),
2460           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2461         /* CometLake-LP */
2462         { PCI_DEVICE(0x8086, 0x02C8),
2463           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2464         /* CometLake-H */
2465         { PCI_DEVICE(0x8086, 0x06C8),
2466           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2467         /* CometLake-S */
2468         { PCI_DEVICE(0x8086, 0xa3f0),
2469           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2470         /* Icelake */
2471         { PCI_DEVICE(0x8086, 0x34c8),
2472           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2473         /* Jasperlake */
2474         { PCI_DEVICE(0x8086, 0x38c8),
2475           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2476         { PCI_DEVICE(0x8086, 0x4dc8),
2477           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2478         /* Tigerlake */
2479         { PCI_DEVICE(0x8086, 0xa0c8),
2480           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2481         /* Elkhart Lake */
2482         { PCI_DEVICE(0x8086, 0x4b55),
2483           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2484         /* Broxton-P(Apollolake) */
2485         { PCI_DEVICE(0x8086, 0x5a98),
2486           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2487         /* Broxton-T */
2488         { PCI_DEVICE(0x8086, 0x1a98),
2489           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2490         /* Gemini-Lake */
2491         { PCI_DEVICE(0x8086, 0x3198),
2492           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2493         /* Haswell */
2494         { PCI_DEVICE(0x8086, 0x0a0c),
2495           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2496         { PCI_DEVICE(0x8086, 0x0c0c),
2497           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2498         { PCI_DEVICE(0x8086, 0x0d0c),
2499           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2500         /* Broadwell */
2501         { PCI_DEVICE(0x8086, 0x160c),
2502           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2503         /* 5 Series/3400 */
2504         { PCI_DEVICE(0x8086, 0x3b56),
2505           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2506         /* Poulsbo */
2507         { PCI_DEVICE(0x8086, 0x811b),
2508           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2509         /* Oaktrail */
2510         { PCI_DEVICE(0x8086, 0x080a),
2511           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2512         /* BayTrail */
2513         { PCI_DEVICE(0x8086, 0x0f04),
2514           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2515         /* Braswell */
2516         { PCI_DEVICE(0x8086, 0x2284),
2517           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2518         /* ICH6 */
2519         { PCI_DEVICE(0x8086, 0x2668),
2520           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2521         /* ICH7 */
2522         { PCI_DEVICE(0x8086, 0x27d8),
2523           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2524         /* ESB2 */
2525         { PCI_DEVICE(0x8086, 0x269a),
2526           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2527         /* ICH8 */
2528         { PCI_DEVICE(0x8086, 0x284b),
2529           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2530         /* ICH9 */
2531         { PCI_DEVICE(0x8086, 0x293e),
2532           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2533         /* ICH9 */
2534         { PCI_DEVICE(0x8086, 0x293f),
2535           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2536         /* ICH10 */
2537         { PCI_DEVICE(0x8086, 0x3a3e),
2538           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2539         /* ICH10 */
2540         { PCI_DEVICE(0x8086, 0x3a6e),
2541           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2542         /* Generic Intel */
2543         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2544           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2545           .class_mask = 0xffffff,
2546           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2547         /* ATI SB 450/600/700/800/900 */
2548         { PCI_DEVICE(0x1002, 0x437b),
2549           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2550         { PCI_DEVICE(0x1002, 0x4383),
2551           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2552         /* AMD Hudson */
2553         { PCI_DEVICE(0x1022, 0x780d),
2554           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2555         /* AMD, X370 & co */
2556         { PCI_DEVICE(0x1022, 0x1457),
2557           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2558         /* AMD, X570 & co */
2559         { PCI_DEVICE(0x1022, 0x1487),
2560           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2561         /* AMD Stoney */
2562         { PCI_DEVICE(0x1022, 0x157a),
2563           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2564                          AZX_DCAPS_PM_RUNTIME },
2565         /* AMD Raven */
2566         { PCI_DEVICE(0x1022, 0x15e3),
2567           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2568         /* ATI HDMI */
2569         { PCI_DEVICE(0x1002, 0x0002),
2570           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2571         { PCI_DEVICE(0x1002, 0x1308),
2572           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2573         { PCI_DEVICE(0x1002, 0x157a),
2574           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2575         { PCI_DEVICE(0x1002, 0x15b3),
2576           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2577         { PCI_DEVICE(0x1002, 0x793b),
2578           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2579         { PCI_DEVICE(0x1002, 0x7919),
2580           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2581         { PCI_DEVICE(0x1002, 0x960f),
2582           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2583         { PCI_DEVICE(0x1002, 0x970f),
2584           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2585         { PCI_DEVICE(0x1002, 0x9840),
2586           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2587         { PCI_DEVICE(0x1002, 0xaa00),
2588           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2589         { PCI_DEVICE(0x1002, 0xaa08),
2590           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591         { PCI_DEVICE(0x1002, 0xaa10),
2592           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2593         { PCI_DEVICE(0x1002, 0xaa18),
2594           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595         { PCI_DEVICE(0x1002, 0xaa20),
2596           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597         { PCI_DEVICE(0x1002, 0xaa28),
2598           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599         { PCI_DEVICE(0x1002, 0xaa30),
2600           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2601         { PCI_DEVICE(0x1002, 0xaa38),
2602           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2603         { PCI_DEVICE(0x1002, 0xaa40),
2604           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605         { PCI_DEVICE(0x1002, 0xaa48),
2606           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2607         { PCI_DEVICE(0x1002, 0xaa50),
2608           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609         { PCI_DEVICE(0x1002, 0xaa58),
2610           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611         { PCI_DEVICE(0x1002, 0xaa60),
2612           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613         { PCI_DEVICE(0x1002, 0xaa68),
2614           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615         { PCI_DEVICE(0x1002, 0xaa80),
2616           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617         { PCI_DEVICE(0x1002, 0xaa88),
2618           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619         { PCI_DEVICE(0x1002, 0xaa90),
2620           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621         { PCI_DEVICE(0x1002, 0xaa98),
2622           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623         { PCI_DEVICE(0x1002, 0x9902),
2624           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2625         { PCI_DEVICE(0x1002, 0xaaa0),
2626           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2627         { PCI_DEVICE(0x1002, 0xaaa8),
2628           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2629         { PCI_DEVICE(0x1002, 0xaab0),
2630           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2631         { PCI_DEVICE(0x1002, 0xaac0),
2632           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2633         { PCI_DEVICE(0x1002, 0xaac8),
2634           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2635         { PCI_DEVICE(0x1002, 0xaad8),
2636           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2637           AZX_DCAPS_PM_RUNTIME },
2638         { PCI_DEVICE(0x1002, 0xaae0),
2639           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2640           AZX_DCAPS_PM_RUNTIME },
2641         { PCI_DEVICE(0x1002, 0xaae8),
2642           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2643           AZX_DCAPS_PM_RUNTIME },
2644         { PCI_DEVICE(0x1002, 0xaaf0),
2645           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2646           AZX_DCAPS_PM_RUNTIME },
2647         { PCI_DEVICE(0x1002, 0xaaf8),
2648           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2649           AZX_DCAPS_PM_RUNTIME },
2650         { PCI_DEVICE(0x1002, 0xab00),
2651           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2652           AZX_DCAPS_PM_RUNTIME },
2653         { PCI_DEVICE(0x1002, 0xab08),
2654           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2655           AZX_DCAPS_PM_RUNTIME },
2656         { PCI_DEVICE(0x1002, 0xab10),
2657           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2658           AZX_DCAPS_PM_RUNTIME },
2659         { PCI_DEVICE(0x1002, 0xab18),
2660           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2661           AZX_DCAPS_PM_RUNTIME },
2662         { PCI_DEVICE(0x1002, 0xab20),
2663           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2664           AZX_DCAPS_PM_RUNTIME },
2665         { PCI_DEVICE(0x1002, 0xab28),
2666           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2667           AZX_DCAPS_PM_RUNTIME },
2668         { PCI_DEVICE(0x1002, 0xab38),
2669           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2670           AZX_DCAPS_PM_RUNTIME },
2671         /* VIA VT8251/VT8237A */
2672         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2673         /* VIA GFX VT7122/VX900 */
2674         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2675         /* VIA GFX VT6122/VX11 */
2676         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2677         /* SIS966 */
2678         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2679         /* ULI M5461 */
2680         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2681         /* NVIDIA MCP */
2682         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2683           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2684           .class_mask = 0xffffff,
2685           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2686         /* Teradici */
2687         { PCI_DEVICE(0x6549, 0x1200),
2688           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2689         { PCI_DEVICE(0x6549, 0x2200),
2690           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2691         /* Creative X-Fi (CA0110-IBG) */
2692         /* CTHDA chips */
2693         { PCI_DEVICE(0x1102, 0x0010),
2694           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2695         { PCI_DEVICE(0x1102, 0x0012),
2696           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2697 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2698         /* the following entry conflicts with snd-ctxfi driver,
2699          * as ctxfi driver mutates from HD-audio to native mode with
2700          * a special command sequence.
2701          */
2702         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2703           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2704           .class_mask = 0xffffff,
2705           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2706           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2707 #else
2708         /* this entry seems still valid -- i.e. without emu20kx chip */
2709         { PCI_DEVICE(0x1102, 0x0009),
2710           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2711           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2712 #endif
2713         /* CM8888 */
2714         { PCI_DEVICE(0x13f6, 0x5011),
2715           .driver_data = AZX_DRIVER_CMEDIA |
2716           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2717         /* Vortex86MX */
2718         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2719         /* VMware HDAudio */
2720         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2721         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2722         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2723           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2724           .class_mask = 0xffffff,
2725           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2726         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2727           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2728           .class_mask = 0xffffff,
2729           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2730         /* Zhaoxin */
2731         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2732         { 0, }
2733 };
2734 MODULE_DEVICE_TABLE(pci, azx_ids);
2735
2736 /* pci_driver definition */
2737 static struct pci_driver azx_driver = {
2738         .name = KBUILD_MODNAME,
2739         .id_table = azx_ids,
2740         .probe = azx_probe,
2741         .remove = azx_remove,
2742         .shutdown = azx_shutdown,
2743         .driver = {
2744                 .pm = AZX_PM_OPS,
2745         },
2746 };
2747
2748 module_pci_driver(azx_driver);