sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pgtable.h>
  40
  41 #ifdef CONFIG_X86
  42 /* for snoop control */
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/firmware.h>
  54 #include <sound/hda_codec.h>
  55 #include "hda_controller.h"
  56 #include "hda_intel.h"
  57
  58 #define CREATE_TRACE_POINTS
  59 #include "hda_intel_trace.h"
  60
  61 /* position fix mode */
  62 enum {
  63         POS_FIX_AUTO,
  64         POS_FIX_LPIB,
  65         POS_FIX_POSBUF,
  66         POS_FIX_VIACOMBO,
  67         POS_FIX_COMBO,
  68         POS_FIX_SKL,
  69         POS_FIX_FIFO,
  70 };
  71
  72 /* Defines for ATI HD Audio support in SB450 south bridge */
  73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  75
  76 /* Defines for Nvidia HDA support */
  77 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  78 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  79 #define NVIDIA_HDA_ISTRM_COH          0x4d
  80 #define NVIDIA_HDA_OSTRM_COH          0x4c
  81 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  82
  83 /* Defines for Intel SCH HDA snoop control */
  84 #define INTEL_HDA_CGCTL  0x48
  85 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  86 #define INTEL_SCH_HDA_DEVC      0x78
  87 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  88
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = 1;
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
 165                              "(0=off, 1=on) (default=1); "
 166                  "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
 167
 168 #ifdef CONFIG_PM
 169 static int param_set_xint(const char *val, const struct kernel_param *kp);
 170 static const struct kernel_param_ops param_ops_xint = {
 171         .set = param_set_xint,
 172         .get = param_get_int,
 173 };
 174 #define param_check_xint param_check_int
 175
 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 177 module_param(power_save, xint, 0644);
 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 179                  "(in second, 0 = disable).");
 180
 181 static bool pm_blacklist = true;
 182 module_param(pm_blacklist, bool, 0644);
 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
 184
 185 /* reset the HD-audio controller in power save mode.
 186  * this may give more power-saving, but will take longer time to
 187  * wake up.
 188  */
 189 static bool power_save_controller = 1;
 190 module_param(power_save_controller, bool, 0644);
 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 192 #else
 193 #define power_save      0
 194 #endif /* CONFIG_PM */
 195
 196 static int align_buffer_size = -1;
 197 module_param(align_buffer_size, bint, 0644);
 198 MODULE_PARM_DESC(align_buffer_size,
 199                 "Force buffer and period sizes to be multiple of 128 bytes.");
 200
 201 #ifdef CONFIG_X86
 202 static int hda_snoop = -1;
 203 module_param_named(snoop, hda_snoop, bint, 0444);
 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 205 #else
 206 #define hda_snoop               true
 207 #endif
 208
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_DESCRIPTION("Intel HDA driver");
 212
 213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 215 #define SUPPORT_VGA_SWITCHEROO
 216 #endif
 217 #endif
 218
 219
 220 /*
 221  */
 222
 223 /* driver types */
 224 enum {
 225         AZX_DRIVER_ICH,
 226         AZX_DRIVER_PCH,
 227         AZX_DRIVER_SCH,
 228         AZX_DRIVER_SKL,
 229         AZX_DRIVER_HDMI,
 230         AZX_DRIVER_ATI,
 231         AZX_DRIVER_ATIHDMI,
 232         AZX_DRIVER_ATIHDMI_NS,
 233         AZX_DRIVER_VIA,
 234         AZX_DRIVER_SIS,
 235         AZX_DRIVER_ULI,
 236         AZX_DRIVER_NVIDIA,
 237         AZX_DRIVER_TERA,
 238         AZX_DRIVER_CTX,
 239         AZX_DRIVER_CTHDA,
 240         AZX_DRIVER_CMEDIA,
 241         AZX_DRIVER_ZHAOXIN,
 242         AZX_DRIVER_GENERIC,
 243         AZX_NUM_DRIVERS, /* keep this as last entry */
 244 };
 245
 246 #define azx_get_snoop_type(chip) \
 247         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 249
 250 /* quirks for old Intel chipsets */
 251 #define AZX_DCAPS_INTEL_ICH \
 252         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 253
 254 /* quirks for Intel PCH */
 255 #define AZX_DCAPS_INTEL_PCH_BASE \
 256         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 257          AZX_DCAPS_SNOOP_TYPE(SCH))
 258
 259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 260 #define AZX_DCAPS_INTEL_PCH_NOPM \
 261         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 262
 263 /* PCH for HSW/BDW; with runtime PM */
 264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 265 #define AZX_DCAPS_INTEL_PCH \
 266         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 267
 268 /* HSW HDMI */
 269 #define AZX_DCAPS_INTEL_HASWELL \
 270         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 271          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 272          AZX_DCAPS_SNOOP_TYPE(SCH))
 273
 274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 275 #define AZX_DCAPS_INTEL_BROADWELL \
 276         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 277          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 278          AZX_DCAPS_SNOOP_TYPE(SCH))
 279
 280 #define AZX_DCAPS_INTEL_BAYTRAIL \
 281         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 282
 283 #define AZX_DCAPS_INTEL_BRASWELL \
 284         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 285          AZX_DCAPS_I915_COMPONENT)
 286
 287 #define AZX_DCAPS_INTEL_SKYLAKE \
 288         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 289          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 290
 291 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 292
 293 /* quirks for ATI SB / AMD Hudson */
 294 #define AZX_DCAPS_PRESET_ATI_SB \
 295         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
 296          AZX_DCAPS_SNOOP_TYPE(ATI))
 297
 298 /* quirks for ATI/AMD HDMI */
 299 #define AZX_DCAPS_PRESET_ATI_HDMI \
 300         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
 301          AZX_DCAPS_NO_MSI64)
 302
 303 /* quirks for ATI HDMI with snoop off */
 304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 305         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 306
 307 /* quirks for AMD SB */
 308 #define AZX_DCAPS_PRESET_AMD_SB \
 309         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
 310          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 311
 312 /* quirks for Nvidia */
 313 #define AZX_DCAPS_PRESET_NVIDIA \
 314         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 315          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 316
 317 #define AZX_DCAPS_PRESET_CTHDA \
 318         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_NO_64BIT |\
 320          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 321
 322 /*
 323  * vga_switcheroo support
 324  */
 325 #ifdef SUPPORT_VGA_SWITCHEROO
 326 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 327 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 328 #else
 329 #define use_vga_switcheroo(chip)        0
 330 #define needs_eld_notify_link(chip)     false
 331 #endif
 332
 333 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 334                                         ((pci)->device == 0x0c0c) || \
 335                                         ((pci)->device == 0x0d0c) || \
 336                                         ((pci)->device == 0x160c) || \
 337                                         ((pci)->device == 0x490d))
 338
 339 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 340
 341 static const char * const driver_short_names[] = {
 342         [AZX_DRIVER_ICH] = "HDA Intel",
 343         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 344         [AZX_DRIVER_SCH] = "HDA Intel MID",
 345         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 346         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 347         [AZX_DRIVER_ATI] = "HDA ATI SB",
 348         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 349         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 350         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 351         [AZX_DRIVER_SIS] = "HDA SIS966",
 352         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 353         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 354         [AZX_DRIVER_TERA] = "HDA Teradici",
 355         [AZX_DRIVER_CTX] = "HDA Creative",
 356         [AZX_DRIVER_CTHDA] = "HDA Creative",
 357         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 358         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 359         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 360 };
 361
 362 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 363 static void set_default_power_save(struct azx *chip);
 364
 365 /*
 366  * initialize the PCI registers
 367  */
 368 /* update bits in a PCI register byte */
 369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 370                             unsigned char mask, unsigned char val)
 371 {
 372         unsigned char data;
 373
 374         pci_read_config_byte(pci, reg, &data);
 375         data &= ~mask;
 376         data |= (val & mask);
 377         pci_write_config_byte(pci, reg, data);
 378 }
 379
 380 static void azx_init_pci(struct azx *chip)
 381 {
 382         int snoop_type = azx_get_snoop_type(chip);
 383
 384         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 385          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 386          * Ensuring these bits are 0 clears playback static on some HD Audio
 387          * codecs.
 388          * The PCI register TCSEL is defined in the Intel manuals.
 389          */
 390         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 391                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 392                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 393         }
 394
 395         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 396          * we need to enable snoop.
 397          */
 398         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 399                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 400                         azx_snoop(chip));
 401                 update_pci_byte(chip->pci,
 402                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 403                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 404         }
 405
 406         /* For NVIDIA HDA, enable snoop */
 407         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 408                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 409                         azx_snoop(chip));
 410                 update_pci_byte(chip->pci,
 411                                 NVIDIA_HDA_TRANSREG_ADDR,
 412                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 413                 update_pci_byte(chip->pci,
 414                                 NVIDIA_HDA_ISTRM_COH,
 415                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 416                 update_pci_byte(chip->pci,
 417                                 NVIDIA_HDA_OSTRM_COH,
 418                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 419         }
 420
 421         /* Enable SCH/PCH snoop if needed */
 422         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 423                 unsigned short snoop;
 424                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 425                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 426                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 427                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 428                         if (!azx_snoop(chip))
 429                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 430                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 431                         pci_read_config_word(chip->pci,
 432                                 INTEL_SCH_HDA_DEVC, &snoop);
 433                 }
 434                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 435                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 436                         "Disabled" : "Enabled");
 437         }
 438 }
 439
 440 /*
 441  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 442  * and makes an audio stream sensitive to system latencies when
 443  * 24/32 bits are playing.
 444  * Adjusting threshold of DMA fifo to force the DMA request
 445  * sooner to improve latency tolerance at the expense of power.
 446  */
 447 static void bxt_reduce_dma_latency(struct azx *chip)
 448 {
 449         u32 val;
 450
 451         val = azx_readl(chip, VS_EM4L);
 452         val &= (0x3 << 20);
 453         azx_writel(chip, VS_EM4L, val);
 454 }
 455
 456 /*
 457  * ML_LCAP bits:
 458  *  bit 0: 6 MHz Supported
 459  *  bit 1: 12 MHz Supported
 460  *  bit 2: 24 MHz Supported
 461  *  bit 3: 48 MHz Supported
 462  *  bit 4: 96 MHz Supported
 463  *  bit 5: 192 MHz Supported
 464  */
 465 static int intel_get_lctl_scf(struct azx *chip)
 466 {
 467         struct hdac_bus *bus = azx_bus(chip);
 468         static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
 469         u32 val, t;
 470         int i;
 471
 472         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 473
 474         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 475                 t = preferred_bits[i];
 476                 if (val & (1 << t))
 477                         return t;
 478         }
 479
 480         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 481         return 0;
 482 }
 483
 484 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 485 {
 486         struct hdac_bus *bus = azx_bus(chip);
 487         u32 val;
 488         int timeout;
 489
 490         /*
 491          * the codecs are sharing the first link setting by default
 492          * If other links are enabled for stream, they need similar fix
 493          */
 494         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 495         val &= ~AZX_MLCTL_SPA;
 496         val |= state << AZX_MLCTL_SPA_SHIFT;
 497         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 498         /* wait for CPA */
 499         timeout = 50;
 500         while (timeout) {
 501                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 502                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 503                         return 0;
 504                 timeout--;
 505                 udelay(10);
 506         }
 507
 508         return -1;
 509 }
 510
 511 static void intel_init_lctl(struct azx *chip)
 512 {
 513         struct hdac_bus *bus = azx_bus(chip);
 514         u32 val;
 515         int ret;
 516
 517         /* 0. check lctl register value is correct or not */
 518         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 519         /* if SCF is already set, let's use it */
 520         if ((val & ML_LCTL_SCF_MASK) != 0)
 521                 return;
 522
 523         /*
 524          * Before operating on SPA, CPA must match SPA.
 525          * Any deviation may result in undefined behavior.
 526          */
 527         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 528                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 529                 return;
 530
 531         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 532         ret = intel_ml_lctl_set_power(chip, 0);
 533         udelay(100);
 534         if (ret)
 535                 goto set_spa;
 536
 537         /* 2. update SCF to select a properly audio clock*/
 538         val &= ~ML_LCTL_SCF_MASK;
 539         val |= intel_get_lctl_scf(chip);
 540         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 541
 542 set_spa:
 543         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 544         intel_ml_lctl_set_power(chip, 1);
 545         udelay(100);
 546 }
 547
 548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 549 {
 550         struct hdac_bus *bus = azx_bus(chip);
 551         struct pci_dev *pci = chip->pci;
 552         u32 val;
 553
 554         snd_hdac_set_codec_wakeup(bus, true);
 555         if (chip->driver_type == AZX_DRIVER_SKL) {
 556                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 557                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 558                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 559         }
 560         azx_init_chip(chip, full_reset);
 561         if (chip->driver_type == AZX_DRIVER_SKL) {
 562                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 563                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 564                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 565         }
 566
 567         snd_hdac_set_codec_wakeup(bus, false);
 568
 569         /* reduce dma latency to avoid noise */
 570         if (IS_BXT(pci))
 571                 bxt_reduce_dma_latency(chip);
 572
 573         if (bus->mlcap != NULL)
 574                 intel_init_lctl(chip);
 575 }
 576
 577 /* calculate runtime delay from LPIB */
 578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 579                                    unsigned int pos)
 580 {
 581         struct snd_pcm_substream *substream = azx_dev->core.substream;
 582         int stream = substream->stream;
 583         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 584         int delay;
 585
 586         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 587                 delay = pos - lpib_pos;
 588         else
 589                 delay = lpib_pos - pos;
 590         if (delay < 0) {
 591                 if (delay >= azx_dev->core.delay_negative_threshold)
 592                         delay = 0;
 593                 else
 594                         delay += azx_dev->core.bufsize;
 595         }
 596
 597         if (delay >= azx_dev->core.period_bytes) {
 598                 dev_info(chip->card->dev,
 599                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 600                          delay, azx_dev->core.period_bytes);
 601                 delay = 0;
 602                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 603                 chip->get_delay[stream] = NULL;
 604         }
 605
 606         return bytes_to_frames(substream->runtime, delay);
 607 }
 608
 609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 610
 611 /* called from IRQ */
 612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 613 {
 614         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 615         int ok;
 616
 617         ok = azx_position_ok(chip, azx_dev);
 618         if (ok == 1) {
 619                 azx_dev->irq_pending = 0;
 620                 return ok;
 621         } else if (ok == 0) {
 622                 /* bogus IRQ, process it later */
 623                 azx_dev->irq_pending = 1;
 624                 schedule_work(&hda->irq_pending_work);
 625         }
 626         return 0;
 627 }
 628
 629 #define display_power(chip, enable) \
 630         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 631
 632 /*
 633  * Check whether the current DMA position is acceptable for updating
 634  * periods.  Returns non-zero if it's OK.
 635  *
 636  * Many HD-audio controllers appear pretty inaccurate about
 637  * the update-IRQ timing.  The IRQ is issued before actually the
 638  * data is processed.  So, we need to process it afterwords in a
 639  * workqueue.
 640  */
 641 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 642 {
 643         struct snd_pcm_substream *substream = azx_dev->core.substream;
 644         int stream = substream->stream;
 645         u32 wallclk;
 646         unsigned int pos;
 647
 648         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 649         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 650                 return -1;      /* bogus (too early) interrupt */
 651
 652         if (chip->get_position[stream])
 653                 pos = chip->get_position[stream](chip, azx_dev);
 654         else { /* use the position buffer as default */
 655                 pos = azx_get_pos_posbuf(chip, azx_dev);
 656                 if (!pos || pos == (u32)-1) {
 657                         dev_info(chip->card->dev,
 658                                  "Invalid position buffer, using LPIB read method instead.\n");
 659                         chip->get_position[stream] = azx_get_pos_lpib;
 660                         if (chip->get_position[0] == azx_get_pos_lpib &&
 661                             chip->get_position[1] == azx_get_pos_lpib)
 662                                 azx_bus(chip)->use_posbuf = false;
 663                         pos = azx_get_pos_lpib(chip, azx_dev);
 664                         chip->get_delay[stream] = NULL;
 665                 } else {
 666                         chip->get_position[stream] = azx_get_pos_posbuf;
 667                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 668                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 669                 }
 670         }
 671
 672         if (pos >= azx_dev->core.bufsize)
 673                 pos = 0;
 674
 675         if (WARN_ONCE(!azx_dev->core.period_bytes,
 676                       "hda-intel: zero azx_dev->period_bytes"))
 677                 return -1; /* this shouldn't happen! */
 678         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 679             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 680                 /* NG - it's below the first next period boundary */
 681                 return chip->bdl_pos_adj ? 0 : -1;
 682         azx_dev->core.start_wallclk += wallclk;
 683         return 1; /* OK, it's fine */
 684 }
 685
 686 /*
 687  * The work for pending PCM period updates.
 688  */
 689 static void azx_irq_pending_work(struct work_struct *work)
 690 {
 691         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 692         struct azx *chip = &hda->chip;
 693         struct hdac_bus *bus = azx_bus(chip);
 694         struct hdac_stream *s;
 695         int pending, ok;
 696
 697         if (!hda->irq_pending_warned) {
 698                 dev_info(chip->card->dev,
 699                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 700                          chip->card->number);
 701                 hda->irq_pending_warned = 1;
 702         }
 703
 704         for (;;) {
 705                 pending = 0;
 706                 spin_lock_irq(&bus->reg_lock);
 707                 list_for_each_entry(s, &bus->stream_list, list) {
 708                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 709                         if (!azx_dev->irq_pending ||
 710                             !s->substream ||
 711                             !s->running)
 712                                 continue;
 713                         ok = azx_position_ok(chip, azx_dev);
 714                         if (ok > 0) {
 715                                 azx_dev->irq_pending = 0;
 716                                 spin_unlock(&bus->reg_lock);
 717                                 snd_pcm_period_elapsed(s->substream);
 718                                 spin_lock(&bus->reg_lock);
 719                         } else if (ok < 0) {
 720                                 pending = 0;    /* too early */
 721                         } else
 722                                 pending++;
 723                 }
 724                 spin_unlock_irq(&bus->reg_lock);
 725                 if (!pending)
 726                         return;
 727                 msleep(1);
 728         }
 729 }
 730
 731 /* clear irq_pending flags and assure no on-going workq */
 732 static void azx_clear_irq_pending(struct azx *chip)
 733 {
 734         struct hdac_bus *bus = azx_bus(chip);
 735         struct hdac_stream *s;
 736
 737         spin_lock_irq(&bus->reg_lock);
 738         list_for_each_entry(s, &bus->stream_list, list) {
 739                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 740                 azx_dev->irq_pending = 0;
 741         }
 742         spin_unlock_irq(&bus->reg_lock);
 743 }
 744
 745 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 746 {
 747         struct hdac_bus *bus = azx_bus(chip);
 748
 749         if (request_irq(chip->pci->irq, azx_interrupt,
 750                         chip->msi ? 0 : IRQF_SHARED,
 751                         chip->card->irq_descr, chip)) {
 752                 dev_err(chip->card->dev,
 753                         "unable to grab IRQ %d, disabling device\n",
 754                         chip->pci->irq);
 755                 if (do_disconnect)
 756                         snd_card_disconnect(chip->card);
 757                 return -1;
 758         }
 759         bus->irq = chip->pci->irq;
 760         chip->card->sync_irq = bus->irq;
 761         pci_intx(chip->pci, !chip->msi);
 762         return 0;
 763 }
 764
 765 /* get the current DMA position with correction on VIA chips */
 766 static unsigned int azx_via_get_position(struct azx *chip,
 767                                          struct azx_dev *azx_dev)
 768 {
 769         unsigned int link_pos, mini_pos, bound_pos;
 770         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 771         unsigned int fifo_size;
 772
 773         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 774         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 775                 /* Playback, no problem using link position */
 776                 return link_pos;
 777         }
 778
 779         /* Capture */
 780         /* For new chipset,
 781          * use mod to get the DMA position just like old chipset
 782          */
 783         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 784         mod_dma_pos %= azx_dev->core.period_bytes;
 785
 786         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 787
 788         if (azx_dev->insufficient) {
 789                 /* Link position never gather than FIFO size */
 790                 if (link_pos <= fifo_size)
 791                         return 0;
 792
 793                 azx_dev->insufficient = 0;
 794         }
 795
 796         if (link_pos <= fifo_size)
 797                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 798         else
 799                 mini_pos = link_pos - fifo_size;
 800
 801         /* Find nearest previous boudary */
 802         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 803         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 804         if (mod_link_pos >= fifo_size)
 805                 bound_pos = link_pos - mod_link_pos;
 806         else if (mod_dma_pos >= mod_mini_pos)
 807                 bound_pos = mini_pos - mod_mini_pos;
 808         else {
 809                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 810                 if (bound_pos >= azx_dev->core.bufsize)
 811                         bound_pos = 0;
 812         }
 813
 814         /* Calculate real DMA position we want */
 815         return bound_pos + mod_dma_pos;
 816 }
 817
 818 #define AMD_FIFO_SIZE   32
 819
 820 /* get the current DMA position with FIFO size correction */
 821 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 822 {
 823         struct snd_pcm_substream *substream = azx_dev->core.substream;
 824         struct snd_pcm_runtime *runtime = substream->runtime;
 825         unsigned int pos, delay;
 826
 827         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 828         if (!runtime)
 829                 return pos;
 830
 831         runtime->delay = AMD_FIFO_SIZE;
 832         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 833         if (azx_dev->insufficient) {
 834                 if (pos < delay) {
 835                         delay = pos;
 836                         runtime->delay = bytes_to_frames(runtime, pos);
 837                 } else {
 838                         azx_dev->insufficient = 0;
 839                 }
 840         }
 841
 842         /* correct the DMA position for capture stream */
 843         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 844                 if (pos < delay)
 845                         pos += azx_dev->core.bufsize;
 846                 pos -= delay;
 847         }
 848
 849         return pos;
 850 }
 851
 852 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 853                                    unsigned int pos)
 854 {
 855         struct snd_pcm_substream *substream = azx_dev->core.substream;
 856
 857         /* just read back the calculated value in the above */
 858         return substream->runtime->delay;
 859 }
 860
 861 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 862                                          struct azx_dev *azx_dev)
 863 {
 864         return _snd_hdac_chip_readl(azx_bus(chip),
 865                                     AZX_REG_VS_SDXDPIB_XBASE +
 866                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 867                                      azx_dev->core.index));
 868 }
 869
 870 /* get the current DMA position with correction on SKL+ chips */
 871 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 872 {
 873         /* DPIB register gives a more accurate position for playback */
 874         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 875                 return azx_skl_get_dpib_pos(chip, azx_dev);
 876
 877         /* For capture, we need to read posbuf, but it requires a delay
 878          * for the possible boundary overlap; the read of DPIB fetches the
 879          * actual posbuf
 880          */
 881         udelay(20);
 882         azx_skl_get_dpib_pos(chip, azx_dev);
 883         return azx_get_pos_posbuf(chip, azx_dev);
 884 }
 885
 886 #ifdef CONFIG_PM
 887 static DEFINE_MUTEX(card_list_lock);
 888 static LIST_HEAD(card_list);
 889
 890 static void azx_add_card_list(struct azx *chip)
 891 {
 892         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 893         mutex_lock(&card_list_lock);
 894         list_add(&hda->list, &card_list);
 895         mutex_unlock(&card_list_lock);
 896 }
 897
 898 static void azx_del_card_list(struct azx *chip)
 899 {
 900         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 901         mutex_lock(&card_list_lock);
 902         list_del_init(&hda->list);
 903         mutex_unlock(&card_list_lock);
 904 }
 905
 906 /* trigger power-save check at writing parameter */
 907 static int param_set_xint(const char *val, const struct kernel_param *kp)
 908 {
 909         struct hda_intel *hda;
 910         struct azx *chip;
 911         int prev = power_save;
 912         int ret = param_set_int(val, kp);
 913
 914         if (ret || prev == power_save)
 915                 return ret;
 916
 917         mutex_lock(&card_list_lock);
 918         list_for_each_entry(hda, &card_list, list) {
 919                 chip = &hda->chip;
 920                 if (!hda->probe_continued || chip->disabled)
 921                         continue;
 922                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 923         }
 924         mutex_unlock(&card_list_lock);
 925         return 0;
 926 }
 927
 928 /*
 929  * power management
 930  */
 931 static bool azx_is_pm_ready(struct snd_card *card)
 932 {
 933         struct azx *chip;
 934         struct hda_intel *hda;
 935
 936         if (!card)
 937                 return false;
 938         chip = card->private_data;
 939         hda = container_of(chip, struct hda_intel, chip);
 940         if (chip->disabled || hda->init_failed || !chip->running)
 941                 return false;
 942         return true;
 943 }
 944
 945 static void __azx_runtime_suspend(struct azx *chip)
 946 {
 947         azx_stop_chip(chip);
 948         azx_enter_link_reset(chip);
 949         azx_clear_irq_pending(chip);
 950         display_power(chip, false);
 951 }
 952
 953 static void __azx_runtime_resume(struct azx *chip)
 954 {
 955         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 956         struct hdac_bus *bus = azx_bus(chip);
 957         struct hda_codec *codec;
 958         int status;
 959
 960         display_power(chip, true);
 961         if (hda->need_i915_power)
 962                 snd_hdac_i915_set_bclk(bus);
 963
 964         /* Read STATESTS before controller reset */
 965         status = azx_readw(chip, STATESTS);
 966
 967         azx_init_pci(chip);
 968         hda_intel_init_chip(chip, true);
 969
 970         /* Avoid codec resume if runtime resume is for system suspend */
 971         if (!chip->pm_prepared) {
 972                 list_for_each_codec(codec, &chip->bus) {
 973                         if (codec->relaxed_resume)
 974                                 continue;
 975
 976                         if (codec->forced_resume || (status & (1 << codec->addr)))
 977                                 pm_request_resume(hda_codec_dev(codec));
 978                 }
 979         }
 980
 981         /* power down again for link-controlled chips */
 982         if (!hda->need_i915_power)
 983                 display_power(chip, false);
 984 }
 985
 986 #ifdef CONFIG_PM_SLEEP
 987 static int azx_prepare(struct device *dev)
 988 {
 989         struct snd_card *card = dev_get_drvdata(dev);
 990         struct azx *chip;
 991
 992         chip = card->private_data;
 993         chip->pm_prepared = 1;
 994
 995         flush_work(&azx_bus(chip)->unsol_work);
 996
 997         /* HDA controller always requires different WAKEEN for runtime suspend
 998          * and system suspend, so don't use direct-complete here.
 999          */
1000         return 0;
1001 }
1002
1003 static void azx_complete(struct device *dev)
1004 {
1005         struct snd_card *card = dev_get_drvdata(dev);
1006         struct azx *chip;
1007
1008         chip = card->private_data;
1009         chip->pm_prepared = 0;
1010 }
1011
1012 static int azx_suspend(struct device *dev)
1013 {
1014         struct snd_card *card = dev_get_drvdata(dev);
1015         struct azx *chip;
1016         struct hdac_bus *bus;
1017
1018         if (!azx_is_pm_ready(card))
1019                 return 0;
1020
1021         chip = card->private_data;
1022         bus = azx_bus(chip);
1023         __azx_runtime_suspend(chip);
1024         if (bus->irq >= 0) {
1025                 free_irq(bus->irq, chip);
1026                 bus->irq = -1;
1027                 chip->card->sync_irq = -1;
1028         }
1029
1030         if (chip->msi)
1031                 pci_disable_msi(chip->pci);
1032
1033         trace_azx_suspend(chip);
1034         return 0;
1035 }
1036
1037 static int azx_resume(struct device *dev)
1038 {
1039         struct snd_card *card = dev_get_drvdata(dev);
1040         struct azx *chip;
1041
1042         if (!azx_is_pm_ready(card))
1043                 return 0;
1044
1045         chip = card->private_data;
1046         if (chip->msi)
1047                 if (pci_enable_msi(chip->pci) < 0)
1048                         chip->msi = 0;
1049         if (azx_acquire_irq(chip, 1) < 0)
1050                 return -EIO;
1051
1052         __azx_runtime_resume(chip);
1053
1054         trace_azx_resume(chip);
1055         return 0;
1056 }
1057
1058 /* put codec down to D3 at hibernation for Intel SKL+;
1059  * otherwise BIOS may still access the codec and screw up the driver
1060  */
1061 static int azx_freeze_noirq(struct device *dev)
1062 {
1063         struct snd_card *card = dev_get_drvdata(dev);
1064         struct azx *chip = card->private_data;
1065         struct pci_dev *pci = to_pci_dev(dev);
1066
1067         if (!azx_is_pm_ready(card))
1068                 return 0;
1069         if (chip->driver_type == AZX_DRIVER_SKL)
1070                 pci_set_power_state(pci, PCI_D3hot);
1071
1072         return 0;
1073 }
1074
1075 static int azx_thaw_noirq(struct device *dev)
1076 {
1077         struct snd_card *card = dev_get_drvdata(dev);
1078         struct azx *chip = card->private_data;
1079         struct pci_dev *pci = to_pci_dev(dev);
1080
1081         if (!azx_is_pm_ready(card))
1082                 return 0;
1083         if (chip->driver_type == AZX_DRIVER_SKL)
1084                 pci_set_power_state(pci, PCI_D0);
1085
1086         return 0;
1087 }
1088 #endif /* CONFIG_PM_SLEEP */
1089
1090 static int azx_runtime_suspend(struct device *dev)
1091 {
1092         struct snd_card *card = dev_get_drvdata(dev);
1093         struct azx *chip;
1094
1095         if (!azx_is_pm_ready(card))
1096                 return 0;
1097         chip = card->private_data;
1098
1099         /* enable controller wake up event */
1100         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1101
1102         __azx_runtime_suspend(chip);
1103         trace_azx_runtime_suspend(chip);
1104         return 0;
1105 }
1106
1107 static int azx_runtime_resume(struct device *dev)
1108 {
1109         struct snd_card *card = dev_get_drvdata(dev);
1110         struct azx *chip;
1111
1112         if (!azx_is_pm_ready(card))
1113                 return 0;
1114         chip = card->private_data;
1115         __azx_runtime_resume(chip);
1116
1117         /* disable controller Wake Up event*/
1118         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1119
1120         trace_azx_runtime_resume(chip);
1121         return 0;
1122 }
1123
1124 static int azx_runtime_idle(struct device *dev)
1125 {
1126         struct snd_card *card = dev_get_drvdata(dev);
1127         struct azx *chip;
1128         struct hda_intel *hda;
1129
1130         if (!card)
1131                 return 0;
1132
1133         chip = card->private_data;
1134         hda = container_of(chip, struct hda_intel, chip);
1135         if (chip->disabled || hda->init_failed)
1136                 return 0;
1137
1138         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1139             azx_bus(chip)->codec_powered || !chip->running)
1140                 return -EBUSY;
1141
1142         /* ELD notification gets broken when HD-audio bus is off */
1143         if (needs_eld_notify_link(chip))
1144                 return -EBUSY;
1145
1146         return 0;
1147 }
1148
1149 static const struct dev_pm_ops azx_pm = {
1150         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1151 #ifdef CONFIG_PM_SLEEP
1152         .prepare = azx_prepare,
1153         .complete = azx_complete,
1154         .freeze_noirq = azx_freeze_noirq,
1155         .thaw_noirq = azx_thaw_noirq,
1156 #endif
1157         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1158 };
1159
1160 #define AZX_PM_OPS      &azx_pm
1161 #else
1162 #define azx_add_card_list(chip) /* NOP */
1163 #define azx_del_card_list(chip) /* NOP */
1164 #define AZX_PM_OPS      NULL
1165 #endif /* CONFIG_PM */
1166
1167
1168 static int azx_probe_continue(struct azx *chip);
1169
1170 #ifdef SUPPORT_VGA_SWITCHEROO
1171 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1172
1173 static void azx_vs_set_state(struct pci_dev *pci,
1174                              enum vga_switcheroo_state state)
1175 {
1176         struct snd_card *card = pci_get_drvdata(pci);
1177         struct azx *chip = card->private_data;
1178         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1179         struct hda_codec *codec;
1180         bool disabled;
1181
1182         wait_for_completion(&hda->probe_wait);
1183         if (hda->init_failed)
1184                 return;
1185
1186         disabled = (state == VGA_SWITCHEROO_OFF);
1187         if (chip->disabled == disabled)
1188                 return;
1189
1190         if (!hda->probe_continued) {
1191                 chip->disabled = disabled;
1192                 if (!disabled) {
1193                         dev_info(chip->card->dev,
1194                                  "Start delayed initialization\n");
1195                         if (azx_probe_continue(chip) < 0)
1196                                 dev_err(chip->card->dev, "initialization error\n");
1197                 }
1198         } else {
1199                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1200                          disabled ? "Disabling" : "Enabling");
1201                 if (disabled) {
1202                         list_for_each_codec(codec, &chip->bus) {
1203                                 pm_runtime_suspend(hda_codec_dev(codec));
1204                                 pm_runtime_disable(hda_codec_dev(codec));
1205                         }
1206                         pm_runtime_suspend(card->dev);
1207                         pm_runtime_disable(card->dev);
1208                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1209                          * however we have no ACPI handle, so pci/acpi can't put us there,
1210                          * put ourselves there */
1211                         pci->current_state = PCI_D3cold;
1212                         chip->disabled = true;
1213                         if (snd_hda_lock_devices(&chip->bus))
1214                                 dev_warn(chip->card->dev,
1215                                          "Cannot lock devices!\n");
1216                 } else {
1217                         snd_hda_unlock_devices(&chip->bus);
1218                         chip->disabled = false;
1219                         pm_runtime_enable(card->dev);
1220                         list_for_each_codec(codec, &chip->bus) {
1221                                 pm_runtime_enable(hda_codec_dev(codec));
1222                                 pm_runtime_resume(hda_codec_dev(codec));
1223                         }
1224                 }
1225         }
1226 }
1227
1228 static bool azx_vs_can_switch(struct pci_dev *pci)
1229 {
1230         struct snd_card *card = pci_get_drvdata(pci);
1231         struct azx *chip = card->private_data;
1232         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1233
1234         wait_for_completion(&hda->probe_wait);
1235         if (hda->init_failed)
1236                 return false;
1237         if (chip->disabled || !hda->probe_continued)
1238                 return true;
1239         if (snd_hda_lock_devices(&chip->bus))
1240                 return false;
1241         snd_hda_unlock_devices(&chip->bus);
1242         return true;
1243 }
1244
1245 /*
1246  * The discrete GPU cannot power down unless the HDA controller runtime
1247  * suspends, so activate runtime PM on codecs even if power_save == 0.
1248  */
1249 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1250 {
1251         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1252         struct hda_codec *codec;
1253
1254         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1255                 list_for_each_codec(codec, &chip->bus)
1256                         codec->auto_runtime_pm = 1;
1257                 /* reset the power save setup */
1258                 if (chip->running)
1259                         set_default_power_save(chip);
1260         }
1261 }
1262
1263 static void azx_vs_gpu_bound(struct pci_dev *pci,
1264                              enum vga_switcheroo_client_id client_id)
1265 {
1266         struct snd_card *card = pci_get_drvdata(pci);
1267         struct azx *chip = card->private_data;
1268
1269         if (client_id == VGA_SWITCHEROO_DIS)
1270                 chip->bus.keep_power = 0;
1271         setup_vga_switcheroo_runtime_pm(chip);
1272 }
1273
1274 static void init_vga_switcheroo(struct azx *chip)
1275 {
1276         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1277         struct pci_dev *p = get_bound_vga(chip->pci);
1278         struct pci_dev *parent;
1279         if (p) {
1280                 dev_info(chip->card->dev,
1281                          "Handle vga_switcheroo audio client\n");
1282                 hda->use_vga_switcheroo = 1;
1283
1284                 /* cleared in either gpu_bound op or codec probe, or when its
1285                  * upstream port has _PR3 (i.e. dGPU).
1286                  */
1287                 parent = pci_upstream_bridge(p);
1288                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1289                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1290                 pci_dev_put(p);
1291         }
1292 }
1293
1294 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1295         .set_gpu_state = azx_vs_set_state,
1296         .can_switch = azx_vs_can_switch,
1297         .gpu_bound = azx_vs_gpu_bound,
1298 };
1299
1300 static int register_vga_switcheroo(struct azx *chip)
1301 {
1302         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1303         struct pci_dev *p;
1304         int err;
1305
1306         if (!hda->use_vga_switcheroo)
1307                 return 0;
1308
1309         p = get_bound_vga(chip->pci);
1310         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1311         pci_dev_put(p);
1312
1313         if (err < 0)
1314                 return err;
1315         hda->vga_switcheroo_registered = 1;
1316
1317         return 0;
1318 }
1319 #else
1320 #define init_vga_switcheroo(chip)               /* NOP */
1321 #define register_vga_switcheroo(chip)           0
1322 #define check_hdmi_disabled(pci)        false
1323 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1324 #endif /* SUPPORT_VGA_SWITCHER */
1325
1326 /*
1327  * destructor
1328  */
1329 static void azx_free(struct azx *chip)
1330 {
1331         struct pci_dev *pci = chip->pci;
1332         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1333         struct hdac_bus *bus = azx_bus(chip);
1334
1335         if (hda->freed)
1336                 return;
1337
1338         if (azx_has_pm_runtime(chip) && chip->running)
1339                 pm_runtime_get_noresume(&pci->dev);
1340         chip->running = 0;
1341
1342         azx_del_card_list(chip);
1343
1344         hda->init_failed = 1; /* to be sure */
1345         complete_all(&hda->probe_wait);
1346
1347         if (use_vga_switcheroo(hda)) {
1348                 if (chip->disabled && hda->probe_continued)
1349                         snd_hda_unlock_devices(&chip->bus);
1350                 if (hda->vga_switcheroo_registered)
1351                         vga_switcheroo_unregister_client(chip->pci);
1352         }
1353
1354         if (bus->chip_init) {
1355                 azx_clear_irq_pending(chip);
1356                 azx_stop_all_streams(chip);
1357                 azx_stop_chip(chip);
1358         }
1359
1360         if (bus->irq >= 0)
1361                 free_irq(bus->irq, (void*)chip);
1362         if (chip->msi)
1363                 pci_disable_msi(chip->pci);
1364         iounmap(bus->remap_addr);
1365
1366         azx_free_stream_pages(chip);
1367         azx_free_streams(chip);
1368         snd_hdac_bus_exit(bus);
1369
1370         if (chip->region_requested)
1371                 pci_release_regions(chip->pci);
1372
1373         pci_disable_device(chip->pci);
1374 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1375         release_firmware(chip->fw);
1376 #endif
1377         display_power(chip, false);
1378
1379         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1380                 snd_hdac_i915_exit(bus);
1381
1382         hda->freed = 1;
1383 }
1384
1385 static int azx_dev_disconnect(struct snd_device *device)
1386 {
1387         struct azx *chip = device->device_data;
1388         struct hdac_bus *bus = azx_bus(chip);
1389
1390         chip->bus.shutdown = 1;
1391         cancel_work_sync(&bus->unsol_work);
1392
1393         return 0;
1394 }
1395
1396 static int azx_dev_free(struct snd_device *device)
1397 {
1398         azx_free(device->device_data);
1399         return 0;
1400 }
1401
1402 #ifdef SUPPORT_VGA_SWITCHEROO
1403 #ifdef CONFIG_ACPI
1404 /* ATPX is in the integrated GPU's namespace */
1405 static bool atpx_present(void)
1406 {
1407         struct pci_dev *pdev = NULL;
1408         acpi_handle dhandle, atpx_handle;
1409         acpi_status status;
1410
1411         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1412                 dhandle = ACPI_HANDLE(&pdev->dev);
1413                 if (dhandle) {
1414                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1415                         if (ACPI_SUCCESS(status)) {
1416                                 pci_dev_put(pdev);
1417                                 return true;
1418                         }
1419                 }
1420         }
1421         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1422                 dhandle = ACPI_HANDLE(&pdev->dev);
1423                 if (dhandle) {
1424                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1425                         if (ACPI_SUCCESS(status)) {
1426                                 pci_dev_put(pdev);
1427                                 return true;
1428                         }
1429                 }
1430         }
1431         return false;
1432 }
1433 #else
1434 static bool atpx_present(void)
1435 {
1436         return false;
1437 }
1438 #endif
1439
1440 /*
1441  * Check of disabled HDMI controller by vga_switcheroo
1442  */
1443 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1444 {
1445         struct pci_dev *p;
1446
1447         /* check only discrete GPU */
1448         switch (pci->vendor) {
1449         case PCI_VENDOR_ID_ATI:
1450         case PCI_VENDOR_ID_AMD:
1451                 if (pci->devfn == 1) {
1452                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1453                                                         pci->bus->number, 0);
1454                         if (p) {
1455                                 /* ATPX is in the integrated GPU's ACPI namespace
1456                                  * rather than the dGPU's namespace. However,
1457                                  * the dGPU is the one who is involved in
1458                                  * vgaswitcheroo.
1459                                  */
1460                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1461                                     atpx_present())
1462                                         return p;
1463                                 pci_dev_put(p);
1464                         }
1465                 }
1466                 break;
1467         case PCI_VENDOR_ID_NVIDIA:
1468                 if (pci->devfn == 1) {
1469                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1470                                                         pci->bus->number, 0);
1471                         if (p) {
1472                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1473                                         return p;
1474                                 pci_dev_put(p);
1475                         }
1476                 }
1477                 break;
1478         }
1479         return NULL;
1480 }
1481
1482 static bool check_hdmi_disabled(struct pci_dev *pci)
1483 {
1484         bool vga_inactive = false;
1485         struct pci_dev *p = get_bound_vga(pci);
1486
1487         if (p) {
1488                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1489                         vga_inactive = true;
1490                 pci_dev_put(p);
1491         }
1492         return vga_inactive;
1493 }
1494 #endif /* SUPPORT_VGA_SWITCHEROO */
1495
1496 /*
1497  * allow/deny-listing for position_fix
1498  */
1499 static const struct snd_pci_quirk position_fix_list[] = {
1500         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1501         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1502         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1503         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1504         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1505         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1506         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1507         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1508         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1509         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1510         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1511         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1512         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1513         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1514         {}
1515 };
1516
1517 static int check_position_fix(struct azx *chip, int fix)
1518 {
1519         const struct snd_pci_quirk *q;
1520
1521         switch (fix) {
1522         case POS_FIX_AUTO:
1523         case POS_FIX_LPIB:
1524         case POS_FIX_POSBUF:
1525         case POS_FIX_VIACOMBO:
1526         case POS_FIX_COMBO:
1527         case POS_FIX_SKL:
1528         case POS_FIX_FIFO:
1529                 return fix;
1530         }
1531
1532         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1533         if (q) {
1534                 dev_info(chip->card->dev,
1535                          "position_fix set to %d for device %04x:%04x\n",
1536                          q->value, q->subvendor, q->subdevice);
1537                 return q->value;
1538         }
1539
1540         /* Check VIA/ATI HD Audio Controller exist */
1541         if (chip->driver_type == AZX_DRIVER_VIA) {
1542                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1543                 return POS_FIX_VIACOMBO;
1544         }
1545         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1546                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1547                 return POS_FIX_FIFO;
1548         }
1549         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1550                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1551                 return POS_FIX_LPIB;
1552         }
1553         if (chip->driver_type == AZX_DRIVER_SKL) {
1554                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1555                 return POS_FIX_SKL;
1556         }
1557         return POS_FIX_AUTO;
1558 }
1559
1560 static void assign_position_fix(struct azx *chip, int fix)
1561 {
1562         static const azx_get_pos_callback_t callbacks[] = {
1563                 [POS_FIX_AUTO] = NULL,
1564                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1565                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1566                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1567                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1568                 [POS_FIX_SKL] = azx_get_pos_skl,
1569                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1570         };
1571
1572         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1573
1574         /* combo mode uses LPIB only for playback */
1575         if (fix == POS_FIX_COMBO)
1576                 chip->get_position[1] = NULL;
1577
1578         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1579             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1580                 chip->get_delay[0] = chip->get_delay[1] =
1581                         azx_get_delay_from_lpib;
1582         }
1583
1584         if (fix == POS_FIX_FIFO)
1585                 chip->get_delay[0] = chip->get_delay[1] =
1586                         azx_get_delay_from_fifo;
1587 }
1588
1589 /*
1590  * deny-lists for probe_mask
1591  */
1592 static const struct snd_pci_quirk probe_mask_list[] = {
1593         /* Thinkpad often breaks the controller communication when accessing
1594          * to the non-working (or non-existing) modem codec slot.
1595          */
1596         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1597         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1598         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1599         /* broken BIOS */
1600         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1601         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1602         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1603         /* forced codec slots */
1604         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1605         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1606         /* WinFast VP200 H (Teradici) user reported broken communication */
1607         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1608         {}
1609 };
1610
1611 #define AZX_FORCE_CODEC_MASK    0x100
1612
1613 static void check_probe_mask(struct azx *chip, int dev)
1614 {
1615         const struct snd_pci_quirk *q;
1616
1617         chip->codec_probe_mask = probe_mask[dev];
1618         if (chip->codec_probe_mask == -1) {
1619                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1620                 if (q) {
1621                         dev_info(chip->card->dev,
1622                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1623                                  q->value, q->subvendor, q->subdevice);
1624                         chip->codec_probe_mask = q->value;
1625                 }
1626         }
1627
1628         /* check forced option */
1629         if (chip->codec_probe_mask != -1 &&
1630             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1631                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1632                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1633                          (int)azx_bus(chip)->codec_mask);
1634         }
1635 }
1636
1637 /*
1638  * allow/deny-list for enable_msi
1639  */
1640 static const struct snd_pci_quirk msi_deny_list[] = {
1641         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1642         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1643         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1644         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1645         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1646         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1647         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1648         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1649         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1650         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1651         {}
1652 };
1653
1654 static void check_msi(struct azx *chip)
1655 {
1656         const struct snd_pci_quirk *q;
1657
1658         if (enable_msi >= 0) {
1659                 chip->msi = !!enable_msi;
1660                 return;
1661         }
1662         chip->msi = 1;  /* enable MSI as default */
1663         q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1664         if (q) {
1665                 dev_info(chip->card->dev,
1666                          "msi for device %04x:%04x set to %d\n",
1667                          q->subvendor, q->subdevice, q->value);
1668                 chip->msi = q->value;
1669                 return;
1670         }
1671
1672         /* NVidia chipsets seem to cause troubles with MSI */
1673         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1674                 dev_info(chip->card->dev, "Disabling MSI\n");
1675                 chip->msi = 0;
1676         }
1677 }
1678
1679 /* check the snoop mode availability */
1680 static void azx_check_snoop_available(struct azx *chip)
1681 {
1682         int snoop = hda_snoop;
1683
1684         if (snoop >= 0) {
1685                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1686                          snoop ? "snoop" : "non-snoop");
1687                 chip->snoop = snoop;
1688                 chip->uc_buffer = !snoop;
1689                 return;
1690         }
1691
1692         snoop = true;
1693         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1694             chip->driver_type == AZX_DRIVER_VIA) {
1695                 /* force to non-snoop mode for a new VIA controller
1696                  * when BIOS is set
1697                  */
1698                 u8 val;
1699                 pci_read_config_byte(chip->pci, 0x42, &val);
1700                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1701                                       chip->pci->revision == 0x20))
1702                         snoop = false;
1703         }
1704
1705         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1706                 snoop = false;
1707
1708         chip->snoop = snoop;
1709         if (!snoop) {
1710                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1711                 /* C-Media requires non-cached pages only for CORB/RIRB */
1712                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1713                         chip->uc_buffer = true;
1714         }
1715 }
1716
1717 static void azx_probe_work(struct work_struct *work)
1718 {
1719         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1720         azx_probe_continue(&hda->chip);
1721 }
1722
1723 static int default_bdl_pos_adj(struct azx *chip)
1724 {
1725         /* some exceptions: Atoms seem problematic with value 1 */
1726         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1727                 switch (chip->pci->device) {
1728                 case 0x0f04: /* Baytrail */
1729                 case 0x2284: /* Braswell */
1730                         return 32;
1731                 }
1732         }
1733
1734         switch (chip->driver_type) {
1735         case AZX_DRIVER_ICH:
1736         case AZX_DRIVER_PCH:
1737                 return 1;
1738         default:
1739                 return 32;
1740         }
1741 }
1742
1743 /*
1744  * constructor
1745  */
1746 static const struct hda_controller_ops pci_hda_ops;
1747
1748 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1749                       int dev, unsigned int driver_caps,
1750                       struct azx **rchip)
1751 {
1752         static const struct snd_device_ops ops = {
1753                 .dev_disconnect = azx_dev_disconnect,
1754                 .dev_free = azx_dev_free,
1755         };
1756         struct hda_intel *hda;
1757         struct azx *chip;
1758         int err;
1759
1760         *rchip = NULL;
1761
1762         err = pci_enable_device(pci);
1763         if (err < 0)
1764                 return err;
1765
1766         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1767         if (!hda) {
1768                 pci_disable_device(pci);
1769                 return -ENOMEM;
1770         }
1771
1772         chip = &hda->chip;
1773         mutex_init(&chip->open_mutex);
1774         chip->card = card;
1775         chip->pci = pci;
1776         chip->ops = &pci_hda_ops;
1777         chip->driver_caps = driver_caps;
1778         chip->driver_type = driver_caps & 0xff;
1779         check_msi(chip);
1780         chip->dev_index = dev;
1781         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1782                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1783         INIT_LIST_HEAD(&chip->pcm_list);
1784         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1785         INIT_LIST_HEAD(&hda->list);
1786         init_vga_switcheroo(chip);
1787         init_completion(&hda->probe_wait);
1788
1789         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1790
1791         check_probe_mask(chip, dev);
1792
1793         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1794                 chip->fallback_to_single_cmd = 1;
1795         else /* explicitly set to single_cmd or not */
1796                 chip->single_cmd = single_cmd;
1797
1798         azx_check_snoop_available(chip);
1799
1800         if (bdl_pos_adj[dev] < 0)
1801                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1802         else
1803                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1804
1805         err = azx_bus_init(chip, model[dev]);
1806         if (err < 0) {
1807                 pci_disable_device(pci);
1808                 return err;
1809         }
1810
1811         /* use the non-cached pages in non-snoop mode */
1812         if (!azx_snoop(chip))
1813                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1814
1815         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1816                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1817                 chip->bus.core.needs_damn_long_delay = 1;
1818         }
1819
1820         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1821         if (err < 0) {
1822                 dev_err(card->dev, "Error creating device [card]!\n");
1823                 azx_free(chip);
1824                 return err;
1825         }
1826
1827         /* continue probing in work context as may trigger request module */
1828         INIT_WORK(&hda->probe_work, azx_probe_work);
1829
1830         *rchip = chip;
1831
1832         return 0;
1833 }
1834
1835 static int azx_first_init(struct azx *chip)
1836 {
1837         int dev = chip->dev_index;
1838         struct pci_dev *pci = chip->pci;
1839         struct snd_card *card = chip->card;
1840         struct hdac_bus *bus = azx_bus(chip);
1841         int err;
1842         unsigned short gcap;
1843         unsigned int dma_bits = 64;
1844
1845 #if BITS_PER_LONG != 64
1846         /* Fix up base address on ULI M5461 */
1847         if (chip->driver_type == AZX_DRIVER_ULI) {
1848                 u16 tmp3;
1849                 pci_read_config_word(pci, 0x40, &tmp3);
1850                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1851                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1852         }
1853 #endif
1854
1855         err = pci_request_regions(pci, "ICH HD audio");
1856         if (err < 0)
1857                 return err;
1858         chip->region_requested = 1;
1859
1860         bus->addr = pci_resource_start(pci, 0);
1861         bus->remap_addr = pci_ioremap_bar(pci, 0);
1862         if (bus->remap_addr == NULL) {
1863                 dev_err(card->dev, "ioremap error\n");
1864                 return -ENXIO;
1865         }
1866
1867         if (chip->driver_type == AZX_DRIVER_SKL)
1868                 snd_hdac_bus_parse_capabilities(bus);
1869
1870         /*
1871          * Some Intel CPUs has always running timer (ART) feature and
1872          * controller may have Global time sync reporting capability, so
1873          * check both of these before declaring synchronized time reporting
1874          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1875          */
1876         chip->gts_present = false;
1877
1878 #ifdef CONFIG_X86
1879         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1880                 chip->gts_present = true;
1881 #endif
1882
1883         if (chip->msi) {
1884                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1885                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1886                         pci->no_64bit_msi = true;
1887                 }
1888                 if (pci_enable_msi(pci) < 0)
1889                         chip->msi = 0;
1890         }
1891
1892         pci_set_master(pci);
1893
1894         gcap = azx_readw(chip, GCAP);
1895         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1896
1897         /* AMD devices support 40 or 48bit DMA, take the safe one */
1898         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1899                 dma_bits = 40;
1900
1901         /* disable SB600 64bit support for safety */
1902         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1903                 struct pci_dev *p_smbus;
1904                 dma_bits = 40;
1905                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1906                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1907                                          NULL);
1908                 if (p_smbus) {
1909                         if (p_smbus->revision < 0x30)
1910                                 gcap &= ~AZX_GCAP_64OK;
1911                         pci_dev_put(p_smbus);
1912                 }
1913         }
1914
1915         /* NVidia hardware normally only supports up to 40 bits of DMA */
1916         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1917                 dma_bits = 40;
1918
1919         /* disable 64bit DMA address on some devices */
1920         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1921                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1922                 gcap &= ~AZX_GCAP_64OK;
1923         }
1924
1925         /* disable buffer size rounding to 128-byte multiples if supported */
1926         if (align_buffer_size >= 0)
1927                 chip->align_buffer_size = !!align_buffer_size;
1928         else {
1929                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1930                         chip->align_buffer_size = 0;
1931                 else
1932                         chip->align_buffer_size = 1;
1933         }
1934
1935         /* allow 64bit DMA address if supported by H/W */
1936         if (!(gcap & AZX_GCAP_64OK))
1937                 dma_bits = 32;
1938         if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1939                 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1940
1941         /* read number of streams from GCAP register instead of using
1942          * hardcoded value
1943          */
1944         chip->capture_streams = (gcap >> 8) & 0x0f;
1945         chip->playback_streams = (gcap >> 12) & 0x0f;
1946         if (!chip->playback_streams && !chip->capture_streams) {
1947                 /* gcap didn't give any info, switching to old method */
1948
1949                 switch (chip->driver_type) {
1950                 case AZX_DRIVER_ULI:
1951                         chip->playback_streams = ULI_NUM_PLAYBACK;
1952                         chip->capture_streams = ULI_NUM_CAPTURE;
1953                         break;
1954                 case AZX_DRIVER_ATIHDMI:
1955                 case AZX_DRIVER_ATIHDMI_NS:
1956                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1957                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1958                         break;
1959                 case AZX_DRIVER_GENERIC:
1960                 default:
1961                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1962                         chip->capture_streams = ICH6_NUM_CAPTURE;
1963                         break;
1964                 }
1965         }
1966         chip->capture_index_offset = 0;
1967         chip->playback_index_offset = chip->capture_streams;
1968         chip->num_streams = chip->playback_streams + chip->capture_streams;
1969
1970         /* sanity check for the SDxCTL.STRM field overflow */
1971         if (chip->num_streams > 15 &&
1972             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1973                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1974                          "forcing separate stream tags", chip->num_streams);
1975                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1976         }
1977
1978         /* initialize streams */
1979         err = azx_init_streams(chip);
1980         if (err < 0)
1981                 return err;
1982
1983         err = azx_alloc_stream_pages(chip);
1984         if (err < 0)
1985                 return err;
1986
1987         /* initialize chip */
1988         azx_init_pci(chip);
1989
1990         snd_hdac_i915_set_bclk(bus);
1991
1992         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1993
1994         /* codec detection */
1995         if (!azx_bus(chip)->codec_mask) {
1996                 dev_err(card->dev, "no codecs found!\n");
1997                 /* keep running the rest for the runtime PM */
1998         }
1999
2000         if (azx_acquire_irq(chip, 0) < 0)
2001                 return -EBUSY;
2002
2003         strcpy(card->driver, "HDA-Intel");
2004         strscpy(card->shortname, driver_short_names[chip->driver_type],
2005                 sizeof(card->shortname));
2006         snprintf(card->longname, sizeof(card->longname),
2007                  "%s at 0x%lx irq %i",
2008                  card->shortname, bus->addr, bus->irq);
2009
2010         return 0;
2011 }
2012
2013 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2014 /* callback from request_firmware_nowait() */
2015 static void azx_firmware_cb(const struct firmware *fw, void *context)
2016 {
2017         struct snd_card *card = context;
2018         struct azx *chip = card->private_data;
2019
2020         if (fw)
2021                 chip->fw = fw;
2022         else
2023                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2024         if (!chip->disabled) {
2025                 /* continue probing */
2026                 azx_probe_continue(chip);
2027         }
2028 }
2029 #endif
2030
2031 static int disable_msi_reset_irq(struct azx *chip)
2032 {
2033         struct hdac_bus *bus = azx_bus(chip);
2034         int err;
2035
2036         free_irq(bus->irq, chip);
2037         bus->irq = -1;
2038         chip->card->sync_irq = -1;
2039         pci_disable_msi(chip->pci);
2040         chip->msi = 0;
2041         err = azx_acquire_irq(chip, 1);
2042         if (err < 0)
2043                 return err;
2044
2045         return 0;
2046 }
2047
2048 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2049                              struct vm_area_struct *area)
2050 {
2051 #ifdef CONFIG_X86
2052         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2053         struct azx *chip = apcm->chip;
2054         if (chip->uc_buffer)
2055                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2056 #endif
2057 }
2058
2059 /* Denylist for skipping the whole probe:
2060  * some HD-audio PCI entries are exposed without any codecs, and such devices
2061  * should be ignored from the beginning.
2062  */
2063 static const struct pci_device_id driver_denylist[] = {
2064         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2065         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2066         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2067         {}
2068 };
2069
2070 static const struct hda_controller_ops pci_hda_ops = {
2071         .disable_msi_reset_irq = disable_msi_reset_irq,
2072         .pcm_mmap_prepare = pcm_mmap_prepare,
2073         .position_check = azx_position_check,
2074 };
2075
2076 static int azx_probe(struct pci_dev *pci,
2077                      const struct pci_device_id *pci_id)
2078 {
2079         static int dev;
2080         struct snd_card *card;
2081         struct hda_intel *hda;
2082         struct azx *chip;
2083         bool schedule_probe;
2084         int err;
2085
2086         if (pci_match_id(driver_denylist, pci)) {
2087                 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2088                 return -ENODEV;
2089         }
2090
2091         if (dev >= SNDRV_CARDS)
2092                 return -ENODEV;
2093         if (!enable[dev]) {
2094                 dev++;
2095                 return -ENOENT;
2096         }
2097
2098         /*
2099          * stop probe if another Intel's DSP driver should be activated
2100          */
2101         if (dmic_detect) {
2102                 err = snd_intel_dsp_driver_probe(pci);
2103                 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2104                         dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2105                         return -ENODEV;
2106                 }
2107         } else {
2108                 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2109         }
2110
2111         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2112                            0, &card);
2113         if (err < 0) {
2114                 dev_err(&pci->dev, "Error creating card!\n");
2115                 return err;
2116         }
2117
2118         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2119         if (err < 0)
2120                 goto out_free;
2121         card->private_data = chip;
2122         hda = container_of(chip, struct hda_intel, chip);
2123
2124         pci_set_drvdata(pci, card);
2125
2126         err = register_vga_switcheroo(chip);
2127         if (err < 0) {
2128                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2129                 goto out_free;
2130         }
2131
2132         if (check_hdmi_disabled(pci)) {
2133                 dev_info(card->dev, "VGA controller is disabled\n");
2134                 dev_info(card->dev, "Delaying initialization\n");
2135                 chip->disabled = true;
2136         }
2137
2138         schedule_probe = !chip->disabled;
2139
2140 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2141         if (patch[dev] && *patch[dev]) {
2142                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2143                          patch[dev]);
2144                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2145                                               &pci->dev, GFP_KERNEL, card,
2146                                               azx_firmware_cb);
2147                 if (err < 0)
2148                         goto out_free;
2149                 schedule_probe = false; /* continued in azx_firmware_cb() */
2150         }
2151 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2152
2153 #ifndef CONFIG_SND_HDA_I915
2154         if (CONTROLLER_IN_GPU(pci))
2155                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2156 #endif
2157
2158         if (schedule_probe)
2159                 schedule_work(&hda->probe_work);
2160
2161         dev++;
2162         if (chip->disabled)
2163                 complete_all(&hda->probe_wait);
2164         return 0;
2165
2166 out_free:
2167         snd_card_free(card);
2168         return err;
2169 }
2170
2171 #ifdef CONFIG_PM
2172 /* On some boards setting power_save to a non 0 value leads to clicking /
2173  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2174  * figure out how to avoid these sounds, but that is not always feasible.
2175  * So we keep a list of devices where we disable powersaving as its known
2176  * to causes problems on these devices.
2177  */
2178 static const struct snd_pci_quirk power_save_denylist[] = {
2179         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2180         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2181         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2182         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2183         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2184         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2185         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2186         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2187         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2188         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2189         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2190         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2191         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2192         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2193         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2194         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2195         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2196         /* https://bugs.launchpad.net/bugs/1821663 */
2197         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2198         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2199         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2200         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2201         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2202         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2203         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2204         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2205         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2206         /* https://bugs.launchpad.net/bugs/1821663 */
2207         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2208         {}
2209 };
2210 #endif /* CONFIG_PM */
2211
2212 static void set_default_power_save(struct azx *chip)
2213 {
2214         int val = power_save;
2215
2216 #ifdef CONFIG_PM
2217         if (pm_blacklist) {
2218                 const struct snd_pci_quirk *q;
2219
2220                 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2221                 if (q && val) {
2222                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2223                                  q->subvendor, q->subdevice);
2224                         val = 0;
2225                 }
2226         }
2227 #endif /* CONFIG_PM */
2228         snd_hda_set_power_save(&chip->bus, val * 1000);
2229 }
2230
2231 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2232 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2233         [AZX_DRIVER_NVIDIA] = 8,
2234         [AZX_DRIVER_TERA] = 1,
2235 };
2236
2237 static int azx_probe_continue(struct azx *chip)
2238 {
2239         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2240         struct hdac_bus *bus = azx_bus(chip);
2241         struct pci_dev *pci = chip->pci;
2242         int dev = chip->dev_index;
2243         int err;
2244
2245         to_hda_bus(bus)->bus_probing = 1;
2246         hda->probe_continued = 1;
2247
2248         /* bind with i915 if needed */
2249         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2250                 err = snd_hdac_i915_init(bus);
2251                 if (err < 0) {
2252                         /* if the controller is bound only with HDMI/DP
2253                          * (for HSW and BDW), we need to abort the probe;
2254                          * for other chips, still continue probing as other
2255                          * codecs can be on the same link.
2256                          */
2257                         if (CONTROLLER_IN_GPU(pci)) {
2258                                 dev_err(chip->card->dev,
2259                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2260                                 goto out_free;
2261                         } else {
2262                                 /* don't bother any longer */
2263                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2264                         }
2265                 }
2266
2267                 /* HSW/BDW controllers need this power */
2268                 if (CONTROLLER_IN_GPU(pci))
2269                         hda->need_i915_power = true;
2270         }
2271
2272         /* Request display power well for the HDA controller or codec. For
2273          * Haswell/Broadwell, both the display HDA controller and codec need
2274          * this power. For other platforms, like Baytrail/Braswell, only the
2275          * display codec needs the power and it can be released after probe.
2276          */
2277         display_power(chip, true);
2278
2279         err = azx_first_init(chip);
2280         if (err < 0)
2281                 goto out_free;
2282
2283 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2284         chip->beep_mode = beep_mode[dev];
2285 #endif
2286
2287         /* create codec instances */
2288         if (bus->codec_mask) {
2289                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2290                 if (err < 0)
2291                         goto out_free;
2292         }
2293
2294 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2295         if (chip->fw) {
2296                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2297                                          chip->fw->data);
2298                 if (err < 0)
2299                         goto out_free;
2300 #ifndef CONFIG_PM
2301                 release_firmware(chip->fw); /* no longer needed */
2302                 chip->fw = NULL;
2303 #endif
2304         }
2305 #endif
2306         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2307                 err = azx_codec_configure(chip);
2308                 if (err < 0)
2309                         goto out_free;
2310         }
2311
2312         err = snd_card_register(chip->card);
2313         if (err < 0)
2314                 goto out_free;
2315
2316         setup_vga_switcheroo_runtime_pm(chip);
2317
2318         chip->running = 1;
2319         azx_add_card_list(chip);
2320
2321         set_default_power_save(chip);
2322
2323         if (azx_has_pm_runtime(chip)) {
2324                 pm_runtime_use_autosuspend(&pci->dev);
2325                 pm_runtime_allow(&pci->dev);
2326                 pm_runtime_put_autosuspend(&pci->dev);
2327         }
2328
2329 out_free:
2330         if (err < 0) {
2331                 azx_free(chip);
2332                 return err;
2333         }
2334
2335         if (!hda->need_i915_power)
2336                 display_power(chip, false);
2337         complete_all(&hda->probe_wait);
2338         to_hda_bus(bus)->bus_probing = 0;
2339         return 0;
2340 }
2341
2342 static void azx_remove(struct pci_dev *pci)
2343 {
2344         struct snd_card *card = pci_get_drvdata(pci);
2345         struct azx *chip;
2346         struct hda_intel *hda;
2347
2348         if (card) {
2349                 /* cancel the pending probing work */
2350                 chip = card->private_data;
2351                 hda = container_of(chip, struct hda_intel, chip);
2352                 /* FIXME: below is an ugly workaround.
2353                  * Both device_release_driver() and driver_probe_device()
2354                  * take *both* the device's and its parent's lock before
2355                  * calling the remove() and probe() callbacks.  The codec
2356                  * probe takes the locks of both the codec itself and its
2357                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2358                  * the PCI controller is unbound, it takes its lock, too
2359                  * ==> ouch, a deadlock!
2360                  * As a workaround, we unlock temporarily here the controller
2361                  * device during cancel_work_sync() call.
2362                  */
2363                 device_unlock(&pci->dev);
2364                 cancel_work_sync(&hda->probe_work);
2365                 device_lock(&pci->dev);
2366
2367                 snd_card_free(card);
2368         }
2369 }
2370
2371 static void azx_shutdown(struct pci_dev *pci)
2372 {
2373         struct snd_card *card = pci_get_drvdata(pci);
2374         struct azx *chip;
2375
2376         if (!card)
2377                 return;
2378         chip = card->private_data;
2379         if (chip && chip->running)
2380                 azx_stop_chip(chip);
2381 }
2382
2383 /* PCI IDs */
2384 static const struct pci_device_id azx_ids[] = {
2385         /* CPT */
2386         { PCI_DEVICE(0x8086, 0x1c20),
2387           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2388         /* PBG */
2389         { PCI_DEVICE(0x8086, 0x1d20),
2390           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2391         /* Panther Point */
2392         { PCI_DEVICE(0x8086, 0x1e20),
2393           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2394         /* Lynx Point */
2395         { PCI_DEVICE(0x8086, 0x8c20),
2396           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2397         /* 9 Series */
2398         { PCI_DEVICE(0x8086, 0x8ca0),
2399           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2400         /* Wellsburg */
2401         { PCI_DEVICE(0x8086, 0x8d20),
2402           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2403         { PCI_DEVICE(0x8086, 0x8d21),
2404           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2405         /* Lewisburg */
2406         { PCI_DEVICE(0x8086, 0xa1f0),
2407           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2408         { PCI_DEVICE(0x8086, 0xa270),
2409           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2410         /* Lynx Point-LP */
2411         { PCI_DEVICE(0x8086, 0x9c20),
2412           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2413         /* Lynx Point-LP */
2414         { PCI_DEVICE(0x8086, 0x9c21),
2415           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2416         /* Wildcat Point-LP */
2417         { PCI_DEVICE(0x8086, 0x9ca0),
2418           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2419         /* Sunrise Point */
2420         { PCI_DEVICE(0x8086, 0xa170),
2421           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2422         /* Sunrise Point-LP */
2423         { PCI_DEVICE(0x8086, 0x9d70),
2424           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2425         /* Kabylake */
2426         { PCI_DEVICE(0x8086, 0xa171),
2427           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2428         /* Kabylake-LP */
2429         { PCI_DEVICE(0x8086, 0x9d71),
2430           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2431         /* Kabylake-H */
2432         { PCI_DEVICE(0x8086, 0xa2f0),
2433           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2434         /* Coffelake */
2435         { PCI_DEVICE(0x8086, 0xa348),
2436           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2437         /* Cannonlake */
2438         { PCI_DEVICE(0x8086, 0x9dc8),
2439           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2440         /* CometLake-LP */
2441         { PCI_DEVICE(0x8086, 0x02C8),
2442           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2443         /* CometLake-H */
2444         { PCI_DEVICE(0x8086, 0x06C8),
2445           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2446         { PCI_DEVICE(0x8086, 0xf1c8),
2447           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2448         /* CometLake-S */
2449         { PCI_DEVICE(0x8086, 0xa3f0),
2450           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2451         /* CometLake-R */
2452         { PCI_DEVICE(0x8086, 0xf0c8),
2453           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2454         /* Icelake */
2455         { PCI_DEVICE(0x8086, 0x34c8),
2456           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2457         /* Icelake-H */
2458         { PCI_DEVICE(0x8086, 0x3dc8),
2459           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2460         /* Jasperlake */
2461         { PCI_DEVICE(0x8086, 0x38c8),
2462           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2463         { PCI_DEVICE(0x8086, 0x4dc8),
2464           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2465         /* Tigerlake */
2466         { PCI_DEVICE(0x8086, 0xa0c8),
2467           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2468         /* Tigerlake-H */
2469         { PCI_DEVICE(0x8086, 0x43c8),
2470           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2471         /* DG1 */
2472         { PCI_DEVICE(0x8086, 0x490d),
2473           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2474         /* Alderlake-S */
2475         { PCI_DEVICE(0x8086, 0x7ad0),
2476           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2477         /* Alderlake-P */
2478         { PCI_DEVICE(0x8086, 0x51c8),
2479           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2480         /* Elkhart Lake */
2481         { PCI_DEVICE(0x8086, 0x4b55),
2482           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2483         { PCI_DEVICE(0x8086, 0x4b58),
2484           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2485         /* Broxton-P(Apollolake) */
2486         { PCI_DEVICE(0x8086, 0x5a98),
2487           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2488         /* Broxton-T */
2489         { PCI_DEVICE(0x8086, 0x1a98),
2490           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2491         /* Gemini-Lake */
2492         { PCI_DEVICE(0x8086, 0x3198),
2493           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2494         /* Haswell */
2495         { PCI_DEVICE(0x8086, 0x0a0c),
2496           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2497         { PCI_DEVICE(0x8086, 0x0c0c),
2498           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2499         { PCI_DEVICE(0x8086, 0x0d0c),
2500           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2501         /* Broadwell */
2502         { PCI_DEVICE(0x8086, 0x160c),
2503           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2504         /* 5 Series/3400 */
2505         { PCI_DEVICE(0x8086, 0x3b56),
2506           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2507         /* Poulsbo */
2508         { PCI_DEVICE(0x8086, 0x811b),
2509           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2510         /* Oaktrail */
2511         { PCI_DEVICE(0x8086, 0x080a),
2512           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2513         /* BayTrail */
2514         { PCI_DEVICE(0x8086, 0x0f04),
2515           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2516         /* Braswell */
2517         { PCI_DEVICE(0x8086, 0x2284),
2518           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2519         /* ICH6 */
2520         { PCI_DEVICE(0x8086, 0x2668),
2521           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2522         /* ICH7 */
2523         { PCI_DEVICE(0x8086, 0x27d8),
2524           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2525         /* ESB2 */
2526         { PCI_DEVICE(0x8086, 0x269a),
2527           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2528         /* ICH8 */
2529         { PCI_DEVICE(0x8086, 0x284b),
2530           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2531         /* ICH9 */
2532         { PCI_DEVICE(0x8086, 0x293e),
2533           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2534         /* ICH9 */
2535         { PCI_DEVICE(0x8086, 0x293f),
2536           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2537         /* ICH10 */
2538         { PCI_DEVICE(0x8086, 0x3a3e),
2539           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2540         /* ICH10 */
2541         { PCI_DEVICE(0x8086, 0x3a6e),
2542           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2543         /* Generic Intel */
2544         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2545           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2546           .class_mask = 0xffffff,
2547           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2548         /* ATI SB 450/600/700/800/900 */
2549         { PCI_DEVICE(0x1002, 0x437b),
2550           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2551         { PCI_DEVICE(0x1002, 0x4383),
2552           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2553         /* AMD Hudson */
2554         { PCI_DEVICE(0x1022, 0x780d),
2555           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2556         /* AMD, X370 & co */
2557         { PCI_DEVICE(0x1022, 0x1457),
2558           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2559         /* AMD, X570 & co */
2560         { PCI_DEVICE(0x1022, 0x1487),
2561           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2562         /* AMD Stoney */
2563         { PCI_DEVICE(0x1022, 0x157a),
2564           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2565                          AZX_DCAPS_PM_RUNTIME },
2566         /* AMD Raven */
2567         { PCI_DEVICE(0x1022, 0x15e3),
2568           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2569         /* ATI HDMI */
2570         { PCI_DEVICE(0x1002, 0x0002),
2571           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2572           AZX_DCAPS_PM_RUNTIME },
2573         { PCI_DEVICE(0x1002, 0x1308),
2574           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2575         { PCI_DEVICE(0x1002, 0x157a),
2576           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2577         { PCI_DEVICE(0x1002, 0x15b3),
2578           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2579         { PCI_DEVICE(0x1002, 0x793b),
2580           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2581         { PCI_DEVICE(0x1002, 0x7919),
2582           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2583         { PCI_DEVICE(0x1002, 0x960f),
2584           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2585         { PCI_DEVICE(0x1002, 0x970f),
2586           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2587         { PCI_DEVICE(0x1002, 0x9840),
2588           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2589         { PCI_DEVICE(0x1002, 0xaa00),
2590           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591         { PCI_DEVICE(0x1002, 0xaa08),
2592           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2593         { PCI_DEVICE(0x1002, 0xaa10),
2594           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595         { PCI_DEVICE(0x1002, 0xaa18),
2596           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597         { PCI_DEVICE(0x1002, 0xaa20),
2598           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599         { PCI_DEVICE(0x1002, 0xaa28),
2600           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2601         { PCI_DEVICE(0x1002, 0xaa30),
2602           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2603         { PCI_DEVICE(0x1002, 0xaa38),
2604           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605         { PCI_DEVICE(0x1002, 0xaa40),
2606           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2607         { PCI_DEVICE(0x1002, 0xaa48),
2608           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609         { PCI_DEVICE(0x1002, 0xaa50),
2610           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611         { PCI_DEVICE(0x1002, 0xaa58),
2612           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613         { PCI_DEVICE(0x1002, 0xaa60),
2614           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615         { PCI_DEVICE(0x1002, 0xaa68),
2616           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617         { PCI_DEVICE(0x1002, 0xaa80),
2618           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619         { PCI_DEVICE(0x1002, 0xaa88),
2620           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621         { PCI_DEVICE(0x1002, 0xaa90),
2622           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623         { PCI_DEVICE(0x1002, 0xaa98),
2624           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625         { PCI_DEVICE(0x1002, 0x9902),
2626           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2627         { PCI_DEVICE(0x1002, 0xaaa0),
2628           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2629         { PCI_DEVICE(0x1002, 0xaaa8),
2630           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2631         { PCI_DEVICE(0x1002, 0xaab0),
2632           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2633         { PCI_DEVICE(0x1002, 0xaac0),
2634           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2635           AZX_DCAPS_PM_RUNTIME },
2636         { PCI_DEVICE(0x1002, 0xaac8),
2637           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2638           AZX_DCAPS_PM_RUNTIME },
2639         { PCI_DEVICE(0x1002, 0xaad8),
2640           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2641           AZX_DCAPS_PM_RUNTIME },
2642         { PCI_DEVICE(0x1002, 0xaae0),
2643           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2644           AZX_DCAPS_PM_RUNTIME },
2645         { PCI_DEVICE(0x1002, 0xaae8),
2646           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2647           AZX_DCAPS_PM_RUNTIME },
2648         { PCI_DEVICE(0x1002, 0xaaf0),
2649           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2650           AZX_DCAPS_PM_RUNTIME },
2651         { PCI_DEVICE(0x1002, 0xaaf8),
2652           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2653           AZX_DCAPS_PM_RUNTIME },
2654         { PCI_DEVICE(0x1002, 0xab00),
2655           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2656           AZX_DCAPS_PM_RUNTIME },
2657         { PCI_DEVICE(0x1002, 0xab08),
2658           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2659           AZX_DCAPS_PM_RUNTIME },
2660         { PCI_DEVICE(0x1002, 0xab10),
2661           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2662           AZX_DCAPS_PM_RUNTIME },
2663         { PCI_DEVICE(0x1002, 0xab18),
2664           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2665           AZX_DCAPS_PM_RUNTIME },
2666         { PCI_DEVICE(0x1002, 0xab20),
2667           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2668           AZX_DCAPS_PM_RUNTIME },
2669         { PCI_DEVICE(0x1002, 0xab28),
2670           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2671           AZX_DCAPS_PM_RUNTIME },
2672         { PCI_DEVICE(0x1002, 0xab38),
2673           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2674           AZX_DCAPS_PM_RUNTIME },
2675         /* VIA VT8251/VT8237A */
2676         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2677         /* VIA GFX VT7122/VX900 */
2678         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2679         /* VIA GFX VT6122/VX11 */
2680         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2681         /* SIS966 */
2682         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2683         /* ULI M5461 */
2684         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2685         /* NVIDIA MCP */
2686         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2687           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2688           .class_mask = 0xffffff,
2689           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2690         /* Teradici */
2691         { PCI_DEVICE(0x6549, 0x1200),
2692           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2693         { PCI_DEVICE(0x6549, 0x2200),
2694           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2695         /* Creative X-Fi (CA0110-IBG) */
2696         /* CTHDA chips */
2697         { PCI_DEVICE(0x1102, 0x0010),
2698           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2699         { PCI_DEVICE(0x1102, 0x0012),
2700           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2701 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2702         /* the following entry conflicts with snd-ctxfi driver,
2703          * as ctxfi driver mutates from HD-audio to native mode with
2704          * a special command sequence.
2705          */
2706         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2707           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2708           .class_mask = 0xffffff,
2709           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2710           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2711 #else
2712         /* this entry seems still valid -- i.e. without emu20kx chip */
2713         { PCI_DEVICE(0x1102, 0x0009),
2714           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2715           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2716 #endif
2717         /* CM8888 */
2718         { PCI_DEVICE(0x13f6, 0x5011),
2719           .driver_data = AZX_DRIVER_CMEDIA |
2720           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2721         /* Vortex86MX */
2722         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2723         /* VMware HDAudio */
2724         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2725         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2726         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2727           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2728           .class_mask = 0xffffff,
2729           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2730         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2731           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2732           .class_mask = 0xffffff,
2733           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2734         /* Zhaoxin */
2735         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2736         { 0, }
2737 };
2738 MODULE_DEVICE_TABLE(pci, azx_ids);
2739
2740 /* pci_driver definition */
2741 static struct pci_driver azx_driver = {
2742         .name = KBUILD_MODNAME,
2743         .id_table = azx_ids,
2744         .probe = azx_probe,
2745         .remove = azx_remove,
2746         .shutdown = azx_shutdown,
2747         .driver = {
2748                 .pm = AZX_PM_OPS,
2749         },
2750 };
2751
2752 module_pci_driver(azx_driver);