sound/pci/cmipci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   4  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   5  */
   6
   7 /* Does not work. Warning may block system in capture mode */
   8 /* #define USE_VAR48KRATE */
   9
  10 #include <linux/io.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/gameport.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <sound/core.h>
  20 #include <sound/info.h>
  21 #include <sound/control.h>
  22 #include <sound/pcm.h>
  23 #include <sound/rawmidi.h>
  24 #include <sound/mpu401.h>
  25 #include <sound/opl3.h>
  26 #include <sound/sb.h>
  27 #include <sound/asoundef.h>
  28 #include <sound/initval.h>
  29
  30 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  31 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  32 MODULE_LICENSE("GPL");
  33
  34 #if IS_REACHABLE(CONFIG_GAMEPORT)
  35 #define SUPPORT_JOYSTICK 1
  36 #endif
  37
  38 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  39 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  40 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  41 static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
  42 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  43 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  44 #ifdef SUPPORT_JOYSTICK
  45 static int joystick_port[SNDRV_CARDS];
  46 #endif
  47
  48 module_param_array(index, int, NULL, 0444);
  49 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  50 module_param_array(id, charp, NULL, 0444);
  51 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  52 module_param_array(enable, bool, NULL, 0444);
  53 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  54 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
  55 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  56 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
  57 MODULE_PARM_DESC(fm_port, "FM port.");
  58 module_param_array(soft_ac3, bool, NULL, 0444);
  59 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
  60 #ifdef SUPPORT_JOYSTICK
  61 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  62 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  63 #endif
  64
  65 /*
  66  * CM8x38 registers definition
  67  */
  68
  69 #define CM_REG_FUNCTRL0         0x00
  70 #define CM_RST_CH1              0x00080000
  71 #define CM_RST_CH0              0x00040000
  72 #define CM_CHEN1                0x00020000      /* ch1: enable */
  73 #define CM_CHEN0                0x00010000      /* ch0: enable */
  74 #define CM_PAUSE1               0x00000008      /* ch1: pause */
  75 #define CM_PAUSE0               0x00000004      /* ch0: pause */
  76 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
  77 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
  78
  79 #define CM_REG_FUNCTRL1         0x04
  80 #define CM_DSFC_MASK            0x0000E000      /* channel 1 (DAC?) sampling frequency */
  81 #define CM_DSFC_SHIFT           13
  82 #define CM_ASFC_MASK            0x00001C00      /* channel 0 (ADC?) sampling frequency */
  83 #define CM_ASFC_SHIFT           10
  84 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
  85 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
  86 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/IN -> OUT loopback */
  87 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
  88 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
  89 #define CM_BREQ                 0x00000010      /* bus master enabled */
  90 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
  91 #define CM_UART_EN              0x00000004      /* legacy UART */
  92 #define CM_JYSTK_EN             0x00000002      /* legacy joystick */
  93 #define CM_ZVPORT               0x00000001      /* ZVPORT */
  94
  95 #define CM_REG_CHFORMAT         0x08
  96
  97 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
  98 #define CM_FMOFFSET2            0x40000000      /* initial FM PCM offset 2 when Fmute=1 */
  99 #define CM_CHB3D                0x20000000      /* 4 channels */
 100
 101 #define CM_CHIP_MASK1           0x1f000000
 102 #define CM_CHIP_037             0x01000000
 103 #define CM_SETLAT48             0x00800000      /* set latency timer 48h */
 104 #define CM_EDGEIRQ              0x00400000      /* emulated edge trigger legacy IRQ */
 105 #define CM_SPD24SEL39           0x00200000      /* 24-bit spdif: model 039 */
 106 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 107 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 108 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 109 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 110
 111 #define CM_ADCBITLEN_MASK       0x0000C000
 112 #define CM_ADCBITLEN_16         0x00000000
 113 #define CM_ADCBITLEN_15         0x00004000
 114 #define CM_ADCBITLEN_14         0x00008000
 115 #define CM_ADCBITLEN_13         0x0000C000
 116
 117 #define CM_ADCDACLEN_MASK       0x00003000      /* model 037 */
 118 #define CM_ADCDACLEN_060        0x00000000
 119 #define CM_ADCDACLEN_066        0x00001000
 120 #define CM_ADCDACLEN_130        0x00002000
 121 #define CM_ADCDACLEN_280        0x00003000
 122
 123 #define CM_ADCDLEN_MASK         0x00003000      /* model 039 */
 124 #define CM_ADCDLEN_ORIGINAL     0x00000000
 125 #define CM_ADCDLEN_EXTRA        0x00001000
 126 #define CM_ADCDLEN_24K          0x00002000
 127 #define CM_ADCDLEN_WEIGHT       0x00003000
 128
 129 #define CM_CH1_SRATE_176K       0x00000800
 130 #define CM_CH1_SRATE_96K        0x00000800      /* model 055? */
 131 #define CM_CH1_SRATE_88K        0x00000400
 132 #define CM_CH0_SRATE_176K       0x00000200
 133 #define CM_CH0_SRATE_96K        0x00000200      /* model 055? */
 134 #define CM_CH0_SRATE_88K        0x00000100
 135 #define CM_CH0_SRATE_128K       0x00000300
 136 #define CM_CH0_SRATE_MASK       0x00000300
 137
 138 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 139 #define CM_DBLSPDS              0x00000040      /* double SPDIF sample rate 88.2/96 */
 140 #define CM_POLVALID             0x00000020      /* inverse SPDIF/IN valid bit */
 141 #define CM_SPDLOCKED            0x00000010
 142
 143 #define CM_CH1FMT_MASK          0x0000000C      /* bit 3: 16 bits, bit 2: stereo */
 144 #define CM_CH1FMT_SHIFT         2
 145 #define CM_CH0FMT_MASK          0x00000003      /* bit 1: 16 bits, bit 0: stereo */
 146 #define CM_CH0FMT_SHIFT         0
 147
 148 #define CM_REG_INT_HLDCLR       0x0C
 149 #define CM_CHIP_MASK2           0xff000000
 150 #define CM_CHIP_8768            0x20000000
 151 #define CM_CHIP_055             0x08000000
 152 #define CM_CHIP_039             0x04000000
 153 #define CM_CHIP_039_6CH         0x01000000
 154 #define CM_UNKNOWN_INT_EN       0x00080000      /* ? */
 155 #define CM_TDMA_INT_EN          0x00040000
 156 #define CM_CH1_INT_EN           0x00020000
 157 #define CM_CH0_INT_EN           0x00010000
 158
 159 #define CM_REG_INT_STATUS       0x10
 160 #define CM_INTR                 0x80000000
 161 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 162 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 163 #define CM_UARTINT              0x00010000
 164 #define CM_LTDMAINT             0x00008000
 165 #define CM_HTDMAINT             0x00004000
 166 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 167 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 168 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 169 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 170 #define CM_CH1BUSY              0x00000008
 171 #define CM_CH0BUSY              0x00000004
 172 #define CM_CHINT1               0x00000002
 173 #define CM_CHINT0               0x00000001
 174
 175 #define CM_REG_LEGACY_CTRL      0x14
 176 #define CM_NXCHG                0x80000000      /* don't map base reg dword->sample */
 177 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 178 #define CM_VMPU_330             0x00000000
 179 #define CM_VMPU_320             0x20000000
 180 #define CM_VMPU_310             0x40000000
 181 #define CM_VMPU_300             0x60000000
 182 #define CM_ENWR8237             0x10000000      /* enable bus master to write 8237 base reg */
 183 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 184 #define CM_VSBSEL_220           0x00000000
 185 #define CM_VSBSEL_240           0x04000000
 186 #define CM_VSBSEL_260           0x08000000
 187 #define CM_VSBSEL_280           0x0C000000
 188 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 189 #define CM_FMSEL_388            0x00000000
 190 #define CM_FMSEL_3C8            0x01000000
 191 #define CM_FMSEL_3E0            0x02000000
 192 #define CM_FMSEL_3E8            0x03000000
 193 #define CM_ENSPDOUT             0x00800000      /* enable XSPDIF/OUT to I/O interface */
 194 #define CM_SPDCOPYRHT           0x00400000      /* spdif in/out copyright bit */
 195 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 196 #define CM_INVIDWEN             0x00100000      /* internal vendor ID write enable, model 039? */
 197 #define CM_SETRETRY             0x00100000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 198 #define CM_C_EEACCESS           0x00080000      /* direct programming eeprom regs */
 199 #define CM_C_EECS               0x00040000
 200 #define CM_C_EEDI46             0x00020000
 201 #define CM_C_EECK46             0x00010000
 202 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 203 #define CM_CENTR2LIN            0x00004000      /* line-in as center out */
 204 #define CM_BASE2LIN             0x00002000      /* line-in as bass out */
 205 #define CM_EXBASEN              0x00001000      /* external bass input enable */
 206
 207 #define CM_REG_MISC_CTRL        0x18
 208 #define CM_PWD                  0x80000000      /* power down */
 209 #define CM_RESET                0x40000000
 210 #define CM_SFIL_MASK            0x30000000      /* filter control at front end DAC, model 037? */
 211 #define CM_VMGAIN               0x10000000      /* analog master amp +6dB, model 039? */
 212 #define CM_TXVX                 0x08000000      /* model 037? */
 213 #define CM_N4SPK3D              0x04000000      /* copy front to rear */
 214 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 215 #define CM_SPDIF48K             0x01000000      /* write */
 216 #define CM_SPATUS48K            0x01000000      /* read */
 217 #define CM_ENDBDAC              0x00800000      /* enable double dac */
 218 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 219 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 220 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-OUT -> int. IN */
 221 #define CM_FM_EN                0x00080000      /* enable legacy FM */
 222 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 223 #define CM_ENWRASID             0x00010000      /* choose writable internal SUBID (audio) */
 224 #define CM_VIDWPDSB             0x00010000      /* model 037? */
 225 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 226 #define CM_MASK_EN              0x00004000      /* activate channel mask on legacy DMA */
 227 #define CM_ENWRMSID             0x00002000      /* choose writable internal SUBID (modem) */
 228 #define CM_VIDWPPRT             0x00002000      /* model 037? */
 229 #define CM_SFILENB              0x00001000      /* filter stepping at front end DAC, model 037? */
 230 #define CM_MMODE_MASK           0x00000E00      /* model DAA interface mode */
 231 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 232 #define CM_ENCENTER             0x00000080
 233 #define CM_FLINKON              0x00000040      /* force modem link detection on, model 037 */
 234 #define CM_MUTECH1              0x00000040      /* mute PCI ch1 to DAC */
 235 #define CM_FLINKOFF             0x00000020      /* force modem link detection off, model 037 */
 236 #define CM_MIDSMP               0x00000010      /* 1/2 interpolation at front end DAC */
 237 #define CM_UPDDMA_MASK          0x0000000C      /* TDMA position update notification */
 238 #define CM_UPDDMA_2048          0x00000000
 239 #define CM_UPDDMA_1024          0x00000004
 240 #define CM_UPDDMA_512           0x00000008
 241 #define CM_UPDDMA_256           0x0000000C
 242 #define CM_TWAIT_MASK           0x00000003      /* model 037 */
 243 #define CM_TWAIT1               0x00000002      /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
 244 #define CM_TWAIT0               0x00000001      /* i/o cycle, 0: 4, 1: 6 PCICLKs */
 245
 246 #define CM_REG_TDMA_POSITION    0x1C
 247 #define CM_TDMA_CNT_MASK        0xFFFF0000      /* current byte/word count */
 248 #define CM_TDMA_ADR_MASK        0x0000FFFF      /* current address */
 249
 250         /* byte */
 251 #define CM_REG_MIXER0           0x20
 252 #define CM_REG_SBVR             0x20            /* write: sb16 version */
 253 #define CM_REG_DEV              0x20            /* read: hardware device version */
 254
 255 #define CM_REG_MIXER21          0x21
 256 #define CM_UNKNOWN_21_MASK      0x78            /* ? */
 257 #define CM_X_ADPCM              0x04            /* SB16 ADPCM enable */
 258 #define CM_PROINV               0x02            /* SBPro left/right channel switching */
 259 #define CM_X_SB16               0x01            /* SB16 compatible */
 260
 261 #define CM_REG_SB16_DATA        0x22
 262 #define CM_REG_SB16_ADDR        0x23
 263
 264 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 265 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 266 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 267 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 268
 269 #define CM_REG_MIXER1           0x24
 270 #define CM_FMMUTE               0x80    /* mute FM */
 271 #define CM_FMMUTE_SHIFT         7
 272 #define CM_WSMUTE               0x40    /* mute PCM */
 273 #define CM_WSMUTE_SHIFT         6
 274 #define CM_REAR2LIN             0x20    /* lin-in -> rear line out */
 275 #define CM_REAR2LIN_SHIFT       5
 276 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 277 #define CM_REAR2FRONT_SHIFT     4
 278 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 279 #define CM_WAVEINL_SHIFT        3
 280 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 281 #define CM_WAVEINR_SHIFT        2
 282 #define CM_X3DEN                0x02    /* 3D surround enable */
 283 #define CM_X3DEN_SHIFT          1
 284 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 285 #define CM_CDPLAY_SHIFT         0
 286
 287 #define CM_REG_MIXER2           0x25
 288 #define CM_RAUXREN              0x80    /* AUX right capture */
 289 #define CM_RAUXREN_SHIFT        7
 290 #define CM_RAUXLEN              0x40    /* AUX left capture */
 291 #define CM_RAUXLEN_SHIFT        6
 292 #define CM_VAUXRM               0x20    /* AUX right mute */
 293 #define CM_VAUXRM_SHIFT         5
 294 #define CM_VAUXLM               0x10    /* AUX left mute */
 295 #define CM_VAUXLM_SHIFT         4
 296 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 297 #define CM_VADMIC_SHIFT         1
 298 #define CM_MICGAINZ             0x01    /* mic boost */
 299 #define CM_MICGAINZ_SHIFT       0
 300
 301 #define CM_REG_AUX_VOL          0x26
 302 #define CM_VAUXL_MASK           0xf0
 303 #define CM_VAUXR_MASK           0x0f
 304
 305 #define CM_REG_MISC             0x27
 306 #define CM_UNKNOWN_27_MASK      0xd8    /* ? */
 307 #define CM_XGPO1                0x20
 308 // #define CM_XGPBIO            0x04
 309 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 310 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 311 #define CM_SPDVALID             0x02    /* spdif input valid check */
 312 #define CM_DMAUTO               0x01    /* SB16 DMA auto detect */
 313
 314 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 315 /*
 316  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 317  * or identical with AC97 codec?
 318  */
 319 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 320
 321 /*
 322  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 323  */
 324 #define CM_REG_MPU_PCI          0x40
 325
 326 /*
 327  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 328  */
 329 #define CM_REG_FM_PCI           0x50
 330
 331 /*
 332  * access from SB-mixer port
 333  */
 334 #define CM_REG_EXTENT_IND       0xf0
 335 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 336 #define CM_VPHONE_SHIFT         5
 337 #define CM_VPHOM                0x10    /* Phone mute control */
 338 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 339 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 340 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 341 #define CM_VADMIC3              0x01    /* Mic record boost */
 342
 343 /*
 344  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 345  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 346  * unit (readonly?).
 347  */
 348 #define CM_REG_PLL              0xf8
 349
 350 /*
 351  * extended registers
 352  */
 353 #define CM_REG_CH0_FRAME1       0x80    /* write: base address */
 354 #define CM_REG_CH0_FRAME2       0x84    /* read: current address */
 355 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 356 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 357
 358 #define CM_REG_EXT_MISC         0x90
 359 #define CM_ADC48K44K            0x10000000      /* ADC parameters group, 0: 44k, 1: 48k */
 360 #define CM_CHB3D8C              0x00200000      /* 7.1 channels support */
 361 #define CM_SPD32FMT             0x00100000      /* SPDIF/IN 32k sample rate */
 362 #define CM_ADC2SPDIF            0x00080000      /* ADC output to SPDIF/OUT */
 363 #define CM_SHAREADC             0x00040000      /* DAC in ADC as Center/LFE */
 364 #define CM_REALTCMP             0x00020000      /* monitor the CMPL/CMPR of ADC */
 365 #define CM_INVLRCK              0x00010000      /* invert ZVPORT's LRCK */
 366 #define CM_UNKNOWN_90_MASK      0x0000FFFF      /* ? */
 367
 368 /*
 369  * size of i/o region
 370  */
 371 #define CM_EXTENT_CODEC   0x100
 372 #define CM_EXTENT_MIDI    0x2
 373 #define CM_EXTENT_SYNTH   0x4
 374
 375
 376 /*
 377  * channels for playback / capture
 378  */
 379 #define CM_CH_PLAY      0
 380 #define CM_CH_CAPT      1
 381
 382 /*
 383  * flags to check device open/close
 384  */
 385 #define CM_OPEN_NONE    0
 386 #define CM_OPEN_CH_MASK 0x01
 387 #define CM_OPEN_DAC     0x10
 388 #define CM_OPEN_ADC     0x20
 389 #define CM_OPEN_SPDIF   0x40
 390 #define CM_OPEN_MCHAN   0x80
 391 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 392 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 393 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 394 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 395 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 396 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 397
 398
 399 #if CM_CH_PLAY == 1
 400 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 401 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 402 #define CM_CAPTURE_SPDF         CM_SPDF_0
 403 #else
 404 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 405 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 406 #define CM_CAPTURE_SPDF         CM_SPDF_1
 407 #endif
 408
 409
 410 /*
 411  * driver data
 412  */
 413
 414 struct cmipci_pcm {
 415         struct snd_pcm_substream *substream;
 416         u8 running;             /* dac/adc running? */
 417         u8 fmt;                 /* format bits */
 418         u8 is_dac;
 419         u8 needs_silencing;
 420         unsigned int dma_size;  /* in frames */
 421         unsigned int shift;
 422         unsigned int ch;        /* channel (0/1) */
 423         unsigned int offset;    /* physical address of the buffer */
 424 };
 425
 426 /* mixer elements toggled/resumed during ac3 playback */
 427 struct cmipci_mixer_auto_switches {
 428         const char *name;       /* switch to toggle */
 429         int toggle_on;          /* value to change when ac3 mode */
 430 };
 431 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 432         {"PCM Playback Switch", 0},
 433         {"IEC958 Output Switch", 1},
 434         {"IEC958 Mix Analog", 0},
 435         // {"IEC958 Out To DAC", 1}, // no longer used
 436         {"IEC958 Loop", 0},
 437 };
 438 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 439
 440 struct cmipci {
 441         struct snd_card *card;
 442
 443         struct pci_dev *pci;
 444         unsigned int device;    /* device ID */
 445         int irq;
 446
 447         unsigned long iobase;
 448         unsigned int ctrl;      /* FUNCTRL0 current value */
 449
 450         struct snd_pcm *pcm;            /* DAC/ADC PCM */
 451         struct snd_pcm *pcm2;   /* 2nd DAC */
 452         struct snd_pcm *pcm_spdif;      /* SPDIF */
 453
 454         int chip_version;
 455         int max_channels;
 456         unsigned int can_ac3_sw: 1;
 457         unsigned int can_ac3_hw: 1;
 458         unsigned int can_multi_ch: 1;
 459         unsigned int can_96k: 1;        /* samplerate above 48k */
 460         unsigned int do_soft_ac3: 1;
 461
 462         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 463         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 464         int spdif_counter;      /* for software AC3 */
 465
 466         unsigned int dig_status;
 467         unsigned int dig_pcm_status;
 468
 469         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
 470
 471         int opened[2];  /* open mode */
 472         struct mutex open_mutex;
 473
 474         unsigned int mixer_insensitive: 1;
 475         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
 476         int mixer_res_status[CM_SAVED_MIXERS];
 477
 478         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 479
 480         /* external MIDI */
 481         struct snd_rawmidi *rmidi;
 482
 483 #ifdef SUPPORT_JOYSTICK
 484         struct gameport *gameport;
 485 #endif
 486
 487         spinlock_t reg_lock;
 488
 489         unsigned int saved_regs[0x20];
 490         unsigned char saved_mixers[0x20];
 491 };
 492
 493
 494 /* read/write operations for dword register */
 495 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
 496 {
 497         outl(data, cm->iobase + cmd);
 498 }
 499
 500 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
 501 {
 502         return inl(cm->iobase + cmd);
 503 }
 504
 505 /* read/write operations for word register */
 506 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
 507 {
 508         outw(data, cm->iobase + cmd);
 509 }
 510
 511 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
 512 {
 513         return inw(cm->iobase + cmd);
 514 }
 515
 516 /* read/write operations for byte register */
 517 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
 518 {
 519         outb(data, cm->iobase + cmd);
 520 }
 521
 522 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
 523 {
 524         return inb(cm->iobase + cmd);
 525 }
 526
 527 /* bit operations for dword register */
 528 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 529 {
 530         unsigned int val, oval;
 531         val = oval = inl(cm->iobase + cmd);
 532         val |= flag;
 533         if (val == oval)
 534                 return 0;
 535         outl(val, cm->iobase + cmd);
 536         return 1;
 537 }
 538
 539 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 540 {
 541         unsigned int val, oval;
 542         val = oval = inl(cm->iobase + cmd);
 543         val &= ~flag;
 544         if (val == oval)
 545                 return 0;
 546         outl(val, cm->iobase + cmd);
 547         return 1;
 548 }
 549
 550 /* bit operations for byte register */
 551 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 552 {
 553         unsigned char val, oval;
 554         val = oval = inb(cm->iobase + cmd);
 555         val |= flag;
 556         if (val == oval)
 557                 return 0;
 558         outb(val, cm->iobase + cmd);
 559         return 1;
 560 }
 561
 562 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 563 {
 564         unsigned char val, oval;
 565         val = oval = inb(cm->iobase + cmd);
 566         val &= ~flag;
 567         if (val == oval)
 568                 return 0;
 569         outb(val, cm->iobase + cmd);
 570         return 1;
 571 }
 572
 573
 574 /*
 575  * PCM interface
 576  */
 577
 578 /*
 579  * calculate frequency
 580  */
 581
 582 static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 583
 584 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 585 {
 586         unsigned int i;
 587
 588         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 589                 if (rates[i] == rate)
 590                         return i;
 591         }
 592         snd_BUG();
 593         return 0;
 594 }
 595
 596 #ifdef USE_VAR48KRATE
 597 /*
 598  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 599  * does it this way .. maybe not.  Never get any information from C-Media about
 600  * that <werner@suse.de>.
 601  */
 602 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 603 {
 604         unsigned int delta, tolerance;
 605         int xm, xn, xr;
 606
 607         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 608                 rate <<= 1;
 609         *n = -1;
 610         if (*r > 0xff)
 611                 goto out;
 612         tolerance = rate*CM_TOLERANCE_RATE;
 613
 614         for (xn = (1+2); xn < (0x1f+2); xn++) {
 615                 for (xm = (1+2); xm < (0xff+2); xm++) {
 616                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 617
 618                         if (xr < rate)
 619                                 delta = rate - xr;
 620                         else
 621                                 delta = xr - rate;
 622
 623                         /*
 624                          * If we found one, remember this,
 625                          * and try to find a closer one
 626                          */
 627                         if (delta < tolerance) {
 628                                 tolerance = delta;
 629                                 *m = xm - 2;
 630                                 *n = xn - 2;
 631                         }
 632                 }
 633         }
 634 out:
 635         return (*n > -1);
 636 }
 637
 638 /*
 639  * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
 640  * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
 641  * at the register CM_REG_FUNCTRL1 (0x04).
 642  * Problem: other ways are also possible (any information about that?)
 643  */
 644 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
 645 {
 646         unsigned int reg = CM_REG_PLL + slot;
 647         /*
 648          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 649          * for DSFC/ASFC (000 up to 111).
 650          */
 651
 652         /* FIXME: Init (Do we've to set an other register first before programming?) */
 653
 654         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 655         snd_cmipci_write_b(cm, reg, rate>>8);
 656         snd_cmipci_write_b(cm, reg, rate&0xff);
 657
 658         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 659 }
 660 #endif /* USE_VAR48KRATE */
 661
 662 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
 663                                           struct snd_pcm_hw_params *hw_params)
 664 {
 665         struct cmipci *cm = snd_pcm_substream_chip(substream);
 666         if (params_channels(hw_params) > 2) {
 667                 mutex_lock(&cm->open_mutex);
 668                 if (cm->opened[CM_CH_PLAY]) {
 669                         mutex_unlock(&cm->open_mutex);
 670                         return -EBUSY;
 671                 }
 672                 /* reserve the channel A */
 673                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 674                 mutex_unlock(&cm->open_mutex);
 675         }
 676         return 0;
 677 }
 678
 679 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
 680 {
 681         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 682         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 683         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 684         udelay(10);
 685 }
 686
 687
 688 /*
 689  */
 690
 691 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
 692 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
 693         .count = 3,
 694         .list = hw_channels,
 695         .mask = 0,
 696 };
 697 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
 698         .count = 4,
 699         .list = hw_channels,
 700         .mask = 0,
 701 };
 702 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
 703         .count = 5,
 704         .list = hw_channels,
 705         .mask = 0,
 706 };
 707
 708 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
 709 {
 710         if (channels > 2) {
 711                 if (!cm->can_multi_ch || !rec->ch)
 712                         return -EINVAL;
 713                 if (rec->fmt != 0x03) /* stereo 16bit only */
 714                         return -EINVAL;
 715         }
 716
 717         if (cm->can_multi_ch) {
 718                 spin_lock_irq(&cm->reg_lock);
 719                 if (channels > 2) {
 720                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 721                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 722                 } else {
 723                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 724                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 725                 }
 726                 if (channels == 8)
 727                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 728                 else
 729                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 730                 if (channels == 6) {
 731                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 732                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 733                 } else {
 734                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 735                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 736                 }
 737                 if (channels == 4)
 738                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 739                 else
 740                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 741                 spin_unlock_irq(&cm->reg_lock);
 742         }
 743         return 0;
 744 }
 745
 746
 747 /*
 748  * prepare playback/capture channel
 749  * channel to be used must have been set in rec->ch.
 750  */
 751 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
 752                                  struct snd_pcm_substream *substream)
 753 {
 754         unsigned int reg, freq, freq_ext, val;
 755         unsigned int period_size;
 756         struct snd_pcm_runtime *runtime = substream->runtime;
 757
 758         rec->fmt = 0;
 759         rec->shift = 0;
 760         if (snd_pcm_format_width(runtime->format) >= 16) {
 761                 rec->fmt |= 0x02;
 762                 if (snd_pcm_format_width(runtime->format) > 16)
 763                         rec->shift++; /* 24/32bit */
 764         }
 765         if (runtime->channels > 1)
 766                 rec->fmt |= 0x01;
 767         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 768                 dev_dbg(cm->card->dev, "cannot set dac channels\n");
 769                 return -EINVAL;
 770         }
 771
 772         rec->offset = runtime->dma_addr;
 773         /* buffer and period sizes in frame */
 774         rec->dma_size = runtime->buffer_size << rec->shift;
 775         period_size = runtime->period_size << rec->shift;
 776         if (runtime->channels > 2) {
 777                 /* multi-channels */
 778                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 779                 period_size = (period_size * runtime->channels) / 2;
 780         }
 781
 782         spin_lock_irq(&cm->reg_lock);
 783
 784         /* set buffer address */
 785         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 786         snd_cmipci_write(cm, reg, rec->offset);
 787         /* program sample counts */
 788         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 789         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 790         snd_cmipci_write_w(cm, reg + 2, period_size - 1);
 791
 792         /* set adc/dac flag */
 793         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 794         if (rec->is_dac)
 795                 cm->ctrl &= ~val;
 796         else
 797                 cm->ctrl |= val;
 798         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 799         /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
 800
 801         /* set sample rate */
 802         freq = 0;
 803         freq_ext = 0;
 804         if (runtime->rate > 48000)
 805                 switch (runtime->rate) {
 806                 case 88200:  freq_ext = CM_CH0_SRATE_88K; break;
 807                 case 96000:  freq_ext = CM_CH0_SRATE_96K; break;
 808                 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
 809                 default:     snd_BUG(); break;
 810                 }
 811         else
 812                 freq = snd_cmipci_rate_freq(runtime->rate);
 813         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 814         if (rec->ch) {
 815                 val &= ~CM_DSFC_MASK;
 816                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 817         } else {
 818                 val &= ~CM_ASFC_MASK;
 819                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 820         }
 821         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 822         dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
 823
 824         /* set format */
 825         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 826         if (rec->ch) {
 827                 val &= ~CM_CH1FMT_MASK;
 828                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 829         } else {
 830                 val &= ~CM_CH0FMT_MASK;
 831                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 832         }
 833         if (cm->can_96k) {
 834                 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
 835                 val |= freq_ext << (rec->ch * 2);
 836         }
 837         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 838         dev_dbg(cm->card->dev, "chformat = %08x\n", val);
 839
 840         if (!rec->is_dac && cm->chip_version) {
 841                 if (runtime->rate > 44100)
 842                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 843                 else
 844                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 845         }
 846
 847         rec->running = 0;
 848         spin_unlock_irq(&cm->reg_lock);
 849
 850         return 0;
 851 }
 852
 853 /*
 854  * PCM trigger/stop
 855  */
 856 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
 857                                   int cmd)
 858 {
 859         unsigned int inthld, chen, reset, pause;
 860         int result = 0;
 861
 862         inthld = CM_CH0_INT_EN << rec->ch;
 863         chen = CM_CHEN0 << rec->ch;
 864         reset = CM_RST_CH0 << rec->ch;
 865         pause = CM_PAUSE0 << rec->ch;
 866
 867         spin_lock(&cm->reg_lock);
 868         switch (cmd) {
 869         case SNDRV_PCM_TRIGGER_START:
 870                 rec->running = 1;
 871                 /* set interrupt */
 872                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 873                 cm->ctrl |= chen;
 874                 /* enable channel */
 875                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 876                 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
 877                 break;
 878         case SNDRV_PCM_TRIGGER_STOP:
 879                 rec->running = 0;
 880                 /* disable interrupt */
 881                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 882                 /* reset */
 883                 cm->ctrl &= ~chen;
 884                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 885                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 886                 rec->needs_silencing = rec->is_dac;
 887                 break;
 888         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 889         case SNDRV_PCM_TRIGGER_SUSPEND:
 890                 cm->ctrl |= pause;
 891                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 892                 break;
 893         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 894         case SNDRV_PCM_TRIGGER_RESUME:
 895                 cm->ctrl &= ~pause;
 896                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 897                 break;
 898         default:
 899                 result = -EINVAL;
 900                 break;
 901         }
 902         spin_unlock(&cm->reg_lock);
 903         return result;
 904 }
 905
 906 /*
 907  * return the current pointer
 908  */
 909 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
 910                                                 struct snd_pcm_substream *substream)
 911 {
 912         size_t ptr;
 913         unsigned int reg, rem, tries;
 914
 915         if (!rec->running)
 916                 return 0;
 917 #if 1 // this seems better..
 918         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 919         for (tries = 0; tries < 3; tries++) {
 920                 rem = snd_cmipci_read_w(cm, reg);
 921                 if (rem < rec->dma_size)
 922                         goto ok;
 923         }
 924         dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
 925         return SNDRV_PCM_POS_XRUN;
 926 ok:
 927         ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
 928 #else
 929         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 930         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 931         ptr = bytes_to_frames(substream->runtime, ptr);
 932 #endif
 933         if (substream->runtime->channels > 2)
 934                 ptr = (ptr * 2) / substream->runtime->channels;
 935         return ptr;
 936 }
 937
 938 /*
 939  * playback
 940  */
 941
 942 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
 943                                        int cmd)
 944 {
 945         struct cmipci *cm = snd_pcm_substream_chip(substream);
 946         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
 947 }
 948
 949 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
 950 {
 951         struct cmipci *cm = snd_pcm_substream_chip(substream);
 952         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 953 }
 954
 955
 956
 957 /*
 958  * capture
 959  */
 960
 961 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
 962                                      int cmd)
 963 {
 964         struct cmipci *cm = snd_pcm_substream_chip(substream);
 965         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
 966 }
 967
 968 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
 969 {
 970         struct cmipci *cm = snd_pcm_substream_chip(substream);
 971         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 972 }
 973
 974
 975 /*
 976  * hw preparation for spdif
 977  */
 978
 979 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
 980                                          struct snd_ctl_elem_info *uinfo)
 981 {
 982         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 983         uinfo->count = 1;
 984         return 0;
 985 }
 986
 987 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
 988                                         struct snd_ctl_elem_value *ucontrol)
 989 {
 990         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
 991         int i;
 992
 993         spin_lock_irq(&chip->reg_lock);
 994         for (i = 0; i < 4; i++)
 995                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
 996         spin_unlock_irq(&chip->reg_lock);
 997         return 0;
 998 }
 999
1000 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1001                                          struct snd_ctl_elem_value *ucontrol)
1002 {
1003         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1004         int i, change;
1005         unsigned int val;
1006
1007         val = 0;
1008         spin_lock_irq(&chip->reg_lock);
1009         for (i = 0; i < 4; i++)
1010                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1011         change = val != chip->dig_status;
1012         chip->dig_status = val;
1013         spin_unlock_irq(&chip->reg_lock);
1014         return change;
1015 }
1016
1017 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1018 {
1019         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1020         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1021         .info =         snd_cmipci_spdif_default_info,
1022         .get =          snd_cmipci_spdif_default_get,
1023         .put =          snd_cmipci_spdif_default_put
1024 };
1025
1026 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1027                                       struct snd_ctl_elem_info *uinfo)
1028 {
1029         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1030         uinfo->count = 1;
1031         return 0;
1032 }
1033
1034 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1035                                      struct snd_ctl_elem_value *ucontrol)
1036 {
1037         ucontrol->value.iec958.status[0] = 0xff;
1038         ucontrol->value.iec958.status[1] = 0xff;
1039         ucontrol->value.iec958.status[2] = 0xff;
1040         ucontrol->value.iec958.status[3] = 0xff;
1041         return 0;
1042 }
1043
1044 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1045 {
1046         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1047         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1048         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1049         .info =         snd_cmipci_spdif_mask_info,
1050         .get =          snd_cmipci_spdif_mask_get,
1051 };
1052
1053 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1054                                         struct snd_ctl_elem_info *uinfo)
1055 {
1056         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1057         uinfo->count = 1;
1058         return 0;
1059 }
1060
1061 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1062                                        struct snd_ctl_elem_value *ucontrol)
1063 {
1064         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1065         int i;
1066
1067         spin_lock_irq(&chip->reg_lock);
1068         for (i = 0; i < 4; i++)
1069                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1070         spin_unlock_irq(&chip->reg_lock);
1071         return 0;
1072 }
1073
1074 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1075                                        struct snd_ctl_elem_value *ucontrol)
1076 {
1077         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1078         int i, change;
1079         unsigned int val;
1080
1081         val = 0;
1082         spin_lock_irq(&chip->reg_lock);
1083         for (i = 0; i < 4; i++)
1084                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1085         change = val != chip->dig_pcm_status;
1086         chip->dig_pcm_status = val;
1087         spin_unlock_irq(&chip->reg_lock);
1088         return change;
1089 }
1090
1091 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1092 {
1093         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1094         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1095         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1096         .info =         snd_cmipci_spdif_stream_info,
1097         .get =          snd_cmipci_spdif_stream_get,
1098         .put =          snd_cmipci_spdif_stream_put
1099 };
1100
1101 /*
1102  */
1103
1104 /* save mixer setting and mute for AC3 playback */
1105 static int save_mixer_state(struct cmipci *cm)
1106 {
1107         if (! cm->mixer_insensitive) {
1108                 struct snd_ctl_elem_value *val;
1109                 unsigned int i;
1110
1111                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1112                 if (!val)
1113                         return -ENOMEM;
1114                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1115                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1116                         if (ctl) {
1117                                 int event;
1118                                 memset(val, 0, sizeof(*val));
1119                                 ctl->get(ctl, val);
1120                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1121                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1122                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1123                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1124                                         ctl->put(ctl, val); /* toggle */
1125                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1126                                 }
1127                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1128                                 snd_ctl_notify(cm->card, event, &ctl->id);
1129                         }
1130                 }
1131                 kfree(val);
1132                 cm->mixer_insensitive = 1;
1133         }
1134         return 0;
1135 }
1136
1137
1138 /* restore the previously saved mixer status */
1139 static void restore_mixer_state(struct cmipci *cm)
1140 {
1141         if (cm->mixer_insensitive) {
1142                 struct snd_ctl_elem_value *val;
1143                 unsigned int i;
1144
1145                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1146                 if (!val)
1147                         return;
1148                 cm->mixer_insensitive = 0; /* at first clear this;
1149                                               otherwise the changes will be ignored */
1150                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1151                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1152                         if (ctl) {
1153                                 int event;
1154
1155                                 memset(val, 0, sizeof(*val));
1156                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1157                                 ctl->get(ctl, val);
1158                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1159                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1160                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1161                                         ctl->put(ctl, val);
1162                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1163                                 }
1164                                 snd_ctl_notify(cm->card, event, &ctl->id);
1165                         }
1166                 }
1167                 kfree(val);
1168         }
1169 }
1170
1171 /* spinlock held! */
1172 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1173 {
1174         if (do_ac3) {
1175                 /* AC3EN for 037 */
1176                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1177                 /* AC3EN for 039 */
1178                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1179
1180                 if (cm->can_ac3_hw) {
1181                         /* SPD24SEL for 037, 0x02 */
1182                         /* SPD24SEL for 039, 0x20, but cannot be set */
1183                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1184                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1185                 } else { /* can_ac3_sw */
1186                         /* SPD32SEL for 037 & 039, 0x20 */
1187                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1188                         /* set 176K sample rate to fix 033 HW bug */
1189                         if (cm->chip_version == 33) {
1190                                 if (rate >= 48000) {
1191                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1192                                 } else {
1193                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1194                                 }
1195                         }
1196                 }
1197
1198         } else {
1199                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1200                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1201
1202                 if (cm->can_ac3_hw) {
1203                         /* chip model >= 37 */
1204                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1205                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1206                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1207                         } else {
1208                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1209                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1210                         }
1211                 } else {
1212                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1213                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1214                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1215                 }
1216         }
1217 }
1218
1219 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1220 {
1221         int rate, err;
1222
1223         rate = subs->runtime->rate;
1224
1225         if (up && do_ac3) {
1226                 err = save_mixer_state(cm);
1227                 if (err < 0)
1228                         return err;
1229         }
1230
1231         spin_lock_irq(&cm->reg_lock);
1232         cm->spdif_playback_avail = up;
1233         if (up) {
1234                 /* they are controlled via "IEC958 Output Switch" */
1235                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1236                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1237                 if (cm->spdif_playback_enabled)
1238                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1239                 setup_ac3(cm, subs, do_ac3, rate);
1240
1241                 if (rate == 48000 || rate == 96000)
1242                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1243                 else
1244                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1245                 if (rate > 48000)
1246                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1247                 else
1248                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1249         } else {
1250                 /* they are controlled via "IEC958 Output Switch" */
1251                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1252                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1253                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1254                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1255                 setup_ac3(cm, subs, 0, 0);
1256         }
1257         spin_unlock_irq(&cm->reg_lock);
1258         return 0;
1259 }
1260
1261
1262 /*
1263  * preparation
1264  */
1265
1266 /* playback - enable spdif only on the certain condition */
1267 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1268 {
1269         struct cmipci *cm = snd_pcm_substream_chip(substream);
1270         int rate = substream->runtime->rate;
1271         int err, do_spdif, do_ac3 = 0;
1272
1273         do_spdif = (rate >= 44100 && rate <= 96000 &&
1274                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1275                     substream->runtime->channels == 2);
1276         if (do_spdif && cm->can_ac3_hw)
1277                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1278         err = setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1279         if (err < 0)
1280                 return err;
1281         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1282 }
1283
1284 /* playback  (via device #2) - enable spdif always */
1285 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1286 {
1287         struct cmipci *cm = snd_pcm_substream_chip(substream);
1288         int err, do_ac3;
1289
1290         if (cm->can_ac3_hw)
1291                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1292         else
1293                 do_ac3 = 1; /* doesn't matter */
1294         err = setup_spdif_playback(cm, substream, 1, do_ac3);
1295         if (err < 0)
1296                 return err;
1297         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1298 }
1299
1300 /*
1301  * Apparently, the samples last played on channel A stay in some buffer, even
1302  * after the channel is reset, and get added to the data for the rear DACs when
1303  * playing a multichannel stream on channel B.  This is likely to generate
1304  * wraparounds and thus distortions.
1305  * To avoid this, we play at least one zero sample after the actual stream has
1306  * stopped.
1307  */
1308 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1309 {
1310         struct snd_pcm_runtime *runtime = rec->substream->runtime;
1311         unsigned int reg, val;
1312
1313         if (rec->needs_silencing && runtime && runtime->dma_area) {
1314                 /* set up a small silence buffer */
1315                 memset(runtime->dma_area, 0, PAGE_SIZE);
1316                 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1317                 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1318                 snd_cmipci_write(cm, reg, val);
1319
1320                 /* configure for 16 bits, 2 channels, 8 kHz */
1321                 if (runtime->channels > 2)
1322                         set_dac_channels(cm, rec, 2);
1323                 spin_lock_irq(&cm->reg_lock);
1324                 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1325                 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1326                 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1327                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1328                 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1329                 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1330                 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1331                 if (cm->can_96k)
1332                         val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1333                 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1334
1335                 /* start stream (we don't need interrupts) */
1336                 cm->ctrl |= CM_CHEN0 << rec->ch;
1337                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1338                 spin_unlock_irq(&cm->reg_lock);
1339
1340                 msleep(1);
1341
1342                 /* stop and reset stream */
1343                 spin_lock_irq(&cm->reg_lock);
1344                 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1345                 val = CM_RST_CH0 << rec->ch;
1346                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1347                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1348                 spin_unlock_irq(&cm->reg_lock);
1349
1350                 rec->needs_silencing = 0;
1351         }
1352 }
1353
1354 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1355 {
1356         struct cmipci *cm = snd_pcm_substream_chip(substream);
1357         setup_spdif_playback(cm, substream, 0, 0);
1358         restore_mixer_state(cm);
1359         snd_cmipci_silence_hack(cm, &cm->channel[0]);
1360         return 0;
1361 }
1362
1363 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1364 {
1365         struct cmipci *cm = snd_pcm_substream_chip(substream);
1366         snd_cmipci_silence_hack(cm, &cm->channel[1]);
1367         return 0;
1368 }
1369
1370 /* capture */
1371 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1372 {
1373         struct cmipci *cm = snd_pcm_substream_chip(substream);
1374         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1375 }
1376
1377 /* capture with spdif (via device #2) */
1378 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1379 {
1380         struct cmipci *cm = snd_pcm_substream_chip(substream);
1381
1382         spin_lock_irq(&cm->reg_lock);
1383         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1384         if (cm->can_96k) {
1385                 if (substream->runtime->rate > 48000)
1386                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1387                 else
1388                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1389         }
1390         if (snd_pcm_format_width(substream->runtime->format) > 16)
1391                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1392         else
1393                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1394
1395         spin_unlock_irq(&cm->reg_lock);
1396
1397         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1398 }
1399
1400 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1401 {
1402         struct cmipci *cm = snd_pcm_substream_chip(subs);
1403
1404         spin_lock_irq(&cm->reg_lock);
1405         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1406         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1407         spin_unlock_irq(&cm->reg_lock);
1408
1409         return 0;
1410 }
1411
1412
1413 /*
1414  * interrupt handler
1415  */
1416 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1417 {
1418         struct cmipci *cm = dev_id;
1419         unsigned int status, mask = 0;
1420
1421         /* fastpath out, to ease interrupt sharing */
1422         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1423         if (!(status & CM_INTR))
1424                 return IRQ_NONE;
1425
1426         /* acknowledge interrupt */
1427         spin_lock(&cm->reg_lock);
1428         if (status & CM_CHINT0)
1429                 mask |= CM_CH0_INT_EN;
1430         if (status & CM_CHINT1)
1431                 mask |= CM_CH1_INT_EN;
1432         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1433         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1434         spin_unlock(&cm->reg_lock);
1435
1436         if (cm->rmidi && (status & CM_UARTINT))
1437                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1438
1439         if (cm->pcm) {
1440                 if ((status & CM_CHINT0) && cm->channel[0].running)
1441                         snd_pcm_period_elapsed(cm->channel[0].substream);
1442                 if ((status & CM_CHINT1) && cm->channel[1].running)
1443                         snd_pcm_period_elapsed(cm->channel[1].substream);
1444         }
1445         return IRQ_HANDLED;
1446 }
1447
1448 /*
1449  * h/w infos
1450  */
1451
1452 /* playback on channel A */
1453 static const struct snd_pcm_hardware snd_cmipci_playback =
1454 {
1455         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1456                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1457                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1458         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1459         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1460         .rate_min =             5512,
1461         .rate_max =             48000,
1462         .channels_min =         1,
1463         .channels_max =         2,
1464         .buffer_bytes_max =     (128*1024),
1465         .period_bytes_min =     64,
1466         .period_bytes_max =     (128*1024),
1467         .periods_min =          2,
1468         .periods_max =          1024,
1469         .fifo_size =            0,
1470 };
1471
1472 /* capture on channel B */
1473 static const struct snd_pcm_hardware snd_cmipci_capture =
1474 {
1475         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1476                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1477                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1478         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1479         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1480         .rate_min =             5512,
1481         .rate_max =             48000,
1482         .channels_min =         1,
1483         .channels_max =         2,
1484         .buffer_bytes_max =     (128*1024),
1485         .period_bytes_min =     64,
1486         .period_bytes_max =     (128*1024),
1487         .periods_min =          2,
1488         .periods_max =          1024,
1489         .fifo_size =            0,
1490 };
1491
1492 /* playback on channel B - stereo 16bit only? */
1493 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1494 {
1495         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1496                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1497                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1498         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1499         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1500         .rate_min =             5512,
1501         .rate_max =             48000,
1502         .channels_min =         2,
1503         .channels_max =         2,
1504         .buffer_bytes_max =     (128*1024),
1505         .period_bytes_min =     64,
1506         .period_bytes_max =     (128*1024),
1507         .periods_min =          2,
1508         .periods_max =          1024,
1509         .fifo_size =            0,
1510 };
1511
1512 /* spdif playback on channel A */
1513 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1514 {
1515         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1516                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1517                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1518         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1519         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1520         .rate_min =             44100,
1521         .rate_max =             48000,
1522         .channels_min =         2,
1523         .channels_max =         2,
1524         .buffer_bytes_max =     (128*1024),
1525         .period_bytes_min =     64,
1526         .period_bytes_max =     (128*1024),
1527         .periods_min =          2,
1528         .periods_max =          1024,
1529         .fifo_size =            0,
1530 };
1531
1532 /* spdif playback on channel A (32bit, IEC958 subframes) */
1533 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1534 {
1535         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1536                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1537                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1538         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1539         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1540         .rate_min =             44100,
1541         .rate_max =             48000,
1542         .channels_min =         2,
1543         .channels_max =         2,
1544         .buffer_bytes_max =     (128*1024),
1545         .period_bytes_min =     64,
1546         .period_bytes_max =     (128*1024),
1547         .periods_min =          2,
1548         .periods_max =          1024,
1549         .fifo_size =            0,
1550 };
1551
1552 /* spdif capture on channel B */
1553 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1554 {
1555         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1556                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1557                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1558         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
1559                                 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1560         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1561         .rate_min =             44100,
1562         .rate_max =             48000,
1563         .channels_min =         2,
1564         .channels_max =         2,
1565         .buffer_bytes_max =     (128*1024),
1566         .period_bytes_min =     64,
1567         .period_bytes_max =     (128*1024),
1568         .periods_min =          2,
1569         .periods_max =          1024,
1570         .fifo_size =            0,
1571 };
1572
1573 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1574                         32000, 44100, 48000, 88200, 96000, 128000 };
1575 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1576                 .count = ARRAY_SIZE(rate_constraints),
1577                 .list = rate_constraints,
1578                 .mask = 0,
1579 };
1580
1581 /*
1582  * check device open/close
1583  */
1584 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1585 {
1586         int ch = mode & CM_OPEN_CH_MASK;
1587
1588         /* FIXME: a file should wait until the device becomes free
1589          * when it's opened on blocking mode.  however, since the current
1590          * pcm framework doesn't pass file pointer before actually opened,
1591          * we can't know whether blocking mode or not in open callback..
1592          */
1593         mutex_lock(&cm->open_mutex);
1594         if (cm->opened[ch]) {
1595                 mutex_unlock(&cm->open_mutex);
1596                 return -EBUSY;
1597         }
1598         cm->opened[ch] = mode;
1599         cm->channel[ch].substream = subs;
1600         if (! (mode & CM_OPEN_DAC)) {
1601                 /* disable dual DAC mode */
1602                 cm->channel[ch].is_dac = 0;
1603                 spin_lock_irq(&cm->reg_lock);
1604                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1605                 spin_unlock_irq(&cm->reg_lock);
1606         }
1607         mutex_unlock(&cm->open_mutex);
1608         return 0;
1609 }
1610
1611 static void close_device_check(struct cmipci *cm, int mode)
1612 {
1613         int ch = mode & CM_OPEN_CH_MASK;
1614
1615         mutex_lock(&cm->open_mutex);
1616         if (cm->opened[ch] == mode) {
1617                 if (cm->channel[ch].substream) {
1618                         snd_cmipci_ch_reset(cm, ch);
1619                         cm->channel[ch].running = 0;
1620                         cm->channel[ch].substream = NULL;
1621                 }
1622                 cm->opened[ch] = 0;
1623                 if (! cm->channel[ch].is_dac) {
1624                         /* enable dual DAC mode again */
1625                         cm->channel[ch].is_dac = 1;
1626                         spin_lock_irq(&cm->reg_lock);
1627                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1628                         spin_unlock_irq(&cm->reg_lock);
1629                 }
1630         }
1631         mutex_unlock(&cm->open_mutex);
1632 }
1633
1634 /*
1635  */
1636
1637 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1638 {
1639         struct cmipci *cm = snd_pcm_substream_chip(substream);
1640         struct snd_pcm_runtime *runtime = substream->runtime;
1641         int err;
1642
1643         err = open_device_check(cm, CM_OPEN_PLAYBACK, substream);
1644         if (err < 0)
1645                 return err;
1646         runtime->hw = snd_cmipci_playback;
1647         if (cm->chip_version == 68) {
1648                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1649                                      SNDRV_PCM_RATE_96000;
1650                 runtime->hw.rate_max = 96000;
1651         } else if (cm->chip_version == 55) {
1652                 err = snd_pcm_hw_constraint_list(runtime, 0,
1653                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1654                 if (err < 0)
1655                         return err;
1656                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1657                 runtime->hw.rate_max = 128000;
1658         }
1659         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1660         cm->dig_pcm_status = cm->dig_status;
1661         return 0;
1662 }
1663
1664 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1665 {
1666         struct cmipci *cm = snd_pcm_substream_chip(substream);
1667         struct snd_pcm_runtime *runtime = substream->runtime;
1668         int err;
1669
1670         err = open_device_check(cm, CM_OPEN_CAPTURE, substream);
1671         if (err < 0)
1672                 return err;
1673         runtime->hw = snd_cmipci_capture;
1674         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1675                 runtime->hw.rate_min = 41000;
1676                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1677         } else if (cm->chip_version == 55) {
1678                 err = snd_pcm_hw_constraint_list(runtime, 0,
1679                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1680                 if (err < 0)
1681                         return err;
1682                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1683                 runtime->hw.rate_max = 128000;
1684         }
1685         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1686         return 0;
1687 }
1688
1689 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1690 {
1691         struct cmipci *cm = snd_pcm_substream_chip(substream);
1692         struct snd_pcm_runtime *runtime = substream->runtime;
1693         int err;
1694
1695         /* use channel B */
1696         err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream);
1697         if (err < 0)
1698                 return err;
1699         runtime->hw = snd_cmipci_playback2;
1700         mutex_lock(&cm->open_mutex);
1701         if (! cm->opened[CM_CH_PLAY]) {
1702                 if (cm->can_multi_ch) {
1703                         runtime->hw.channels_max = cm->max_channels;
1704                         if (cm->max_channels == 4)
1705                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1706                         else if (cm->max_channels == 6)
1707                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1708                         else if (cm->max_channels == 8)
1709                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1710                 }
1711         }
1712         mutex_unlock(&cm->open_mutex);
1713         if (cm->chip_version == 68) {
1714                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1715                                      SNDRV_PCM_RATE_96000;
1716                 runtime->hw.rate_max = 96000;
1717         } else if (cm->chip_version == 55) {
1718                 err = snd_pcm_hw_constraint_list(runtime, 0,
1719                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1720                 if (err < 0)
1721                         return err;
1722                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1723                 runtime->hw.rate_max = 128000;
1724         }
1725         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1726         return 0;
1727 }
1728
1729 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1730 {
1731         struct cmipci *cm = snd_pcm_substream_chip(substream);
1732         struct snd_pcm_runtime *runtime = substream->runtime;
1733         int err;
1734
1735         /* use channel A */
1736         err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream);
1737         if (err < 0)
1738                 return err;
1739         if (cm->can_ac3_hw) {
1740                 runtime->hw = snd_cmipci_playback_spdif;
1741                 if (cm->chip_version >= 37) {
1742                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1743                         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1744                 }
1745                 if (cm->can_96k) {
1746                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1747                                              SNDRV_PCM_RATE_96000;
1748                         runtime->hw.rate_max = 96000;
1749                 }
1750         } else {
1751                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1752         }
1753         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1754         cm->dig_pcm_status = cm->dig_status;
1755         return 0;
1756 }
1757
1758 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1759 {
1760         struct cmipci *cm = snd_pcm_substream_chip(substream);
1761         struct snd_pcm_runtime *runtime = substream->runtime;
1762         int err;
1763
1764         /* use channel B */
1765         err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream);
1766         if (err < 0)
1767                 return err;
1768         runtime->hw = snd_cmipci_capture_spdif;
1769         if (cm->can_96k && !(cm->chip_version == 68)) {
1770                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1771                                      SNDRV_PCM_RATE_96000;
1772                 runtime->hw.rate_max = 96000;
1773         }
1774         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1775         return 0;
1776 }
1777
1778
1779 /*
1780  */
1781
1782 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1783 {
1784         struct cmipci *cm = snd_pcm_substream_chip(substream);
1785         close_device_check(cm, CM_OPEN_PLAYBACK);
1786         return 0;
1787 }
1788
1789 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1790 {
1791         struct cmipci *cm = snd_pcm_substream_chip(substream);
1792         close_device_check(cm, CM_OPEN_CAPTURE);
1793         return 0;
1794 }
1795
1796 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1797 {
1798         struct cmipci *cm = snd_pcm_substream_chip(substream);
1799         close_device_check(cm, CM_OPEN_PLAYBACK2);
1800         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1801         return 0;
1802 }
1803
1804 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1805 {
1806         struct cmipci *cm = snd_pcm_substream_chip(substream);
1807         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1808         return 0;
1809 }
1810
1811 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1812 {
1813         struct cmipci *cm = snd_pcm_substream_chip(substream);
1814         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1815         return 0;
1816 }
1817
1818
1819 /*
1820  */
1821
1822 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1823         .open =         snd_cmipci_playback_open,
1824         .close =        snd_cmipci_playback_close,
1825         .hw_free =      snd_cmipci_playback_hw_free,
1826         .prepare =      snd_cmipci_playback_prepare,
1827         .trigger =      snd_cmipci_playback_trigger,
1828         .pointer =      snd_cmipci_playback_pointer,
1829 };
1830
1831 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1832         .open =         snd_cmipci_capture_open,
1833         .close =        snd_cmipci_capture_close,
1834         .prepare =      snd_cmipci_capture_prepare,
1835         .trigger =      snd_cmipci_capture_trigger,
1836         .pointer =      snd_cmipci_capture_pointer,
1837 };
1838
1839 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1840         .open =         snd_cmipci_playback2_open,
1841         .close =        snd_cmipci_playback2_close,
1842         .hw_params =    snd_cmipci_playback2_hw_params,
1843         .hw_free =      snd_cmipci_playback2_hw_free,
1844         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1845         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1846         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1847 };
1848
1849 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1850         .open =         snd_cmipci_playback_spdif_open,
1851         .close =        snd_cmipci_playback_spdif_close,
1852         .hw_free =      snd_cmipci_playback_hw_free,
1853         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1854         .trigger =      snd_cmipci_playback_trigger,
1855         .pointer =      snd_cmipci_playback_pointer,
1856 };
1857
1858 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1859         .open =         snd_cmipci_capture_spdif_open,
1860         .close =        snd_cmipci_capture_spdif_close,
1861         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1862         .prepare =      snd_cmipci_capture_spdif_prepare,
1863         .trigger =      snd_cmipci_capture_trigger,
1864         .pointer =      snd_cmipci_capture_pointer,
1865 };
1866
1867
1868 /*
1869  */
1870
1871 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1872 {
1873         struct snd_pcm *pcm;
1874         int err;
1875
1876         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1877         if (err < 0)
1878                 return err;
1879
1880         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1881         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1882
1883         pcm->private_data = cm;
1884         pcm->info_flags = 0;
1885         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1886         cm->pcm = pcm;
1887
1888         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1889                                        &cm->pci->dev, 64*1024, 128*1024);
1890
1891         return 0;
1892 }
1893
1894 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1895 {
1896         struct snd_pcm *pcm;
1897         int err;
1898
1899         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1900         if (err < 0)
1901                 return err;
1902
1903         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1904
1905         pcm->private_data = cm;
1906         pcm->info_flags = 0;
1907         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1908         cm->pcm2 = pcm;
1909
1910         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1911                                        &cm->pci->dev, 64*1024, 128*1024);
1912
1913         return 0;
1914 }
1915
1916 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1917 {
1918         struct snd_pcm *pcm;
1919         int err;
1920
1921         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1922         if (err < 0)
1923                 return err;
1924
1925         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1926         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1927
1928         pcm->private_data = cm;
1929         pcm->info_flags = 0;
1930         strcpy(pcm->name, "C-Media PCI IEC958");
1931         cm->pcm_spdif = pcm;
1932
1933         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1934                                        &cm->pci->dev, 64*1024, 128*1024);
1935
1936         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1937                                      snd_pcm_alt_chmaps, cm->max_channels, 0,
1938                                      NULL);
1939         if (err < 0)
1940                 return err;
1941
1942         return 0;
1943 }
1944
1945 /*
1946  * mixer interface:
1947  * - CM8338/8738 has a compatible mixer interface with SB16, but
1948  *   lack of some elements like tone control, i/o gain and AGC.
1949  * - Access to native registers:
1950  *   - A 3D switch
1951  *   - Output mute switches
1952  */
1953
1954 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1955 {
1956         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1957         outb(data, s->iobase + CM_REG_SB16_DATA);
1958 }
1959
1960 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1961 {
1962         unsigned char v;
1963
1964         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1965         v = inb(s->iobase + CM_REG_SB16_DATA);
1966         return v;
1967 }
1968
1969 /*
1970  * general mixer element
1971  */
1972 struct cmipci_sb_reg {
1973         unsigned int left_reg, right_reg;
1974         unsigned int left_shift, right_shift;
1975         unsigned int mask;
1976         unsigned int invert: 1;
1977         unsigned int stereo: 1;
1978 };
1979
1980 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1981  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1982
1983 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1984 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1985   .info = snd_cmipci_info_volume, \
1986   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1987   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1988 }
1989
1990 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1991 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1992 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1993 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1994
1995 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1996 {
1997         r->left_reg = val & 0xff;
1998         r->right_reg = (val >> 8) & 0xff;
1999         r->left_shift = (val >> 16) & 0x07;
2000         r->right_shift = (val >> 19) & 0x07;
2001         r->invert = (val >> 22) & 1;
2002         r->stereo = (val >> 23) & 1;
2003         r->mask = (val >> 24) & 0xff;
2004 }
2005
2006 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2007                                   struct snd_ctl_elem_info *uinfo)
2008 {
2009         struct cmipci_sb_reg reg;
2010
2011         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2012         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2013         uinfo->count = reg.stereo + 1;
2014         uinfo->value.integer.min = 0;
2015         uinfo->value.integer.max = reg.mask;
2016         return 0;
2017 }
2018
2019 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2020                                  struct snd_ctl_elem_value *ucontrol)
2021 {
2022         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2023         struct cmipci_sb_reg reg;
2024         int val;
2025
2026         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2027         spin_lock_irq(&cm->reg_lock);
2028         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2029         if (reg.invert)
2030                 val = reg.mask - val;
2031         ucontrol->value.integer.value[0] = val;
2032         if (reg.stereo) {
2033                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2034                 if (reg.invert)
2035                         val = reg.mask - val;
2036                 ucontrol->value.integer.value[1] = val;
2037         }
2038         spin_unlock_irq(&cm->reg_lock);
2039         return 0;
2040 }
2041
2042 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2043                                  struct snd_ctl_elem_value *ucontrol)
2044 {
2045         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2046         struct cmipci_sb_reg reg;
2047         int change;
2048         int left, right, oleft, oright;
2049
2050         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2051         left = ucontrol->value.integer.value[0] & reg.mask;
2052         if (reg.invert)
2053                 left = reg.mask - left;
2054         left <<= reg.left_shift;
2055         if (reg.stereo) {
2056                 right = ucontrol->value.integer.value[1] & reg.mask;
2057                 if (reg.invert)
2058                         right = reg.mask - right;
2059                 right <<= reg.right_shift;
2060         } else
2061                 right = 0;
2062         spin_lock_irq(&cm->reg_lock);
2063         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2064         left |= oleft & ~(reg.mask << reg.left_shift);
2065         change = left != oleft;
2066         if (reg.stereo) {
2067                 if (reg.left_reg != reg.right_reg) {
2068                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
2069                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2070                 } else
2071                         oright = left;
2072                 right |= oright & ~(reg.mask << reg.right_shift);
2073                 change |= right != oright;
2074                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2075         } else
2076                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2077         spin_unlock_irq(&cm->reg_lock);
2078         return change;
2079 }
2080
2081 /*
2082  * input route (left,right) -> (left,right)
2083  */
2084 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2085 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2086   .info = snd_cmipci_info_input_sw, \
2087   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2088   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2089 }
2090
2091 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2092                                     struct snd_ctl_elem_info *uinfo)
2093 {
2094         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2095         uinfo->count = 4;
2096         uinfo->value.integer.min = 0;
2097         uinfo->value.integer.max = 1;
2098         return 0;
2099 }
2100
2101 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2102                                    struct snd_ctl_elem_value *ucontrol)
2103 {
2104         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2105         struct cmipci_sb_reg reg;
2106         int val1, val2;
2107
2108         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2109         spin_lock_irq(&cm->reg_lock);
2110         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2111         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2112         spin_unlock_irq(&cm->reg_lock);
2113         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2114         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2115         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2116         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2117         return 0;
2118 }
2119
2120 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2121                                    struct snd_ctl_elem_value *ucontrol)
2122 {
2123         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2124         struct cmipci_sb_reg reg;
2125         int change;
2126         int val1, val2, oval1, oval2;
2127
2128         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2129         spin_lock_irq(&cm->reg_lock);
2130         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2131         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2132         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2133         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2134         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2135         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2136         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2137         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2138         change = val1 != oval1 || val2 != oval2;
2139         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2140         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2141         spin_unlock_irq(&cm->reg_lock);
2142         return change;
2143 }
2144
2145 /*
2146  * native mixer switches/volumes
2147  */
2148
2149 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2150 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2151   .info = snd_cmipci_info_native_mixer, \
2152   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2153   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2154 }
2155
2156 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2157 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2158   .info = snd_cmipci_info_native_mixer, \
2159   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2160   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2161 }
2162
2163 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2164 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2165   .info = snd_cmipci_info_native_mixer, \
2166   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2167   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2168 }
2169
2170 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2171 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2172   .info = snd_cmipci_info_native_mixer, \
2173   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2174   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2175 }
2176
2177 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2178                                         struct snd_ctl_elem_info *uinfo)
2179 {
2180         struct cmipci_sb_reg reg;
2181
2182         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2183         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2184         uinfo->count = reg.stereo + 1;
2185         uinfo->value.integer.min = 0;
2186         uinfo->value.integer.max = reg.mask;
2187         return 0;
2188
2189 }
2190
2191 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2192                                        struct snd_ctl_elem_value *ucontrol)
2193 {
2194         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2195         struct cmipci_sb_reg reg;
2196         unsigned char oreg, val;
2197
2198         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2199         spin_lock_irq(&cm->reg_lock);
2200         oreg = inb(cm->iobase + reg.left_reg);
2201         val = (oreg >> reg.left_shift) & reg.mask;
2202         if (reg.invert)
2203                 val = reg.mask - val;
2204         ucontrol->value.integer.value[0] = val;
2205         if (reg.stereo) {
2206                 val = (oreg >> reg.right_shift) & reg.mask;
2207                 if (reg.invert)
2208                         val = reg.mask - val;
2209                 ucontrol->value.integer.value[1] = val;
2210         }
2211         spin_unlock_irq(&cm->reg_lock);
2212         return 0;
2213 }
2214
2215 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2216                                        struct snd_ctl_elem_value *ucontrol)
2217 {
2218         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2219         struct cmipci_sb_reg reg;
2220         unsigned char oreg, nreg, val;
2221
2222         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2223         spin_lock_irq(&cm->reg_lock);
2224         oreg = inb(cm->iobase + reg.left_reg);
2225         val = ucontrol->value.integer.value[0] & reg.mask;
2226         if (reg.invert)
2227                 val = reg.mask - val;
2228         nreg = oreg & ~(reg.mask << reg.left_shift);
2229         nreg |= (val << reg.left_shift);
2230         if (reg.stereo) {
2231                 val = ucontrol->value.integer.value[1] & reg.mask;
2232                 if (reg.invert)
2233                         val = reg.mask - val;
2234                 nreg &= ~(reg.mask << reg.right_shift);
2235                 nreg |= (val << reg.right_shift);
2236         }
2237         outb(nreg, cm->iobase + reg.left_reg);
2238         spin_unlock_irq(&cm->reg_lock);
2239         return (nreg != oreg);
2240 }
2241
2242 /*
2243  * special case - check mixer sensitivity
2244  */
2245 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2246                                                  struct snd_ctl_elem_value *ucontrol)
2247 {
2248         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2249         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2250 }
2251
2252 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2253                                                  struct snd_ctl_elem_value *ucontrol)
2254 {
2255         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2256         if (cm->mixer_insensitive) {
2257                 /* ignored */
2258                 return 0;
2259         }
2260         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2261 }
2262
2263
2264 static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2265         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2266         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2267         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2268         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2269         { /* switch with sensitivity */
2270                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271                 .name = "PCM Playback Switch",
2272                 .info = snd_cmipci_info_native_mixer,
2273                 .get = snd_cmipci_get_native_mixer_sensitive,
2274                 .put = snd_cmipci_put_native_mixer_sensitive,
2275                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2276         },
2277         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2278         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2279         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2280         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2281         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2282         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2283         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2284         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2285         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2286         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2287         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2288         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2289         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2290         CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2291         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2292         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2293         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2294         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2295         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2296         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2297         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2298         CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2299         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2300 };
2301
2302 /*
2303  * other switches
2304  */
2305
2306 struct cmipci_switch_args {
2307         int reg;                /* register index */
2308         unsigned int mask;      /* mask bits */
2309         unsigned int mask_on;   /* mask bits to turn on */
2310         unsigned int is_byte: 1;                /* byte access? */
2311         unsigned int ac3_sensitive: 1;  /* access forbidden during
2312                                          * non-audio operation?
2313                                          */
2314 };
2315
2316 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2317
2318 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2319                                    struct snd_ctl_elem_value *ucontrol,
2320                                    struct cmipci_switch_args *args)
2321 {
2322         unsigned int val;
2323         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2324
2325         spin_lock_irq(&cm->reg_lock);
2326         if (args->ac3_sensitive && cm->mixer_insensitive) {
2327                 ucontrol->value.integer.value[0] = 0;
2328                 spin_unlock_irq(&cm->reg_lock);
2329                 return 0;
2330         }
2331         if (args->is_byte)
2332                 val = inb(cm->iobase + args->reg);
2333         else
2334                 val = snd_cmipci_read(cm, args->reg);
2335         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2336         spin_unlock_irq(&cm->reg_lock);
2337         return 0;
2338 }
2339
2340 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2341                                   struct snd_ctl_elem_value *ucontrol)
2342 {
2343         struct cmipci_switch_args *args;
2344         args = (struct cmipci_switch_args *)kcontrol->private_value;
2345         if (snd_BUG_ON(!args))
2346                 return -EINVAL;
2347         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2348 }
2349
2350 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2351                                    struct snd_ctl_elem_value *ucontrol,
2352                                    struct cmipci_switch_args *args)
2353 {
2354         unsigned int val;
2355         int change;
2356         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2357
2358         spin_lock_irq(&cm->reg_lock);
2359         if (args->ac3_sensitive && cm->mixer_insensitive) {
2360                 /* ignored */
2361                 spin_unlock_irq(&cm->reg_lock);
2362                 return 0;
2363         }
2364         if (args->is_byte)
2365                 val = inb(cm->iobase + args->reg);
2366         else
2367                 val = snd_cmipci_read(cm, args->reg);
2368         change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2369                         args->mask_on : (args->mask & ~args->mask_on));
2370         if (change) {
2371                 val &= ~args->mask;
2372                 if (ucontrol->value.integer.value[0])
2373                         val |= args->mask_on;
2374                 else
2375                         val |= (args->mask & ~args->mask_on);
2376                 if (args->is_byte)
2377                         outb((unsigned char)val, cm->iobase + args->reg);
2378                 else
2379                         snd_cmipci_write(cm, args->reg, val);
2380         }
2381         spin_unlock_irq(&cm->reg_lock);
2382         return change;
2383 }
2384
2385 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2386                                   struct snd_ctl_elem_value *ucontrol)
2387 {
2388         struct cmipci_switch_args *args;
2389         args = (struct cmipci_switch_args *)kcontrol->private_value;
2390         if (snd_BUG_ON(!args))
2391                 return -EINVAL;
2392         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2393 }
2394
2395 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2396 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2397   .reg = xreg, \
2398   .mask = xmask, \
2399   .mask_on = xmask_on, \
2400   .is_byte = xis_byte, \
2401   .ac3_sensitive = xac3, \
2402 }
2403
2404 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2405         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2406
2407 #if 0 /* these will be controlled in pcm device */
2408 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2409 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2410 #endif
2411 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2412 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2413 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2414 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2415 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2416 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2417 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2418 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2419 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2420 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2421 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2422 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2423 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2424 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2425 #if CM_CH_PLAY == 1
2426 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2427 #else
2428 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2429 #endif
2430 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2431 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2432 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2433 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2434 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2435
2436 #define DEFINE_SWITCH(sname, stype, sarg) \
2437 { .name = sname, \
2438   .iface = stype, \
2439   .info = snd_cmipci_uswitch_info, \
2440   .get = snd_cmipci_uswitch_get, \
2441   .put = snd_cmipci_uswitch_put, \
2442   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2443 }
2444
2445 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2446 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2447
2448
2449 /*
2450  * callbacks for spdif output switch
2451  * needs toggle two registers..
2452  */
2453 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2454                                         struct snd_ctl_elem_value *ucontrol)
2455 {
2456         int changed;
2457         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2458         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2459         return changed;
2460 }
2461
2462 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2463                                         struct snd_ctl_elem_value *ucontrol)
2464 {
2465         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2466         int changed;
2467         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2468         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2469         if (changed) {
2470                 if (ucontrol->value.integer.value[0]) {
2471                         if (chip->spdif_playback_avail)
2472                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2473                 } else {
2474                         if (chip->spdif_playback_avail)
2475                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2476                 }
2477         }
2478         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2479         return changed;
2480 }
2481
2482
2483 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2484                                         struct snd_ctl_elem_info *uinfo)
2485 {
2486         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2487         static const char *const texts[3] = {
2488                 "Line-In", "Rear Output", "Bass Output"
2489         };
2490
2491         return snd_ctl_enum_info(uinfo, 1,
2492                                  cm->chip_version >= 39 ? 3 : 2, texts);
2493 }
2494
2495 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2496 {
2497         unsigned int val;
2498         if (cm->chip_version >= 39) {
2499                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2500                 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2501                         return 2;
2502         }
2503         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2504         if (val & CM_REAR2LIN)
2505                 return 1;
2506         return 0;
2507 }
2508
2509 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2510                                        struct snd_ctl_elem_value *ucontrol)
2511 {
2512         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2513
2514         spin_lock_irq(&cm->reg_lock);
2515         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2516         spin_unlock_irq(&cm->reg_lock);
2517         return 0;
2518 }
2519
2520 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2521                                        struct snd_ctl_elem_value *ucontrol)
2522 {
2523         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2524         int change;
2525
2526         spin_lock_irq(&cm->reg_lock);
2527         if (ucontrol->value.enumerated.item[0] == 2)
2528                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2529         else
2530                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2531         if (ucontrol->value.enumerated.item[0] == 1)
2532                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2533         else
2534                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2535         spin_unlock_irq(&cm->reg_lock);
2536         return change;
2537 }
2538
2539 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2540                                        struct snd_ctl_elem_info *uinfo)
2541 {
2542         static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2543
2544         return snd_ctl_enum_info(uinfo, 1, 2, texts);
2545 }
2546
2547 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2548                                       struct snd_ctl_elem_value *ucontrol)
2549 {
2550         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2551         /* same bit as spdi_phase */
2552         spin_lock_irq(&cm->reg_lock);
2553         ucontrol->value.enumerated.item[0] =
2554                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2555         spin_unlock_irq(&cm->reg_lock);
2556         return 0;
2557 }
2558
2559 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2560                                       struct snd_ctl_elem_value *ucontrol)
2561 {
2562         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2563         int change;
2564
2565         spin_lock_irq(&cm->reg_lock);
2566         if (ucontrol->value.enumerated.item[0])
2567                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2568         else
2569                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2570         spin_unlock_irq(&cm->reg_lock);
2571         return change;
2572 }
2573
2574 /* both for CM8338/8738 */
2575 static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2576         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2577         {
2578                 .name = "Line-In Mode",
2579                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2580                 .info = snd_cmipci_line_in_mode_info,
2581                 .get = snd_cmipci_line_in_mode_get,
2582                 .put = snd_cmipci_line_in_mode_put,
2583         },
2584 };
2585
2586 /* for non-multichannel chips */
2587 static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2588 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2589
2590 /* only for CM8738 */
2591 static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2592 #if 0 /* controlled in pcm device */
2593         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2594         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2595         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2596 #endif
2597         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2598         { .name = "IEC958 Output Switch",
2599           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2600           .info = snd_cmipci_uswitch_info,
2601           .get = snd_cmipci_spdout_enable_get,
2602           .put = snd_cmipci_spdout_enable_put,
2603         },
2604         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2605         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2606         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2607 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2608         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2609         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2610 };
2611
2612 /* only for model 033/037 */
2613 static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2614         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2615         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2616         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2617 };
2618
2619 /* only for model 039 or later */
2620 static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2621         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2622         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2623         {
2624                 .name = "Mic-In Mode",
2625                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2626                 .info = snd_cmipci_mic_in_mode_info,
2627                 .get = snd_cmipci_mic_in_mode_get,
2628                 .put = snd_cmipci_mic_in_mode_put,
2629         }
2630 };
2631
2632 /* card control switches */
2633 static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2634 DEFINE_CARD_SWITCH("Modem", modem);
2635
2636
2637 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2638 {
2639         struct snd_card *card;
2640         const struct snd_kcontrol_new *sw;
2641         struct snd_kcontrol *kctl;
2642         unsigned int idx;
2643         int err;
2644
2645         if (snd_BUG_ON(!cm || !cm->card))
2646                 return -EINVAL;
2647
2648         card = cm->card;
2649
2650         strcpy(card->mixername, "CMedia PCI");
2651
2652         spin_lock_irq(&cm->reg_lock);
2653         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2654         spin_unlock_irq(&cm->reg_lock);
2655
2656         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2657                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2658                         if (!strcmp(snd_cmipci_mixers[idx].name,
2659                                 "PCM Playback Volume"))
2660                                 continue;
2661                 }
2662                 err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm));
2663                 if (err < 0)
2664                         return err;
2665         }
2666
2667         /* mixer switches */
2668         sw = snd_cmipci_mixer_switches;
2669         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2670                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2671                 if (err < 0)
2672                         return err;
2673         }
2674         if (! cm->can_multi_ch) {
2675                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2676                 if (err < 0)
2677                         return err;
2678         }
2679         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2680             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2681                 sw = snd_cmipci_8738_mixer_switches;
2682                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2683                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2684                         if (err < 0)
2685                                 return err;
2686                 }
2687                 if (cm->can_ac3_hw) {
2688                         kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm);
2689                         kctl->id.device = pcm_spdif_device;
2690                         err = snd_ctl_add(card, kctl);
2691                         if (err < 0)
2692                                 return err;
2693                         kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm);
2694                         kctl->id.device = pcm_spdif_device;
2695                         err = snd_ctl_add(card, kctl);
2696                         if (err < 0)
2697                                 return err;
2698                         kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm);
2699                         kctl->id.device = pcm_spdif_device;
2700                         err = snd_ctl_add(card, kctl);
2701                         if (err < 0)
2702                                 return err;
2703                 }
2704                 if (cm->chip_version <= 37) {
2705                         sw = snd_cmipci_old_mixer_switches;
2706                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2707                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2708                                 if (err < 0)
2709                                         return err;
2710                         }
2711                 }
2712         }
2713         if (cm->chip_version >= 39) {
2714                 sw = snd_cmipci_extra_mixer_switches;
2715                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2716                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2717                         if (err < 0)
2718                                 return err;
2719                 }
2720         }
2721
2722         /* card switches */
2723         /*
2724          * newer chips don't have the register bits to force modem link
2725          * detection; the bit that was FLINKON now mutes CH1
2726          */
2727         if (cm->chip_version < 39) {
2728                 err = snd_ctl_add(cm->card,
2729                                   snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2730                 if (err < 0)
2731                         return err;
2732         }
2733
2734         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2735                 struct snd_kcontrol *ctl;
2736                 ctl = snd_ctl_find_id_mixer(cm->card, cm_saved_mixer[idx].name);
2737                 if (ctl)
2738                         cm->mixer_res_ctl[idx] = ctl;
2739         }
2740
2741         return 0;
2742 }
2743
2744
2745 /*
2746  * proc interface
2747  */
2748
2749 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2750                                  struct snd_info_buffer *buffer)
2751 {
2752         struct cmipci *cm = entry->private_data;
2753         int i, v;
2754
2755         snd_iprintf(buffer, "%s\n", cm->card->longname);
2756         for (i = 0; i < 0x94; i++) {
2757                 if (i == 0x28)
2758                         i = 0x90;
2759                 v = inb(cm->iobase + i);
2760                 if (i % 4 == 0)
2761                         snd_iprintf(buffer, "\n%02x:", i);
2762                 snd_iprintf(buffer, " %02x", v);
2763         }
2764         snd_iprintf(buffer, "\n");
2765 }
2766
2767 static void snd_cmipci_proc_init(struct cmipci *cm)
2768 {
2769         snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2770 }
2771
2772 static const struct pci_device_id snd_cmipci_ids[] = {
2773         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2774         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2775         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2776         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2777         {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2778         {0,},
2779 };
2780
2781
2782 /*
2783  * check chip version and capabilities
2784  * driver name is modified according to the chip model
2785  */
2786 static void query_chip(struct cmipci *cm)
2787 {
2788         unsigned int detect;
2789
2790         /* check reg 0Ch, bit 24-31 */
2791         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2792         if (! detect) {
2793                 /* check reg 08h, bit 24-28 */
2794                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2795                 switch (detect) {
2796                 case 0:
2797                         cm->chip_version = 33;
2798                         if (cm->do_soft_ac3)
2799                                 cm->can_ac3_sw = 1;
2800                         else
2801                                 cm->can_ac3_hw = 1;
2802                         break;
2803                 case CM_CHIP_037:
2804                         cm->chip_version = 37;
2805                         cm->can_ac3_hw = 1;
2806                         break;
2807                 default:
2808                         cm->chip_version = 39;
2809                         cm->can_ac3_hw = 1;
2810                         break;
2811                 }
2812                 cm->max_channels = 2;
2813         } else {
2814                 if (detect & CM_CHIP_039) {
2815                         cm->chip_version = 39;
2816                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2817                                 cm->max_channels = 6;
2818                         else
2819                                 cm->max_channels = 4;
2820                 } else if (detect & CM_CHIP_8768) {
2821                         cm->chip_version = 68;
2822                         cm->max_channels = 8;
2823                         cm->can_96k = 1;
2824                 } else {
2825                         cm->chip_version = 55;
2826                         cm->max_channels = 6;
2827                         cm->can_96k = 1;
2828                 }
2829                 cm->can_ac3_hw = 1;
2830                 cm->can_multi_ch = 1;
2831         }
2832 }
2833
2834 #ifdef SUPPORT_JOYSTICK
2835 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2836 {
2837         static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2838         struct gameport *gp;
2839         struct resource *r = NULL;
2840         int i, io_port = 0;
2841
2842         if (joystick_port[dev] == 0)
2843                 return -ENODEV;
2844
2845         if (joystick_port[dev] == 1) { /* auto-detect */
2846                 for (i = 0; ports[i]; i++) {
2847                         io_port = ports[i];
2848                         r = devm_request_region(&cm->pci->dev, io_port, 1,
2849                                                 "CMIPCI gameport");
2850                         if (r)
2851                                 break;
2852                 }
2853         } else {
2854                 io_port = joystick_port[dev];
2855                 r = devm_request_region(&cm->pci->dev, io_port, 1,
2856                                         "CMIPCI gameport");
2857         }
2858
2859         if (!r) {
2860                 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2861                 return -EBUSY;
2862         }
2863
2864         cm->gameport = gp = gameport_allocate_port();
2865         if (!gp) {
2866                 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2867                 return -ENOMEM;
2868         }
2869         gameport_set_name(gp, "C-Media Gameport");
2870         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2871         gameport_set_dev_parent(gp, &cm->pci->dev);
2872         gp->io = io_port;
2873
2874         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2875
2876         gameport_register_port(cm->gameport);
2877
2878         return 0;
2879 }
2880
2881 static void snd_cmipci_free_gameport(struct cmipci *cm)
2882 {
2883         if (cm->gameport) {
2884                 gameport_unregister_port(cm->gameport);
2885                 cm->gameport = NULL;
2886
2887                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2888         }
2889 }
2890 #else
2891 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2892 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2893 #endif
2894
2895 static void snd_cmipci_free(struct snd_card *card)
2896 {
2897         struct cmipci *cm = card->private_data;
2898
2899         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2900         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2901         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2902         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2903         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2904         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2905         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2906
2907         /* reset mixer */
2908         snd_cmipci_mixer_write(cm, 0, 0);
2909
2910         snd_cmipci_free_gameport(cm);
2911 }
2912
2913 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2914 {
2915         long iosynth;
2916         unsigned int val;
2917         struct snd_opl3 *opl3;
2918         int err;
2919
2920         if (!fm_port)
2921                 goto disable_fm;
2922
2923         if (cm->chip_version >= 39) {
2924                 /* first try FM regs in PCI port range */
2925                 iosynth = cm->iobase + CM_REG_FM_PCI;
2926                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2927                                       OPL3_HW_OPL3, 1, &opl3);
2928         } else {
2929                 err = -EIO;
2930         }
2931         if (err < 0) {
2932                 /* then try legacy ports */
2933                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2934                 iosynth = fm_port;
2935                 switch (iosynth) {
2936                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2937                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2938                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2939                 case 0x388: val |= CM_FMSEL_388; break;
2940                 default:
2941                         goto disable_fm;
2942                 }
2943                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2944                 /* enable FM */
2945                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2946
2947                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2948                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2949                         dev_err(cm->card->dev,
2950                                 "no OPL device at %#lx, skipping...\n",
2951                                 iosynth);
2952                         goto disable_fm;
2953                 }
2954         }
2955         err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2956         if (err < 0) {
2957                 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2958                 return err;
2959         }
2960         return 0;
2961
2962  disable_fm:
2963         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2964         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2965         return 0;
2966 }
2967
2968 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2969                              int dev)
2970 {
2971         struct cmipci *cm = card->private_data;
2972         int err;
2973         unsigned int val;
2974         long iomidi = 0;
2975         int integrated_midi = 0;
2976         char modelstr[16];
2977         int pcm_index, pcm_spdif_index;
2978         static const struct pci_device_id intel_82437vx[] = {
2979                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2980                 { },
2981         };
2982
2983         err = pcim_enable_device(pci);
2984         if (err < 0)
2985                 return err;
2986
2987         spin_lock_init(&cm->reg_lock);
2988         mutex_init(&cm->open_mutex);
2989         cm->device = pci->device;
2990         cm->card = card;
2991         cm->pci = pci;
2992         cm->irq = -1;
2993         cm->channel[0].ch = 0;
2994         cm->channel[1].ch = 1;
2995         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2996
2997         err = pci_request_regions(pci, card->driver);
2998         if (err < 0)
2999                 return err;
3000         cm->iobase = pci_resource_start(pci, 0);
3001
3002         if (devm_request_irq(&pci->dev, pci->irq, snd_cmipci_interrupt,
3003                              IRQF_SHARED, KBUILD_MODNAME, cm)) {
3004                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3005                 return -EBUSY;
3006         }
3007         cm->irq = pci->irq;
3008         card->sync_irq = cm->irq;
3009         card->private_free = snd_cmipci_free;
3010
3011         pci_set_master(cm->pci);
3012
3013         /*
3014          * check chip version, max channels and capabilities
3015          */
3016
3017         cm->chip_version = 0;
3018         cm->max_channels = 2;
3019         cm->do_soft_ac3 = soft_ac3[dev];
3020
3021         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3022             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3023                 query_chip(cm);
3024         /* added -MCx suffix for chip supporting multi-channels */
3025         if (cm->can_multi_ch)
3026                 sprintf(cm->card->driver + strlen(cm->card->driver),
3027                         "-MC%d", cm->max_channels);
3028         else if (cm->can_ac3_sw)
3029                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3030
3031         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3032         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3033
3034 #if CM_CH_PLAY == 1
3035         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
3036 #else
3037         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
3038 #endif
3039
3040         /* initialize codec registers */
3041         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3042         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3043         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
3044         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3045         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3046         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
3047         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3048
3049         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3050         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3051 #if CM_CH_PLAY == 1
3052         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3053 #else
3054         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3055 #endif
3056         if (cm->chip_version) {
3057                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3058                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3059         }
3060         /* Set Bus Master Request */
3061         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3062
3063         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3064         switch (pci->device) {
3065         case PCI_DEVICE_ID_CMEDIA_CM8738:
3066         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3067                 if (!pci_dev_present(intel_82437vx))
3068                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3069                 break;
3070         default:
3071                 break;
3072         }
3073
3074         if (cm->chip_version < 68) {
3075                 val = pci->device < 0x110 ? 8338 : 8738;
3076         } else {
3077                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3078                 case 0:
3079                         val = 8769;
3080                         break;
3081                 case 2:
3082                         val = 8762;
3083                         break;
3084                 default:
3085                         switch ((pci->subsystem_vendor << 16) |
3086                                 pci->subsystem_device) {
3087                         case 0x13f69761:
3088                         case 0x584d3741:
3089                         case 0x584d3751:
3090                         case 0x584d3761:
3091                         case 0x584d3771:
3092                         case 0x72848384:
3093                                 val = 8770;
3094                                 break;
3095                         default:
3096                                 val = 8768;
3097                                 break;
3098                         }
3099                 }
3100         }
3101         sprintf(card->shortname, "C-Media CMI%d", val);
3102         if (cm->chip_version < 68)
3103                 scnprintf(modelstr, sizeof(modelstr),
3104                           " (model %d)", cm->chip_version);
3105         else
3106                 modelstr[0] = '\0';
3107         scnprintf(card->longname, sizeof(card->longname),
3108                   "%s%s at %#lx, irq %i",
3109                   card->shortname, modelstr, cm->iobase, cm->irq);
3110
3111         if (cm->chip_version >= 39) {
3112                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3113                 if (val != 0x00 && val != 0xff) {
3114                         if (mpu_port[dev])
3115                                 iomidi = cm->iobase + CM_REG_MPU_PCI;
3116                         integrated_midi = 1;
3117                 }
3118         }
3119         if (!integrated_midi) {
3120                 val = 0;
3121                 iomidi = mpu_port[dev];
3122                 switch (iomidi) {
3123                 case 0x320: val = CM_VMPU_320; break;
3124                 case 0x310: val = CM_VMPU_310; break;
3125                 case 0x300: val = CM_VMPU_300; break;
3126                 case 0x330: val = CM_VMPU_330; break;
3127                 default:
3128                             iomidi = 0; break;
3129                 }
3130                 if (iomidi > 0) {
3131                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3132                         /* enable UART */
3133                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3134                         if (inb(iomidi + 1) == 0xff) {
3135                                 dev_err(cm->card->dev,
3136                                         "cannot enable MPU-401 port at %#lx\n",
3137                                         iomidi);
3138                                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3139                                                      CM_UART_EN);
3140                                 iomidi = 0;
3141                         }
3142                 }
3143         }
3144
3145         if (cm->chip_version < 68) {
3146                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3147                 if (err < 0)
3148                         return err;
3149         }
3150
3151         /* reset mixer */
3152         snd_cmipci_mixer_write(cm, 0, 0);
3153
3154         snd_cmipci_proc_init(cm);
3155
3156         /* create pcm devices */
3157         pcm_index = pcm_spdif_index = 0;
3158         err = snd_cmipci_pcm_new(cm, pcm_index);
3159         if (err < 0)
3160                 return err;
3161         pcm_index++;
3162         err = snd_cmipci_pcm2_new(cm, pcm_index);
3163         if (err < 0)
3164                 return err;
3165         pcm_index++;
3166         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3167                 pcm_spdif_index = pcm_index;
3168                 err = snd_cmipci_pcm_spdif_new(cm, pcm_index);
3169                 if (err < 0)
3170                         return err;
3171         }
3172
3173         /* create mixer interface & switches */
3174         err = snd_cmipci_mixer_new(cm, pcm_spdif_index);
3175         if (err < 0)
3176                 return err;
3177
3178         if (iomidi > 0) {
3179                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3180                                           iomidi,
3181                                           (integrated_midi ?
3182                                            MPU401_INFO_INTEGRATED : 0) |
3183                                           MPU401_INFO_IRQ_HOOK,
3184                                           -1, &cm->rmidi);
3185                 if (err < 0)
3186                         dev_err(cm->card->dev,
3187                                 "no UART401 device at 0x%lx\n", iomidi);
3188         }
3189
3190 #ifdef USE_VAR48KRATE
3191         for (val = 0; val < ARRAY_SIZE(rates); val++)
3192                 snd_cmipci_set_pll(cm, rates[val], val);
3193
3194         /*
3195          * (Re-)Enable external switch spdo_48k
3196          */
3197         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3198 #endif /* USE_VAR48KRATE */
3199
3200         if (snd_cmipci_create_gameport(cm, dev) < 0)
3201                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3202
3203         return 0;
3204 }
3205
3206 /*
3207  */
3208
3209 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3210
3211 static int snd_cmipci_probe(struct pci_dev *pci,
3212                             const struct pci_device_id *pci_id)
3213 {
3214         static int dev;
3215         struct snd_card *card;
3216         int err;
3217
3218         if (dev >= SNDRV_CARDS)
3219                 return -ENODEV;
3220         if (! enable[dev]) {
3221                 dev++;
3222                 return -ENOENT;
3223         }
3224
3225         err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3226                                 sizeof(struct cmipci), &card);
3227         if (err < 0)
3228                 return err;
3229
3230         switch (pci->device) {
3231         case PCI_DEVICE_ID_CMEDIA_CM8738:
3232         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3233                 strcpy(card->driver, "CMI8738");
3234                 break;
3235         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3236         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3237                 strcpy(card->driver, "CMI8338");
3238                 break;
3239         default:
3240                 strcpy(card->driver, "CMIPCI");
3241                 break;
3242         }
3243
3244         err = snd_cmipci_create(card, pci, dev);
3245         if (err < 0)
3246                 goto error;
3247
3248         err = snd_card_register(card);
3249         if (err < 0)
3250                 goto error;
3251
3252         pci_set_drvdata(pci, card);
3253         dev++;
3254         return 0;
3255
3256  error:
3257         snd_card_free(card);
3258         return err;
3259 }
3260
3261 /*
3262  * power management
3263  */
3264 static const unsigned char saved_regs[] = {
3265         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3266         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3267         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3268         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3269         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3270 };
3271
3272 static const unsigned char saved_mixers[] = {
3273         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3274         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3275         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3276         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3277         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3278         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3279         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3280         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3281 };
3282
3283 static int snd_cmipci_suspend(struct device *dev)
3284 {
3285         struct snd_card *card = dev_get_drvdata(dev);
3286         struct cmipci *cm = card->private_data;
3287         int i;
3288
3289         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3290
3291         /* save registers */
3292         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3293                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3294         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3295                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3296
3297         /* disable ints */
3298         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3299         return 0;
3300 }
3301
3302 static int snd_cmipci_resume(struct device *dev)
3303 {
3304         struct snd_card *card = dev_get_drvdata(dev);
3305         struct cmipci *cm = card->private_data;
3306         int i;
3307
3308         /* reset / initialize to a sane state */
3309         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3310         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3311         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3312         snd_cmipci_mixer_write(cm, 0, 0);
3313
3314         /* restore registers */
3315         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3316                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3317         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3318                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3319
3320         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3321         return 0;
3322 }
3323
3324 static DEFINE_SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3325
3326 static struct pci_driver cmipci_driver = {
3327         .name = KBUILD_MODNAME,
3328         .id_table = snd_cmipci_ids,
3329         .probe = snd_cmipci_probe,
3330         .driver = {
3331                 .pm = &snd_cmipci_pm,
3332         },
3333 };
3334
3335 module_pci_driver(cmipci_driver);