1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2020 HabanaLabs, Ltd.
11 #include <linux/types.h>
12 #include <linux/ioctl.h>
15 * Defines that are asic-specific but constitutes as ABI between kernel driver
18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */
19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */
22 * 128 SOBs reserved for collective wait
23 * 16 SOBs reserved for sync stream
25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
28 * 64 monitors reserved for collective wait
29 * 8 monitors reserved for sync stream
31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72
34 * Goya queue Numbering
36 * The external queues (PCI DMA channels) MUST be before the internal queues
37 * and each group (PCI DMA channels and internal) must be contiguous inside
38 * itself but there can be a gap between the two groups (although not
43 GOYA_QUEUE_ID_DMA_0 = 0,
44 GOYA_QUEUE_ID_DMA_1 = 1,
45 GOYA_QUEUE_ID_DMA_2 = 2,
46 GOYA_QUEUE_ID_DMA_3 = 3,
47 GOYA_QUEUE_ID_DMA_4 = 4,
48 GOYA_QUEUE_ID_CPU_PQ = 5,
49 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */
50 GOYA_QUEUE_ID_TPC0 = 7,
51 GOYA_QUEUE_ID_TPC1 = 8,
52 GOYA_QUEUE_ID_TPC2 = 9,
53 GOYA_QUEUE_ID_TPC3 = 10,
54 GOYA_QUEUE_ID_TPC4 = 11,
55 GOYA_QUEUE_ID_TPC5 = 12,
56 GOYA_QUEUE_ID_TPC6 = 13,
57 GOYA_QUEUE_ID_TPC7 = 14,
62 * Gaudi queue Numbering
63 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*.
64 * Except one CPU queue, all the rest are internal queues.
68 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */
69 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */
70 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */
71 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */
72 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */
73 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */
74 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */
75 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */
76 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */
77 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */
78 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */
79 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */
80 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */
81 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */
82 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */
83 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */
84 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */
85 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */
86 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */
87 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */
88 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */
89 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */
90 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */
91 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */
92 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */
93 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */
94 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */
95 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */
96 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */
97 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */
98 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */
99 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */
100 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */
101 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */
102 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */
103 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */
104 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */
105 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */
106 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */
107 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */
108 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */
109 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */
110 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */
111 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */
112 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */
113 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */
114 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */
115 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */
116 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */
117 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */
118 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */
119 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */
120 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */
121 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */
122 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */
123 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */
124 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */
125 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */
126 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */
127 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */
128 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */
129 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */
130 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */
131 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */
132 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */
133 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */
134 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */
135 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */
136 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */
137 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */
138 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */
139 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */
140 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */
141 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */
142 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */
143 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */
144 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */
145 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */
146 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */
147 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */
148 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */
149 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */
150 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */
151 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */
152 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */
153 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */
154 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */
155 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */
156 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */
157 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */
158 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */
159 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */
160 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */
161 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */
162 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */
163 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */
164 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */
165 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */
166 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */
167 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */
168 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */
169 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */
170 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */
171 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */
172 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */
173 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */
174 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */
175 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */
176 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */
177 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */
178 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */
179 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */
180 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */
187 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle'
190 enum goya_engine_id {
191 GOYA_ENGINE_ID_DMA_0 = 0,
192 GOYA_ENGINE_ID_DMA_1,
193 GOYA_ENGINE_ID_DMA_2,
194 GOYA_ENGINE_ID_DMA_3,
195 GOYA_ENGINE_ID_DMA_4,
196 GOYA_ENGINE_ID_MME_0,
197 GOYA_ENGINE_ID_TPC_0,
198 GOYA_ENGINE_ID_TPC_1,
199 GOYA_ENGINE_ID_TPC_2,
200 GOYA_ENGINE_ID_TPC_3,
201 GOYA_ENGINE_ID_TPC_4,
202 GOYA_ENGINE_ID_TPC_5,
203 GOYA_ENGINE_ID_TPC_6,
204 GOYA_ENGINE_ID_TPC_7,
208 enum gaudi_engine_id {
209 GAUDI_ENGINE_ID_DMA_0 = 0,
210 GAUDI_ENGINE_ID_DMA_1,
211 GAUDI_ENGINE_ID_DMA_2,
212 GAUDI_ENGINE_ID_DMA_3,
213 GAUDI_ENGINE_ID_DMA_4,
214 GAUDI_ENGINE_ID_DMA_5,
215 GAUDI_ENGINE_ID_DMA_6,
216 GAUDI_ENGINE_ID_DMA_7,
217 GAUDI_ENGINE_ID_MME_0,
218 GAUDI_ENGINE_ID_MME_1,
219 GAUDI_ENGINE_ID_MME_2,
220 GAUDI_ENGINE_ID_MME_3,
221 GAUDI_ENGINE_ID_TPC_0,
222 GAUDI_ENGINE_ID_TPC_1,
223 GAUDI_ENGINE_ID_TPC_2,
224 GAUDI_ENGINE_ID_TPC_3,
225 GAUDI_ENGINE_ID_TPC_4,
226 GAUDI_ENGINE_ID_TPC_5,
227 GAUDI_ENGINE_ID_TPC_6,
228 GAUDI_ENGINE_ID_TPC_7,
229 GAUDI_ENGINE_ID_NIC_0,
230 GAUDI_ENGINE_ID_NIC_1,
231 GAUDI_ENGINE_ID_NIC_2,
232 GAUDI_ENGINE_ID_NIC_3,
233 GAUDI_ENGINE_ID_NIC_4,
234 GAUDI_ENGINE_ID_NIC_5,
235 GAUDI_ENGINE_ID_NIC_6,
236 GAUDI_ENGINE_ID_NIC_7,
237 GAUDI_ENGINE_ID_NIC_8,
238 GAUDI_ENGINE_ID_NIC_9,
243 * ASIC specific PLL index
245 * Used to retrieve in frequency info of different IPs via
246 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be
247 * used as an index in struct hl_pll_frequency_info
250 enum hl_goya_pll_index {
261 enum hl_gaudi_pll_index {
262 HL_GAUDI_CPU_PLL = 0,
276 * enum hl_device_status - Device status information.
277 * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational.
278 * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset.
279 * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable.
280 * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled.
281 * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in
283 * @HL_DEVICE_STATUS_LAST: Last status.
285 enum hl_device_status {
286 HL_DEVICE_STATUS_OPERATIONAL,
287 HL_DEVICE_STATUS_IN_RESET,
288 HL_DEVICE_STATUS_MALFUNCTION,
289 HL_DEVICE_STATUS_NEEDS_RESET,
290 HL_DEVICE_STATUS_IN_DEVICE_CREATION,
291 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION
294 enum hl_server_type {
295 HL_SERVER_TYPE_UNKNOWN = 0,
296 HL_SERVER_GAUDI_HLS1 = 1,
297 HL_SERVER_GAUDI_HLS1H = 2,
298 HL_SERVER_GAUDI_TYPE1 = 3,
299 HL_SERVER_GAUDI_TYPE2 = 4
302 /* Opcode for management ioctl
304 * HW_IP_INFO - Receive information about different IP blocks in the
306 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event
307 * occurred since the last hard reset.
308 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the
309 * specific context. This is relevant only for devices
310 * where the dram is managed by the kernel driver
311 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each
313 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't
314 * require an open context.
315 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device
316 * over the last period specified by the user.
317 * The period can be between 100ms to 1s, in
318 * resolution of 100ms. The return value is a
319 * percentage of the utilization rate.
320 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each
321 * event occurred since the driver was loaded.
322 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate
323 * of the device in MHz. The maximum clock rate is
324 * configurable via sysfs parameter
325 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset
326 * operations performed on the device since the last
327 * time the driver was loaded.
328 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time
329 * for synchronization.
330 * HL_INFO_CS_COUNTERS - Retrieve command submission counters
331 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters
332 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason
333 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore
334 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption
335 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency
336 * HL_INFO_POWER - Retrieve power information
337 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls
338 * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info
339 * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num
340 * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened
341 * and CS timeout or razwi error occurred.
342 * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number.
343 * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi:
344 * Timestamp of razwi.
345 * The address which accessing it caused the razwi.
347 * Razwi cause, was it a page fault or MMU access error.
349 #define HL_INFO_HW_IP_INFO 0
350 #define HL_INFO_HW_EVENTS 1
351 #define HL_INFO_DRAM_USAGE 2
352 #define HL_INFO_HW_IDLE 3
353 #define HL_INFO_DEVICE_STATUS 4
354 #define HL_INFO_DEVICE_UTILIZATION 6
355 #define HL_INFO_HW_EVENTS_AGGREGATE 7
356 #define HL_INFO_CLK_RATE 8
357 #define HL_INFO_RESET_COUNT 9
358 #define HL_INFO_TIME_SYNC 10
359 #define HL_INFO_CS_COUNTERS 11
360 #define HL_INFO_PCI_COUNTERS 12
361 #define HL_INFO_CLK_THROTTLE_REASON 13
362 #define HL_INFO_SYNC_MANAGER 14
363 #define HL_INFO_TOTAL_ENERGY 15
364 #define HL_INFO_PLL_FREQUENCY 16
365 #define HL_INFO_POWER 17
366 #define HL_INFO_OPEN_STATS 18
367 #define HL_INFO_DRAM_REPLACED_ROWS 21
368 #define HL_INFO_DRAM_PENDING_ROWS 22
369 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23
370 #define HL_INFO_CS_TIMEOUT_EVENT 24
371 #define HL_INFO_RAZWI_EVENT 25
373 #define HL_INFO_VERSION_MAX_LEN 128
374 #define HL_INFO_CARD_NAME_MAX_LEN 16
377 * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC
378 * @sram_base_address: The first SRAM physical base address that is free to be
380 * @dram_base_address: The first DRAM virtual or physical base address that is
381 * free to be used by the user.
382 * @dram_size: The DRAM size that is available to the user.
383 * @sram_size: The SRAM size that is available to the user.
384 * @num_of_events: The number of events that can be received from the f/w. This
385 * is needed so the user can what is the size of the h/w events
386 * array he needs to pass to the kernel when he wants to fetch
387 * the event counters.
388 * @device_id: PCI device ID of the ASIC.
389 * @module_id: Module ID of the ASIC for mezzanine cards in servers
391 * @first_available_interrupt_id: The first available interrupt ID for the user
392 * to be used when it works with user interrupts.
393 * @server_type: Server type that the Gaudi ASIC is currently installed in.
394 * The value is according to enum hl_server_type
395 * @cpld_version: CPLD version on the board.
396 * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs.
397 * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs.
398 * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs.
399 * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler
401 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant
402 * for Goya/Gaudi only.
403 * @dram_enabled: Whether the DRAM is enabled.
404 * @cpucp_version: The CPUCP f/w version.
405 * @card_name: The card name as passed by the f/w.
406 * @dram_page_size: The DRAM physical page size.
408 struct hl_info_hw_ip_info {
409 __u64 sram_base_address;
410 __u64 dram_base_address;
417 __u16 first_available_interrupt_id;
420 __u32 psoc_pci_pll_nr;
421 __u32 psoc_pci_pll_nf;
422 __u32 psoc_pci_pll_od;
423 __u32 psoc_pci_pll_div_factor;
424 __u8 tpc_enabled_mask;
427 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
428 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
430 __u64 dram_page_size;
433 struct hl_info_dram_usage {
438 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2
440 struct hl_info_hw_idle {
443 * Bitmask of busy engines.
444 * Bits definition is according to `enum <chip>_enging_id'.
446 __u32 busy_engines_mask;
449 * Extended Bitmask of busy engines.
450 * Bits definition is according to `enum <chip>_enging_id'.
452 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE];
455 struct hl_info_device_status {
460 struct hl_info_device_utilization {
465 struct hl_info_clk_rate {
466 __u32 cur_clk_rate_mhz;
467 __u32 max_clk_rate_mhz;
470 struct hl_info_reset_count {
471 __u32 hard_reset_cnt;
472 __u32 soft_reset_cnt;
475 struct hl_info_time_sync {
481 * struct hl_info_pci_counters - pci counters
482 * @rx_throughput: PCI rx throughput KBps
483 * @tx_throughput: PCI tx throughput KBps
484 * @replay_cnt: PCI replay counter
486 struct hl_info_pci_counters {
492 enum hl_clk_throttling_type {
493 HL_CLK_THROTTLE_TYPE_POWER,
494 HL_CLK_THROTTLE_TYPE_THERMAL,
495 HL_CLK_THROTTLE_TYPE_MAX
498 /* clk_throttling_reason masks */
499 #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER)
500 #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL)
503 * struct hl_info_clk_throttle - clock throttling reason
504 * @clk_throttling_reason: each bit represents a clk throttling reason
505 * @clk_throttling_timestamp_us: represents CPU timestamp in microseconds of the start-event
506 * @clk_throttling_duration_ns: the clock throttle time in nanosec
508 struct hl_info_clk_throttle {
509 __u32 clk_throttling_reason;
511 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX];
512 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX];
516 * struct hl_info_energy - device energy information
517 * @total_energy_consumption: total device energy consumption
519 struct hl_info_energy {
520 __u64 total_energy_consumption;
523 #define HL_PLL_NUM_OUTPUTS 4
525 struct hl_pll_frequency_info {
526 __u16 output[HL_PLL_NUM_OUTPUTS];
530 * struct hl_open_stats_info - device open statistics information
531 * @open_counter: ever growing counter, increased on each successful dev open
532 * @last_open_period_ms: duration (ms) device was open last time
534 struct hl_open_stats_info {
536 __u64 last_open_period_ms;
540 * struct hl_power_info - power information
541 * @power: power consumption
543 struct hl_power_info {
548 * struct hl_info_sync_manager - sync manager information
549 * @first_available_sync_object: first available sob
550 * @first_available_monitor: first available monitor
551 * @first_available_cq: first available cq
553 struct hl_info_sync_manager {
554 __u32 first_available_sync_object;
555 __u32 first_available_monitor;
556 __u32 first_available_cq;
561 * struct hl_info_cs_counters - command submission counters
562 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue
563 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue
564 * @total_parsing_drop_cnt: total dropped due to error in packet parsing
565 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing
566 * @total_queue_full_drop_cnt: total dropped due to queue full
567 * @ctx_queue_full_drop_cnt: context dropped due to queue full
568 * @total_device_in_reset_drop_cnt: total dropped due to device in reset
569 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset
570 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight
571 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight
572 * @total_validation_drop_cnt: total dropped due to validation error
573 * @ctx_validation_drop_cnt: context dropped due to validation error
575 struct hl_info_cs_counters {
576 __u64 total_out_of_mem_drop_cnt;
577 __u64 ctx_out_of_mem_drop_cnt;
578 __u64 total_parsing_drop_cnt;
579 __u64 ctx_parsing_drop_cnt;
580 __u64 total_queue_full_drop_cnt;
581 __u64 ctx_queue_full_drop_cnt;
582 __u64 total_device_in_reset_drop_cnt;
583 __u64 ctx_device_in_reset_drop_cnt;
584 __u64 total_max_cs_in_flight_drop_cnt;
585 __u64 ctx_max_cs_in_flight_drop_cnt;
586 __u64 total_validation_drop_cnt;
587 __u64 ctx_validation_drop_cnt;
591 * struct hl_info_last_err_open_dev_time - last error boot information.
592 * @timestamp: timestamp of last time the device was opened and error occurred.
594 struct hl_info_last_err_open_dev_time {
599 * struct hl_info_cs_timeout_event - last CS timeout information.
600 * @timestamp: timestamp when last CS timeout event occurred.
601 * @seq: sequence number of last CS timeout event.
603 struct hl_info_cs_timeout_event {
608 #define HL_RAZWI_PAGE_FAULT 0
609 #define HL_RAZWI_MMU_ACCESS_ERROR 1
612 * struct hl_info_razwi_event - razwi information.
613 * @timestamp: timestamp of razwi.
614 * @addr: address which accessing it caused razwi.
615 * @engine_id_1: engine id of the razwi initiator, if it was initiated by engine that does not
616 * have engine id it will be set to U16_MAX.
617 * @engine_id_2: second engine id of razwi initiator. Might happen that razwi have 2 possible
618 * engines which one them caused the razwi. In that case, it will contain the
619 * second possible engine id, otherwise it will be set to U16_MAX.
620 * @no_engine_id: if razwi initiator does not have engine id, this field will be set to 1,
622 * @error_type: cause of razwi, page fault or access error, otherwise it will be set to U8_MAX.
623 * @pad: padding to 64 bit.
625 struct hl_info_razwi_event {
643 * struct hl_info_args - Main structure to retrieve device related information.
644 * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation
646 * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it
647 * limits how many bytes the kernel can write. For hw_events array, the size should be
648 * hl_info_hw_ip_info.num_of_events * sizeof(__u32).
649 * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details.
650 * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores).
651 * @ctx_id: Context ID of the user. Currently not in use.
652 * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms
653 * resolution. Currently not in use.
654 * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration.
655 * @pad: Padding to 64 bit.
657 struct hl_info_args {
658 __u64 return_pointer;
672 /* Opcode to create a new command buffer */
673 #define HL_CB_OP_CREATE 0
674 /* Opcode to destroy previously created command buffer */
675 #define HL_CB_OP_DESTROY 1
676 /* Opcode to retrieve information about a command buffer */
677 #define HL_CB_OP_INFO 2
679 /* 2MB minus 32 bytes for 2xMSG_PROT */
680 #define HL_MAX_CB_SIZE (0x200000 - 32)
682 /* Indicates whether the command buffer should be mapped to the device's MMU */
683 #define HL_CB_FLAGS_MAP 0x1
685 /* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */
686 #define HL_CB_FLAGS_GET_DEVICE_VA 0x2
689 /* Handle of CB or 0 if we want to create one */
693 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that
694 * will be allocated, regardless of this parameter's value, is PAGE_SIZE
697 /* Context ID - Currently not in use */
709 /* Information about CB */
711 /* Usage count of CB */
716 /* CB mapped address to device MMU */
724 struct hl_cb_out out;
727 /* HL_CS_CHUNK_FLAGS_ values
729 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB:
730 * Indicates if the CB was allocated and mapped by userspace.
731 * User allocated CB is a command buffer allocated by the user, via malloc
732 * (or similar). After allocating the CB, the user invokes “memory ioctl”
733 * to map the user memory into a device virtual address. The user provides
734 * this address via the cb_handle field. The interface provides the
735 * ability to create a large CBs, Which aren’t limited to
736 * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues
737 * throughput. This CB allocation method also reduces the use of Linux
738 * DMA-able memory pool. Which are limited and used by other Linux
741 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
744 * This structure size must always be fixed to 64-bytes for backward
749 /* For external queue, this represents a Handle of CB on the
751 * For internal queue in Goya, this represents an SRAM or
752 * a DRAM address of the internal CB. In Gaudi, this might also
753 * represent a mapped host address of the CB.
755 * A mapped host address is in the device address space, after
756 * a host address was mapped by the device MMU.
760 /* Relevant only when HL_CS_FLAGS_WAIT or
761 * HL_CS_FLAGS_COLLECTIVE_WAIT is set
762 * This holds address of array of u64 values that contain
763 * signal CS sequence numbers. The wait described by
764 * this job will listen on all those signals
765 * (wait event per signal)
767 __u64 signal_seq_arr;
770 * Relevant only when HL_CS_FLAGS_WAIT or
771 * HL_CS_FLAGS_COLLECTIVE_WAIT is set
772 * along with HL_CS_FLAGS_ENCAP_SIGNALS.
773 * This is the CS sequence which has the encapsulated signals.
775 __u64 encaps_signal_seq;
778 /* Index of queue to put the CB on */
783 * Size of command buffer with valid packets
784 * Can be smaller then actual CB size
788 /* Relevant only when HL_CS_FLAGS_WAIT or
789 * HL_CS_FLAGS_COLLECTIVE_WAIT is set.
790 * Number of entries in signal_seq_arr
792 __u32 num_signal_seq_arr;
794 /* Relevant only when HL_CS_FLAGS_WAIT or
795 * HL_CS_FLAGS_COLLECTIVE_WAIT is set along
796 * with HL_CS_FLAGS_ENCAP_SIGNALS
797 * This set the signals range that the user want to wait for
798 * out of the whole reserved signals range.
799 * e.g if the signals range is 20, and user don't want
800 * to wait for signal 8, so he set this offset to 7, then
801 * he call the API again with 9 and so on till 20.
803 __u32 encaps_signal_offset;
806 /* HL_CS_CHUNK_FLAGS_* */
807 __u32 cs_chunk_flags;
809 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set.
810 * This holds the collective engine ID. The wait described by this job
811 * will sync with this engine and with all NICs before completion.
813 __u32 collective_engine_id;
815 /* Align structure to 64 bytes */
819 /* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */
820 #define HL_CS_FLAGS_FORCE_RESTORE 0x1
821 #define HL_CS_FLAGS_SIGNAL 0x2
822 #define HL_CS_FLAGS_WAIT 0x4
823 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8
824 #define HL_CS_FLAGS_TIMESTAMP 0x20
825 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40
826 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80
827 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100
828 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200
829 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400
832 * The encapsulated signals CS is merged into the existing CS ioctls.
833 * In order to use this feature need to follow the below procedure:
834 * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY
835 * the output of this API will be the SOB offset from CFG_BASE.
836 * this address will be used to patch CB cmds to do the signaling for this
837 * SOB by incrementing it's value.
838 * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY
839 * CS type, note that this might fail if out-of-sync happened to the SOB
840 * value, in case other signaling request to the same SOB occurred between
841 * reserve-unreserve calls.
842 * 2. Use the staged CS to do the encapsulated signaling jobs.
843 * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
844 * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset
845 * field. This offset allows app to wait on part of the reserved signals.
846 * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag
847 * to wait for the encapsulated signals.
849 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800
850 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000
851 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000
853 #define HL_CS_STATUS_SUCCESS 0
855 #define HL_MAX_JOBS_PER_CS 512
859 /* this holds address of array of hl_cs_chunk for restore phase */
860 __u64 chunks_restore;
862 /* holds address of array of hl_cs_chunk for execution phase */
863 __u64 chunks_execute;
867 * Sequence number of a staged submission CS
868 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and
869 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset.
874 * Encapsulated signals handle id
875 * Valid for two flows:
876 * 1. CS with encapsulated signals:
877 * when HL_CS_FLAGS_STAGED_SUBMISSION and
878 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
879 * and HL_CS_FLAGS_ENCAP_SIGNALS are set.
880 * 2. unreserve signals:
881 * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set.
883 __u32 encaps_sig_handle_id;
885 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
887 /* Encapsulated signals number */
888 __u32 encaps_signals_count;
890 /* Encapsulated signals queue index (stream) */
891 __u32 encaps_signals_q_idx;
895 /* Number of chunks in restore phase array. Maximum number is
898 __u32 num_chunks_restore;
900 /* Number of chunks in execution array. Maximum number is
903 __u32 num_chunks_execute;
905 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT
913 /* Context ID - Currently not in use */
920 * seq holds the sequence number of the CS to pass to wait
921 * ioctl. All values are valid except for 0 and ULLONG_MAX
925 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
927 /* This is the resereved signal handle id */
930 /* This is the signals count */
939 * SOB base address offset
940 * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set
942 __u32 sob_base_addr_offset;
945 * Count of completed signals in SOB before current signal submission.
946 * Valid only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION)
947 * or HL_CS_FLAGS_SIGNAL is set
949 __u16 sob_count_before_submission;
955 struct hl_cs_out out;
958 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2
959 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000
960 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4
961 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10
963 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32
965 struct hl_wait_cs_in {
969 * In case of wait_cs holds the CS sequence number.
970 * In case of wait for multi CS hold a user pointer to
971 * an array of CS sequence numbers
974 /* Absolute timeout to wait for command submission
982 /* User address for completion comparison.
983 * upon interrupt, driver will compare the value pointed
984 * by this address with the supplied target value.
985 * in order not to perform any comparison, set address
987 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
991 /* cq_counters_handle to a kernel mapped cb which contains
993 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
995 __u64 cq_counters_handle;
998 /* Target value for completion comparison */
1003 /* Context ID - Currently not in use */
1006 /* HL_WAIT_CS_FLAGS_*
1007 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include
1008 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order
1009 * not to specify an interrupt id ,set mask to all 1s.
1015 /* Multi CS API info- valid entries in multi-CS array */
1020 /* Absolute timeout to wait for an interrupt in microseconds.
1021 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
1023 __u64 interrupt_timeout_us;
1027 * cq counter offset inside the counters cb pointed by cq_counters_handle above.
1028 * upon interrupt, driver will compare the value pointed
1029 * by this address (cq_counters_handle + cq_counters_offset)
1030 * with the supplied target value.
1031 * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
1033 __u64 cq_counters_offset;
1036 #define HL_WAIT_CS_STATUS_COMPLETED 0
1037 #define HL_WAIT_CS_STATUS_BUSY 1
1038 #define HL_WAIT_CS_STATUS_TIMEDOUT 2
1039 #define HL_WAIT_CS_STATUS_ABORTED 3
1041 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1
1042 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2
1044 struct hl_wait_cs_out {
1045 /* HL_WAIT_CS_STATUS_* */
1047 /* HL_WAIT_CS_STATUS_FLAG* */
1050 * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set
1051 * for wait_cs: timestamp of CS completion
1052 * for wait_multi_cs: timestamp of FIRST CS completion
1054 __s64 timestamp_nsec;
1055 /* multi CS completion bitmap */
1056 __u32 cs_completion_map;
1060 union hl_wait_cs_args {
1061 struct hl_wait_cs_in in;
1062 struct hl_wait_cs_out out;
1065 /* Opcode to allocate device memory */
1066 #define HL_MEM_OP_ALLOC 0
1067 /* Opcode to free previously allocated device memory */
1068 #define HL_MEM_OP_FREE 1
1069 /* Opcode to map host and device memory */
1070 #define HL_MEM_OP_MAP 2
1071 /* Opcode to unmap previously mapped host and device memory */
1072 #define HL_MEM_OP_UNMAP 3
1073 /* Opcode to map a hw block */
1074 #define HL_MEM_OP_MAP_BLOCK 4
1075 /* Opcode to create DMA-BUF object for an existing device memory allocation
1076 * and to export an FD of that DMA-BUF back to the caller
1078 #define HL_MEM_OP_EXPORT_DMABUF_FD 5
1081 #define HL_MEM_CONTIGUOUS 0x1
1082 #define HL_MEM_SHARED 0x2
1083 #define HL_MEM_USERPTR 0x4
1084 #define HL_MEM_FORCE_HINT 0x8
1088 /* HL_MEM_OP_ALLOC- allocate device memory */
1094 /* HL_MEM_OP_FREE - free device memory */
1096 /* Handle returned from HL_MEM_OP_ALLOC */
1100 /* HL_MEM_OP_MAP - map device memory */
1103 * Requested virtual address of mapped memory.
1104 * The driver will try to map the requested region to
1105 * this hint address, as long as the address is valid
1106 * and not already mapped. The user should check the
1107 * returned address of the IOCTL to make sure he got
1108 * the hint address. Passing 0 here means that the
1109 * driver will choose the address itself.
1112 /* Handle returned from HL_MEM_OP_ALLOC */
1116 /* HL_MEM_OP_MAP - map host memory */
1118 /* Address of allocated host memory */
1119 __u64 host_virt_addr;
1121 * Requested virtual address of mapped memory.
1122 * The driver will try to map the requested region to
1123 * this hint address, as long as the address is valid
1124 * and not already mapped. The user should check the
1125 * returned address of the IOCTL to make sure he got
1126 * the hint address. Passing 0 here means that the
1127 * driver will choose the address itself.
1130 /* Size of allocated host memory */
1134 /* HL_MEM_OP_MAP_BLOCK - map a hw block */
1137 * HW block address to map, a handle and size will be
1138 * returned to the user and will be used to mmap the
1139 * relevant block. Only addresses from configuration
1140 * space are allowed.
1145 /* HL_MEM_OP_UNMAP - unmap host memory */
1147 /* Virtual address returned from HL_MEM_OP_MAP */
1148 __u64 device_virt_addr;
1151 /* HL_MEM_OP_EXPORT_DMABUF_FD */
1153 /* Handle returned from HL_MEM_OP_ALLOC. In Gaudi,
1154 * where we don't have MMU for the device memory, the
1155 * driver expects a physical address (instead of
1156 * a handle) in the device memory space.
1159 /* Size of memory allocation. Relevant only for GAUDI */
1167 * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode, this field holds the
1168 * DMA-BUF file/FD flags.
1171 /* Context ID - Currently not in use */
1179 * Used for HL_MEM_OP_MAP as the virtual address that was
1180 * assigned in the device VA space.
1181 * A value of 0 means the requested operation failed.
1183 __u64 device_virt_addr;
1186 * Used in HL_MEM_OP_ALLOC
1187 * This is the assigned handle for the allocated memory
1193 * Used in HL_MEM_OP_MAP_BLOCK.
1194 * This is the assigned handle for the mapped block
1199 * Used in HL_MEM_OP_MAP_BLOCK
1200 * This is the size of the mapped block
1207 /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the
1208 * DMA-BUF object that was created to describe a memory
1209 * allocation on the device's memory space. The FD should be
1210 * passed to the importer driver
1217 struct hl_mem_in in;
1218 struct hl_mem_out out;
1221 #define HL_DEBUG_MAX_AUX_VALUES 10
1223 struct hl_debug_params_etr {
1224 /* Address in memory to allocate buffer */
1225 __u64 buffer_address;
1227 /* Size of buffer to allocate */
1230 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
1235 struct hl_debug_params_etf {
1236 /* Address in memory to allocate buffer */
1237 __u64 buffer_address;
1239 /* Size of buffer to allocate */
1242 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
1247 struct hl_debug_params_stm {
1248 /* Two bit masks for HW event and Stimulus Port */
1252 /* Trace source ID */
1255 /* Frequency for the timestamp register */
1259 struct hl_debug_params_bmon {
1260 /* Two address ranges that the user can request to filter */
1267 /* Capture window configuration */
1271 /* Trace source ID */
1276 struct hl_debug_params_spmu {
1277 /* Event types selection */
1278 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
1280 /* Number of event types selection */
1281 __u32 event_types_num;
1285 /* Opcode for ETR component */
1286 #define HL_DEBUG_OP_ETR 0
1287 /* Opcode for ETF component */
1288 #define HL_DEBUG_OP_ETF 1
1289 /* Opcode for STM component */
1290 #define HL_DEBUG_OP_STM 2
1291 /* Opcode for FUNNEL component */
1292 #define HL_DEBUG_OP_FUNNEL 3
1293 /* Opcode for BMON component */
1294 #define HL_DEBUG_OP_BMON 4
1295 /* Opcode for SPMU component */
1296 #define HL_DEBUG_OP_SPMU 5
1297 /* Opcode for timestamp (deprecated) */
1298 #define HL_DEBUG_OP_TIMESTAMP 6
1299 /* Opcode for setting the device into or out of debug mode. The enable
1300 * variable should be 1 for enabling debug mode and 0 for disabling it
1302 #define HL_DEBUG_OP_SET_MODE 7
1304 struct hl_debug_args {
1306 * Pointer to user input structure.
1307 * This field is relevant to specific opcodes.
1310 /* Pointer to user output structure */
1312 /* Size of user input structure */
1314 /* Size of user output structure */
1319 * Register index in the component, taken from the debug_regs_index enum
1320 * in the various ASIC header files
1323 /* Enable/disable */
1325 /* Context ID - Currently not in use */
1330 * Various information operations such as:
1331 * - H/W IP information
1332 * - Current dram usage
1334 * The user calls this IOCTL with an opcode that describes the required
1335 * information. The user should supply a pointer to a user-allocated memory
1336 * chunk, which will be filled by the driver with the requested information.
1338 * The user supplies the maximum amount of size to copy into the user's memory,
1339 * in order to prevent data corruption in case of differences between the
1340 * definitions of structures in kernel and userspace, e.g. in case of old
1341 * userspace and new kernel driver
1343 #define HL_IOCTL_INFO \
1344 _IOWR('H', 0x01, struct hl_info_args)
1348 * - Request a Command Buffer
1349 * - Destroy a Command Buffer
1351 * The command buffers are memory blocks that reside in DMA-able address
1352 * space and are physically contiguous so they can be accessed by the device
1353 * directly. They are allocated using the coherent DMA API.
1355 * When creating a new CB, the IOCTL returns a handle of it, and the user-space
1356 * process needs to use that handle to mmap the buffer so it can access them.
1358 * In some instances, the device must access the command buffer through the
1359 * device's MMU, and thus its memory should be mapped. In these cases, user can
1360 * indicate the driver that such a mapping is required.
1361 * The resulting device virtual address will be used internally by the driver,
1362 * and won't be returned to user.
1365 #define HL_IOCTL_CB \
1366 _IOWR('H', 0x02, union hl_cb_args)
1369 * Command Submission
1371 * To submit work to the device, the user need to call this IOCTL with a set
1372 * of JOBS. That set of JOBS constitutes a CS object.
1373 * Each JOB will be enqueued on a specific queue, according to the user's input.
1374 * There can be more then one JOB per queue.
1376 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase
1377 * and a second set is for "execution" phase.
1378 * The JOBS on the "restore" phase are enqueued only after context-switch
1379 * (or if its the first CS for this context). The user can also order the
1380 * driver to run the "restore" phase explicitly
1382 * There are two types of queues - external and internal. External queues
1383 * are DMA queues which transfer data from/to the Host. All other queues are
1384 * internal. The driver will get completion notifications from the device only
1385 * on JOBS which are enqueued in the external queues.
1387 * For jobs on external queues, the user needs to create command buffers
1388 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on
1389 * internal queues, the user needs to prepare a "command buffer" with packets
1390 * on either the device SRAM/DRAM or the host, and give the device address of
1391 * that buffer to the CS ioctl.
1393 * This IOCTL is asynchronous in regard to the actual execution of the CS. This
1394 * means it returns immediately after ALL the JOBS were enqueued on their
1395 * relevant queues. Therefore, the user mustn't assume the CS has been completed
1396 * or has even started to execute.
1398 * Upon successful enqueue, the IOCTL returns a sequence number which the user
1399 * can use with the "Wait for CS" IOCTL to check whether the handle's CS
1400 * external JOBS have been completed. Note that if the CS has internal JOBS
1401 * which can execute AFTER the external JOBS have finished, the driver might
1402 * report that the CS has finished executing BEFORE the internal JOBS have
1403 * actually finished executing.
1405 * Even though the sequence number increments per CS, the user can NOT
1406 * automatically assume that if CS with sequence number N finished, then CS
1407 * with sequence number N-1 also finished. The user can make this assumption if
1408 * and only if CS N and CS N-1 are exactly the same (same CBs for the same
1411 #define HL_IOCTL_CS \
1412 _IOWR('H', 0x03, union hl_cs_args)
1415 * Wait for Command Submission
1417 * The user can call this IOCTL with a handle it received from the CS IOCTL
1418 * to wait until the handle's CS has finished executing. The user will wait
1419 * inside the kernel until the CS has finished or until the user-requested
1420 * timeout has expired.
1422 * If the timeout value is 0, the driver won't sleep at all. It will check
1423 * the status of the CS and return immediately
1425 * The return value of the IOCTL is a standard Linux error code. The possible
1428 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal
1429 * that the user process received
1430 * ETIMEDOUT - The CS has caused a timeout on the device
1431 * EIO - The CS was aborted (usually because the device was reset)
1432 * ENODEV - The device wants to do hard-reset (so user need to close FD)
1434 * The driver also returns a custom define in case the IOCTL call returned 0.
1435 * The define can be one of the following:
1437 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0)
1438 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0)
1439 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device
1441 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the
1442 * device was reset (EIO)
1445 #define HL_IOCTL_WAIT_CS \
1446 _IOWR('H', 0x04, union hl_wait_cs_args)
1450 * - Map host memory to device MMU
1451 * - Unmap host memory from device MMU
1453 * This IOCTL allows the user to map host memory to the device MMU
1455 * For host memory, the IOCTL doesn't allocate memory. The user is supposed
1456 * to allocate the memory in user-space (malloc/new). The driver pins the
1457 * physical pages (up to the allowed limit by the OS), assigns a virtual
1458 * address in the device VA space and initializes the device MMU.
1460 * There is an option for the user to specify the requested virtual address.
1463 #define HL_IOCTL_MEMORY \
1464 _IOWR('H', 0x05, union hl_mem_args)
1468 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces
1470 * This IOCTL allows the user to get debug traces from the chip.
1472 * Before the user can send configuration requests of the various
1473 * debug/profile engines, it needs to set the device into debug mode.
1474 * This is because the debug/profile infrastructure is shared component in the
1475 * device and we can't allow multiple users to access it at the same time.
1477 * Once a user set the device into debug mode, the driver won't allow other
1478 * users to "work" with the device, i.e. open a FD. If there are multiple users
1479 * opened on the device, the driver won't allow any user to debug the device.
1481 * For each configuration request, the user needs to provide the register index
1482 * and essential data such as buffer address and size.
1484 * Once the user has finished using the debug/profile engines, he should
1485 * set the device into non-debug mode, i.e. disable debug mode.
1487 * The driver can decide to "kick out" the user if he abuses this interface.
1490 #define HL_IOCTL_DEBUG \
1491 _IOWR('H', 0x06, struct hl_debug_args)
1493 #define HL_COMMAND_START 0x01
1494 #define HL_COMMAND_END 0x07
1496 #endif /* HABANALABS_H_ */