include/dt-bindings/clock/dra7.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2017 Texas Instruments, Inc.
   4  */
   5 #ifndef __DT_BINDINGS_CLK_DRA7_H
   6 #define __DT_BINDINGS_CLK_DRA7_H
   7
   8 #define DRA7_CLKCTRL_OFFSET     0x20
   9 #define DRA7_CLKCTRL_INDEX(offset)      ((offset) - DRA7_CLKCTRL_OFFSET)
  10
  11 /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
  12
  13 /* mpu clocks */
  14 #define DRA7_MPU_CLKCTRL        DRA7_CLKCTRL_INDEX(0x20)
  15
  16 /* ipu clocks */
  17 #define _DRA7_IPU_CLKCTRL_OFFSET        0x40
  18 #define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
  19 #define DRA7_MCASP1_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x50)
  20 #define DRA7_TIMER5_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x58)
  21 #define DRA7_TIMER6_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x60)
  22 #define DRA7_TIMER7_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x68)
  23 #define DRA7_TIMER8_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x70)
  24 #define DRA7_I2C5_CLKCTRL       _DRA7_IPU_CLKCTRL_INDEX(0x78)
  25 #define DRA7_UART6_CLKCTRL      _DRA7_IPU_CLKCTRL_INDEX(0x80)
  26
  27 /* rtc clocks */
  28 #define DRA7_RTC_CLKCTRL_OFFSET 0x40
  29 #define DRA7_RTC_CLKCTRL_INDEX(offset)  ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
  30 #define DRA7_RTCSS_CLKCTRL      DRA7_RTC_CLKCTRL_INDEX(0x44)
  31
  32 /* vip clocks */
  33 #define DRA7_VIP1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x20)
  34 #define DRA7_VIP2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
  35 #define DRA7_VIP3_CLKCTRL       DRA7_CLKCTRL_INDEX(0x30)
  36
  37 /* vpe clocks */
  38 #define DRA7_VPE_CLKCTRL_OFFSET 0x60
  39 #define DRA7_VPE_CLKCTRL_INDEX(offset)  ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
  40 #define DRA7_VPE_CLKCTRL        DRA7_VPE_CLKCTRL_INDEX(0x64)
  41
  42 /* coreaon clocks */
  43 #define DRA7_SMARTREFLEX_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x28)
  44 #define DRA7_SMARTREFLEX_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x38)
  45
  46 /* l3main1 clocks */
  47 #define DRA7_L3_MAIN_1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
  48 #define DRA7_GPMC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
  49 #define DRA7_TPCC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x70)
  50 #define DRA7_TPTC0_CLKCTRL      DRA7_CLKCTRL_INDEX(0x78)
  51 #define DRA7_TPTC1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x80)
  52 #define DRA7_VCP1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x88)
  53 #define DRA7_VCP2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x90)
  54
  55 /* dma clocks */
  56 #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
  57
  58 /* emif clocks */
  59 #define DRA7_DMM_CLKCTRL        DRA7_CLKCTRL_INDEX(0x20)
  60
  61 /* atl clocks */
  62 #define DRA7_ATL_CLKCTRL_OFFSET 0x0
  63 #define DRA7_ATL_CLKCTRL_INDEX(offset)  ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
  64 #define DRA7_ATL_CLKCTRL        DRA7_ATL_CLKCTRL_INDEX(0x0)
  65
  66 /* l4cfg clocks */
  67 #define DRA7_L4_CFG_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
  68 #define DRA7_SPINLOCK_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
  69 #define DRA7_MAILBOX1_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
  70 #define DRA7_MAILBOX2_CLKCTRL   DRA7_CLKCTRL_INDEX(0x48)
  71 #define DRA7_MAILBOX3_CLKCTRL   DRA7_CLKCTRL_INDEX(0x50)
  72 #define DRA7_MAILBOX4_CLKCTRL   DRA7_CLKCTRL_INDEX(0x58)
  73 #define DRA7_MAILBOX5_CLKCTRL   DRA7_CLKCTRL_INDEX(0x60)
  74 #define DRA7_MAILBOX6_CLKCTRL   DRA7_CLKCTRL_INDEX(0x68)
  75 #define DRA7_MAILBOX7_CLKCTRL   DRA7_CLKCTRL_INDEX(0x70)
  76 #define DRA7_MAILBOX8_CLKCTRL   DRA7_CLKCTRL_INDEX(0x78)
  77 #define DRA7_MAILBOX9_CLKCTRL   DRA7_CLKCTRL_INDEX(0x80)
  78 #define DRA7_MAILBOX10_CLKCTRL  DRA7_CLKCTRL_INDEX(0x88)
  79 #define DRA7_MAILBOX11_CLKCTRL  DRA7_CLKCTRL_INDEX(0x90)
  80 #define DRA7_MAILBOX12_CLKCTRL  DRA7_CLKCTRL_INDEX(0x98)
  81 #define DRA7_MAILBOX13_CLKCTRL  DRA7_CLKCTRL_INDEX(0xa0)
  82
  83 /* l3instr clocks */
  84 #define DRA7_L3_MAIN_2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
  85 #define DRA7_L3_INSTR_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
  86
  87 /* dss clocks */
  88 #define DRA7_DSS_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
  89 #define DRA7_BB2D_CLKCTRL       DRA7_CLKCTRL_INDEX(0x30)
  90
  91 /* l3init clocks */
  92 #define DRA7_MMC1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
  93 #define DRA7_MMC2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x30)
  94 #define DRA7_USB_OTG_SS2_CLKCTRL        DRA7_CLKCTRL_INDEX(0x40)
  95 #define DRA7_USB_OTG_SS3_CLKCTRL        DRA7_CLKCTRL_INDEX(0x48)
  96 #define DRA7_USB_OTG_SS4_CLKCTRL        DRA7_CLKCTRL_INDEX(0x50)
  97 #define DRA7_SATA_CLKCTRL       DRA7_CLKCTRL_INDEX(0x88)
  98 #define DRA7_PCIE1_CLKCTRL      DRA7_CLKCTRL_INDEX(0xb0)
  99 #define DRA7_PCIE2_CLKCTRL      DRA7_CLKCTRL_INDEX(0xb8)
 100 #define DRA7_GMAC_CLKCTRL       DRA7_CLKCTRL_INDEX(0xd0)
 101 #define DRA7_OCP2SCP1_CLKCTRL   DRA7_CLKCTRL_INDEX(0xe0)
 102 #define DRA7_OCP2SCP3_CLKCTRL   DRA7_CLKCTRL_INDEX(0xe8)
 103 #define DRA7_USB_OTG_SS1_CLKCTRL        DRA7_CLKCTRL_INDEX(0xf0)
 104
 105 /* l4per clocks */
 106 #define _DRA7_L4PER_CLKCTRL_OFFSET      0x0
 107 #define _DRA7_L4PER_CLKCTRL_INDEX(offset)       ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
 108 #define DRA7_L4_PER2_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc)
 109 #define DRA7_L4_PER3_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x14)
 110 #define DRA7_TIMER10_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x28)
 111 #define DRA7_TIMER11_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x30)
 112 #define DRA7_TIMER2_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x38)
 113 #define DRA7_TIMER3_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x40)
 114 #define DRA7_TIMER4_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x48)
 115 #define DRA7_TIMER9_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x50)
 116 #define DRA7_ELM_CLKCTRL        _DRA7_L4PER_CLKCTRL_INDEX(0x58)
 117 #define DRA7_GPIO2_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x60)
 118 #define DRA7_GPIO3_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x68)
 119 #define DRA7_GPIO4_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x70)
 120 #define DRA7_GPIO5_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x78)
 121 #define DRA7_GPIO6_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x80)
 122 #define DRA7_HDQ1W_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x88)
 123 #define DRA7_EPWMSS1_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x90)
 124 #define DRA7_EPWMSS2_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x98)
 125 #define DRA7_I2C1_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
 126 #define DRA7_I2C2_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
 127 #define DRA7_I2C3_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
 128 #define DRA7_I2C4_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
 129 #define DRA7_L4_PER1_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
 130 #define DRA7_EPWMSS0_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
 131 #define DRA7_TIMER13_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
 132 #define DRA7_TIMER14_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
 133 #define DRA7_TIMER15_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
 134 #define DRA7_MCSPI1_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
 135 #define DRA7_MCSPI2_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
 136 #define DRA7_MCSPI3_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x100)
 137 #define DRA7_MCSPI4_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x108)
 138 #define DRA7_GPIO7_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x110)
 139 #define DRA7_GPIO8_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x118)
 140 #define DRA7_MMC3_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x120)
 141 #define DRA7_MMC4_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x128)
 142 #define DRA7_TIMER16_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x130)
 143 #define DRA7_QSPI_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x138)
 144 #define DRA7_UART1_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x140)
 145 #define DRA7_UART2_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x148)
 146 #define DRA7_UART3_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x150)
 147 #define DRA7_UART4_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x158)
 148 #define DRA7_MCASP2_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x160)
 149 #define DRA7_MCASP3_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x168)
 150 #define DRA7_UART5_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x170)
 151 #define DRA7_MCASP5_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x178)
 152 #define DRA7_MCASP8_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x190)
 153 #define DRA7_MCASP4_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x198)
 154 #define DRA7_AES1_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
 155 #define DRA7_AES2_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
 156 #define DRA7_DES_CLKCTRL        _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
 157 #define DRA7_RNG_CLKCTRL        _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
 158 #define DRA7_SHAM_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
 159 #define DRA7_UART7_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
 160 #define DRA7_UART8_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
 161 #define DRA7_UART9_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
 162 #define DRA7_DCAN2_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
 163 #define DRA7_MCASP6_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x204)
 164 #define DRA7_MCASP7_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x208)
 165
 166 /* wkupaon clocks */
 167 #define DRA7_L4_WKUP_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
 168 #define DRA7_WD_TIMER2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x30)
 169 #define DRA7_GPIO1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x38)
 170 #define DRA7_TIMER1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x40)
 171 #define DRA7_TIMER12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x48)
 172 #define DRA7_COUNTER_32K_CLKCTRL        DRA7_CLKCTRL_INDEX(0x50)
 173 #define DRA7_UART10_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
 174 #define DRA7_DCAN1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x88)
 175 #define DRA7_ADC_CLKCTRL        DRA7_CLKCTRL_INDEX(0xa0)
 176
 177 /* XXX: Compatibility part end. */
 178
 179 /* mpu clocks */
 180 #define DRA7_MPU_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
 181
 182 /* dsp1 clocks */
 183 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
 184
 185 /* ipu1 clocks */
 186 #define DRA7_IPU1_MMU_IPU1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x20)
 187
 188 /* ipu clocks */
 189 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
 190 #define DRA7_IPU_CLKCTRL_INDEX(offset)  ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
 191 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
 192 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
 193 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
 194 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
 195 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
 196 #define DRA7_IPU_I2C5_CLKCTRL   DRA7_IPU_CLKCTRL_INDEX(0x78)
 197 #define DRA7_IPU_UART6_CLKCTRL  DRA7_IPU_CLKCTRL_INDEX(0x80)
 198
 199 /* dsp2 clocks */
 200 #define DRA7_DSP2_MMU0_DSP2_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
 201
 202 /* rtc clocks */
 203 #define DRA7_RTC_RTCSS_CLKCTRL  DRA7_CLKCTRL_INDEX(0x44)
 204
 205 /* vip clocks */
 206 #define DRA7_CAM_VIP1_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
 207 #define DRA7_CAM_VIP2_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
 208 #define DRA7_CAM_VIP3_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
 209
 210 /* vpe clocks */
 211 #define DRA7_VPE_CLKCTRL_OFFSET 0x60
 212 #define DRA7_VPE_CLKCTRL_INDEX(offset)  ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
 213 #define DRA7_VPE_VPE_CLKCTRL    DRA7_VPE_CLKCTRL_INDEX(0x64)
 214
 215 /* coreaon clocks */
 216 #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x28)
 217 #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x38)
 218
 219 /* l3main1 clocks */
 220 #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
 221 #define DRA7_L3MAIN1_GPMC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
 222 #define DRA7_L3MAIN1_TPCC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x70)
 223 #define DRA7_L3MAIN1_TPTC0_CLKCTRL      DRA7_CLKCTRL_INDEX(0x78)
 224 #define DRA7_L3MAIN1_TPTC1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x80)
 225 #define DRA7_L3MAIN1_VCP1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x88)
 226 #define DRA7_L3MAIN1_VCP2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x90)
 227
 228 /* ipu2 clocks */
 229 #define DRA7_IPU2_MMU_IPU2_CLKCTRL      DRA7_CLKCTRL_INDEX(0x20)
 230
 231 /* dma clocks */
 232 #define DRA7_DMA_DMA_SYSTEM_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
 233
 234 /* emif clocks */
 235 #define DRA7_EMIF_DMM_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
 236
 237 /* atl clocks */
 238 #define DRA7_ATL_CLKCTRL_OFFSET 0x0
 239 #define DRA7_ATL_CLKCTRL_INDEX(offset)  ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
 240 #define DRA7_ATL_ATL_CLKCTRL    DRA7_ATL_CLKCTRL_INDEX(0x0)
 241
 242 /* l4cfg clocks */
 243 #define DRA7_L4CFG_L4_CFG_CLKCTRL       DRA7_CLKCTRL_INDEX(0x20)
 244 #define DRA7_L4CFG_SPINLOCK_CLKCTRL     DRA7_CLKCTRL_INDEX(0x28)
 245 #define DRA7_L4CFG_MAILBOX1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x30)
 246 #define DRA7_L4CFG_MAILBOX2_CLKCTRL     DRA7_CLKCTRL_INDEX(0x48)
 247 #define DRA7_L4CFG_MAILBOX3_CLKCTRL     DRA7_CLKCTRL_INDEX(0x50)
 248 #define DRA7_L4CFG_MAILBOX4_CLKCTRL     DRA7_CLKCTRL_INDEX(0x58)
 249 #define DRA7_L4CFG_MAILBOX5_CLKCTRL     DRA7_CLKCTRL_INDEX(0x60)
 250 #define DRA7_L4CFG_MAILBOX6_CLKCTRL     DRA7_CLKCTRL_INDEX(0x68)
 251 #define DRA7_L4CFG_MAILBOX7_CLKCTRL     DRA7_CLKCTRL_INDEX(0x70)
 252 #define DRA7_L4CFG_MAILBOX8_CLKCTRL     DRA7_CLKCTRL_INDEX(0x78)
 253 #define DRA7_L4CFG_MAILBOX9_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
 254 #define DRA7_L4CFG_MAILBOX10_CLKCTRL    DRA7_CLKCTRL_INDEX(0x88)
 255 #define DRA7_L4CFG_MAILBOX11_CLKCTRL    DRA7_CLKCTRL_INDEX(0x90)
 256 #define DRA7_L4CFG_MAILBOX12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x98)
 257 #define DRA7_L4CFG_MAILBOX13_CLKCTRL    DRA7_CLKCTRL_INDEX(0xa0)
 258
 259 /* l3instr clocks */
 260 #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
 261 #define DRA7_L3INSTR_L3_INSTR_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
 262
 263 /* iva clocks */
 264 #define DRA7_IVA_CLKCTRL                DRA7_CLKCTRL_INDEX(0x20)
 265 #define DRA7_SL2IF_CLKCTRL              DRA7_CLKCTRL_INDEX(0x28)
 266
 267 /* dss clocks */
 268 #define DRA7_DSS_DSS_CORE_CLKCTRL       DRA7_CLKCTRL_INDEX(0x20)
 269 #define DRA7_DSS_BB2D_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
 270
 271 /* gpu clocks */
 272 #define DRA7_GPU_CLKCTRL                DRA7_CLKCTRL_INDEX(0x20)
 273
 274 /* l3init clocks */
 275 #define DRA7_L3INIT_MMC1_CLKCTRL        DRA7_CLKCTRL_INDEX(0x28)
 276 #define DRA7_L3INIT_MMC2_CLKCTRL        DRA7_CLKCTRL_INDEX(0x30)
 277 #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
 278 #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
 279 #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
 280 #define DRA7_L3INIT_SATA_CLKCTRL        DRA7_CLKCTRL_INDEX(0x88)
 281 #define DRA7_L3INIT_OCP2SCP1_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe0)
 282 #define DRA7_L3INIT_OCP2SCP3_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe8)
 283 #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
 284
 285 /* pcie clocks */
 286 #define DRA7_PCIE_CLKCTRL_OFFSET        0xb0
 287 #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
 288 #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
 289 #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
 290
 291 /* gmac clocks */
 292 #define DRA7_GMAC_CLKCTRL_OFFSET        0xd0
 293 #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
 294 #define DRA7_GMAC_GMAC_CLKCTRL  DRA7_GMAC_CLKCTRL_INDEX(0xd0)
 295
 296 /* l4per clocks */
 297 #define DRA7_L4PER_CLKCTRL_OFFSET       0x28
 298 #define DRA7_L4PER_CLKCTRL_INDEX(offset)        ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
 299 #define DRA7_L4PER_TIMER10_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0x28)
 300 #define DRA7_L4PER_TIMER11_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0x30)
 301 #define DRA7_L4PER_TIMER2_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x38)
 302 #define DRA7_L4PER_TIMER3_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x40)
 303 #define DRA7_L4PER_TIMER4_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x48)
 304 #define DRA7_L4PER_TIMER9_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x50)
 305 #define DRA7_L4PER_ELM_CLKCTRL  DRA7_L4PER_CLKCTRL_INDEX(0x58)
 306 #define DRA7_L4PER_GPIO2_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x60)
 307 #define DRA7_L4PER_GPIO3_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x68)
 308 #define DRA7_L4PER_GPIO4_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x70)
 309 #define DRA7_L4PER_GPIO5_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x78)
 310 #define DRA7_L4PER_GPIO6_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x80)
 311 #define DRA7_L4PER_HDQ1W_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x88)
 312 #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
 313 #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
 314 #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
 315 #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
 316 #define DRA7_L4PER_L4_PER1_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0xc0)
 317 #define DRA7_L4PER_MCSPI1_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0xf0)
 318 #define DRA7_L4PER_MCSPI2_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0xf8)
 319 #define DRA7_L4PER_MCSPI3_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x100)
 320 #define DRA7_L4PER_MCSPI4_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x108)
 321 #define DRA7_L4PER_GPIO7_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x110)
 322 #define DRA7_L4PER_GPIO8_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x118)
 323 #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
 324 #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
 325 #define DRA7_L4PER_UART1_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x140)
 326 #define DRA7_L4PER_UART2_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x148)
 327 #define DRA7_L4PER_UART3_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x150)
 328 #define DRA7_L4PER_UART4_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x158)
 329 #define DRA7_L4PER_UART5_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x170)
 330
 331 /* l4sec clocks */
 332 #define DRA7_L4SEC_CLKCTRL_OFFSET       0x1a0
 333 #define DRA7_L4SEC_CLKCTRL_INDEX(offset)        ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
 334 #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
 335 #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
 336 #define DRA7_L4SEC_DES_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
 337 #define DRA7_L4SEC_RNG_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
 338 #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
 339 #define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8)
 340
 341 /* l4per2 clocks */
 342 #define DRA7_L4PER2_CLKCTRL_OFFSET      0xc
 343 #define DRA7_L4PER2_CLKCTRL_INDEX(offset)       ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
 344 #define DRA7_L4PER2_L4_PER2_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0xc)
 345 #define DRA7_L4PER2_PRUSS1_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x18)
 346 #define DRA7_L4PER2_PRUSS2_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x20)
 347 #define DRA7_L4PER2_EPWMSS1_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0x90)
 348 #define DRA7_L4PER2_EPWMSS2_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0x98)
 349 #define DRA7_L4PER2_EPWMSS0_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
 350 #define DRA7_L4PER2_QSPI_CLKCTRL        DRA7_L4PER2_CLKCTRL_INDEX(0x138)
 351 #define DRA7_L4PER2_MCASP2_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x160)
 352 #define DRA7_L4PER2_MCASP3_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x168)
 353 #define DRA7_L4PER2_MCASP5_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x178)
 354 #define DRA7_L4PER2_MCASP8_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x190)
 355 #define DRA7_L4PER2_MCASP4_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x198)
 356 #define DRA7_L4PER2_UART7_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
 357 #define DRA7_L4PER2_UART8_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
 358 #define DRA7_L4PER2_UART9_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
 359 #define DRA7_L4PER2_DCAN2_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
 360 #define DRA7_L4PER2_MCASP6_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x204)
 361 #define DRA7_L4PER2_MCASP7_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x208)
 362
 363 /* l4per3 clocks */
 364 #define DRA7_L4PER3_CLKCTRL_OFFSET      0x14
 365 #define DRA7_L4PER3_CLKCTRL_INDEX(offset)       ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
 366 #define DRA7_L4PER3_L4_PER3_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0x14)
 367 #define DRA7_L4PER3_TIMER13_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
 368 #define DRA7_L4PER3_TIMER14_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
 369 #define DRA7_L4PER3_TIMER15_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
 370 #define DRA7_L4PER3_TIMER16_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0x130)
 371
 372 /* wkupaon clocks */
 373 #define DRA7_WKUPAON_L4_WKUP_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
 374 #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x30)
 375 #define DRA7_WKUPAON_GPIO1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x38)
 376 #define DRA7_WKUPAON_TIMER1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x40)
 377 #define DRA7_WKUPAON_TIMER12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x48)
 378 #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL        DRA7_CLKCTRL_INDEX(0x50)
 379 #define DRA7_WKUPAON_UART10_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
 380 #define DRA7_WKUPAON_DCAN1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x88)
 381 #define DRA7_WKUPAON_ADC_CLKCTRL        DRA7_CLKCTRL_INDEX(0xa0)
 382
 383 #endif