2 * OMAP Dual-Mode Timers
4 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
5 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
6 * Thara Gopinath <thara@ti.com>
8 * Platform device conversion and hwmod support.
10 * Copyright (C) 2005 Nokia Corporation
11 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
12 * PWM and clock framwork support by Timo Teras.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/delay.h>
35 #include <linux/platform_device.h>
37 #ifndef __CLOCKSOURCE_DMTIMER_H
38 #define __CLOCKSOURCE_DMTIMER_H
41 #define OMAP_TIMER_SRC_SYS_CLK 0x00
42 #define OMAP_TIMER_SRC_32_KHZ 0x01
43 #define OMAP_TIMER_SRC_EXT_CLK 0x02
45 /* timer interrupt enable bits */
46 #define OMAP_TIMER_INT_CAPTURE (1 << 2)
47 #define OMAP_TIMER_INT_OVERFLOW (1 << 1)
48 #define OMAP_TIMER_INT_MATCH (1 << 0)
51 #define OMAP_TIMER_TRIGGER_NONE 0x00
52 #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
53 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
55 /* posted mode types */
56 #define OMAP_TIMER_NONPOSTED 0x00
57 #define OMAP_TIMER_POSTED 0x01
59 /* timer capabilities used in hwmod database */
60 #define OMAP_TIMER_SECURE 0x80000000
61 #define OMAP_TIMER_ALWON 0x40000000
62 #define OMAP_TIMER_HAS_PWM 0x20000000
63 #define OMAP_TIMER_NEEDS_RESET 0x10000000
64 #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
69 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
70 * errata prevents us from using posted mode on these devices, unless the
71 * timer counter register is never read. For more details please refer to
72 * the OMAP3/4/5 errata documents.
74 #define OMAP_TIMER_ERRATA_I103_I767 0x80000000
97 struct omap_dm_timer {
102 void __iomem *io_base;
103 void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
104 void __iomem *irq_ena; /* irq enable */
105 void __iomem *irq_dis; /* irq disable, only on v2 ip */
106 void __iomem *pend; /* write pending */
107 void __iomem *func_base; /* function register base */
113 struct timer_regs context;
117 struct platform_device *pdev;
118 struct list_head node;
119 struct notifier_block nb;
122 int omap_dm_timer_reserve_systimer(int id);
123 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
125 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
127 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
129 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
131 int omap_dm_timers_active(void);
134 * Do not use the defines below, they are not needed. They should be only
135 * used by dmtimer.c and sys_timer related code.
139 * The interrupt registers are different between v1 and v2 ip.
140 * These registers are offsets from timer->iobase.
142 #define OMAP_TIMER_ID_OFFSET 0x00
143 #define OMAP_TIMER_OCP_CFG_OFFSET 0x10
145 #define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
146 #define OMAP_TIMER_V1_STAT_OFFSET 0x18
147 #define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
149 #define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
150 #define OMAP_TIMER_V2_IRQSTATUS 0x28
151 #define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
152 #define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
155 * The functional registers have a different base on v1 and v2 ip.
156 * These registers are offsets from timer->func_base. The func_base
157 * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
160 #define OMAP_TIMER_V2_FUNC_OFFSET 0x14
162 #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
163 #define _OMAP_TIMER_CTRL_OFFSET 0x24
164 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
165 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
166 #define OMAP_TIMER_CTRL_PT (1 << 12)
167 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
168 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
169 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
170 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
171 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
172 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
173 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
174 #define OMAP_TIMER_CTRL_POSTED (1 << 2)
175 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
176 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
177 #define _OMAP_TIMER_COUNTER_OFFSET 0x28
178 #define _OMAP_TIMER_LOAD_OFFSET 0x2c
179 #define _OMAP_TIMER_TRIGGER_OFFSET 0x30
180 #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
181 #define WP_NONE 0 /* no write pending bit */
182 #define WP_TCLR (1 << 0)
183 #define WP_TCRR (1 << 1)
184 #define WP_TLDR (1 << 2)
185 #define WP_TTGR (1 << 3)
186 #define WP_TMAR (1 << 4)
187 #define WP_TPIR (1 << 5)
188 #define WP_TNIR (1 << 6)
189 #define WP_TCVR (1 << 7)
190 #define WP_TOCR (1 << 8)
191 #define WP_TOWR (1 << 9)
192 #define _OMAP_TIMER_MATCH_OFFSET 0x38
193 #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
194 #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
195 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
196 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
197 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
198 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
199 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
200 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
202 /* register offsets with the write pending bit encoded */
205 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
206 | (WP_NONE << WPSHIFT))
208 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
209 | (WP_TCLR << WPSHIFT))
211 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
212 | (WP_TCRR << WPSHIFT))
214 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
215 | (WP_TLDR << WPSHIFT))
217 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
218 | (WP_TTGR << WPSHIFT))
220 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
221 | (WP_NONE << WPSHIFT))
223 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
224 | (WP_TMAR << WPSHIFT))
226 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
227 | (WP_NONE << WPSHIFT))
229 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
230 | (WP_NONE << WPSHIFT))
232 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
233 | (WP_NONE << WPSHIFT))
235 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
236 | (WP_TPIR << WPSHIFT))
238 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
239 | (WP_TNIR << WPSHIFT))
241 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
242 | (WP_TCVR << WPSHIFT))
244 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \
245 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
247 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
248 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
250 #endif /* __CLOCKSOURCE_DMTIMER_H */