1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/watchdog.h>
21 #include <linux/of_device.h>
31 static const u32 reg_offset_data_apcs_tmr[] = {
35 [WDT_BARK_TIME] = 0x4C,
36 [WDT_BITE_TIME] = 0x5C,
39 static const u32 reg_offset_data_kpss[] = {
43 [WDT_BARK_TIME] = 0x10,
44 [WDT_BITE_TIME] = 0x14,
48 struct watchdog_device wdd;
55 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
57 return wdt->base + wdt->layout[reg];
61 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
63 return container_of(wdd, struct qcom_wdt, wdd);
66 static int qcom_wdt_start(struct watchdog_device *wdd)
68 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
70 writel(0, wdt_addr(wdt, WDT_EN));
71 writel(1, wdt_addr(wdt, WDT_RST));
72 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
73 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
74 writel(1, wdt_addr(wdt, WDT_EN));
78 static int qcom_wdt_stop(struct watchdog_device *wdd)
80 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
82 writel(0, wdt_addr(wdt, WDT_EN));
86 static int qcom_wdt_ping(struct watchdog_device *wdd)
88 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
90 writel(1, wdt_addr(wdt, WDT_RST));
94 static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
97 wdd->timeout = timeout;
98 return qcom_wdt_start(wdd);
101 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
104 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
108 * Trigger watchdog bite:
109 * Setup BITE_TIME to be 128ms, and enable WDT.
111 timeout = 128 * wdt->rate / 1000;
113 writel(0, wdt_addr(wdt, WDT_EN));
114 writel(1, wdt_addr(wdt, WDT_RST));
115 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
116 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
117 writel(1, wdt_addr(wdt, WDT_EN));
120 * Actually make sure the above sequence hits hardware before sleeping.
128 static const struct watchdog_ops qcom_wdt_ops = {
129 .start = qcom_wdt_start,
130 .stop = qcom_wdt_stop,
131 .ping = qcom_wdt_ping,
132 .set_timeout = qcom_wdt_set_timeout,
133 .restart = qcom_wdt_restart,
134 .owner = THIS_MODULE,
137 static const struct watchdog_info qcom_wdt_info = {
138 .options = WDIOF_KEEPALIVEPING
142 .identity = KBUILD_MODNAME,
145 static void qcom_clk_disable_unprepare(void *data)
147 clk_disable_unprepare(data);
150 static int qcom_wdt_probe(struct platform_device *pdev)
152 struct device *dev = &pdev->dev;
153 struct qcom_wdt *wdt;
154 struct resource *res;
155 struct device_node *np = dev->of_node;
160 regs = of_device_get_match_data(dev);
162 dev_err(dev, "Unsupported QCOM WDT module\n");
166 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
174 /* We use CPU0's DGT for the watchdog */
175 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
178 res->start += percpu_offset;
179 res->end += percpu_offset;
181 wdt->base = devm_ioremap_resource(dev, res);
182 if (IS_ERR(wdt->base))
183 return PTR_ERR(wdt->base);
185 wdt->clk = devm_clk_get(dev, NULL);
186 if (IS_ERR(wdt->clk)) {
187 dev_err(dev, "failed to get input clock\n");
188 return PTR_ERR(wdt->clk);
191 ret = clk_prepare_enable(wdt->clk);
193 dev_err(dev, "failed to setup clock\n");
196 ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare,
202 * We use the clock rate to calculate the max timeout, so ensure it's
203 * not zero to avoid a divide-by-zero exception.
205 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
206 * that it would bite before a second elapses it's usefulness is
207 * limited. Bail if this is the case.
209 wdt->rate = clk_get_rate(wdt->clk);
210 if (wdt->rate == 0 ||
211 wdt->rate > 0x10000000U) {
212 dev_err(dev, "invalid clock rate\n");
216 wdt->wdd.info = &qcom_wdt_info;
217 wdt->wdd.ops = &qcom_wdt_ops;
218 wdt->wdd.min_timeout = 1;
219 wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
220 wdt->wdd.parent = dev;
223 if (readl(wdt_addr(wdt, WDT_STS)) & 1)
224 wdt->wdd.bootstatus = WDIOF_CARDRESET;
227 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
228 * default, unless the max timeout is less than 30 seconds, then use
231 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
232 watchdog_init_timeout(&wdt->wdd, 0, dev);
234 ret = devm_watchdog_register_device(dev, &wdt->wdd);
236 dev_err(dev, "failed to register watchdog\n");
240 platform_set_drvdata(pdev, wdt);
244 static int __maybe_unused qcom_wdt_suspend(struct device *dev)
246 struct qcom_wdt *wdt = dev_get_drvdata(dev);
248 if (watchdog_active(&wdt->wdd))
249 qcom_wdt_stop(&wdt->wdd);
254 static int __maybe_unused qcom_wdt_resume(struct device *dev)
256 struct qcom_wdt *wdt = dev_get_drvdata(dev);
258 if (watchdog_active(&wdt->wdd))
259 qcom_wdt_start(&wdt->wdd);
264 static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
266 static const struct of_device_id qcom_wdt_of_table[] = {
267 { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
268 { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
269 { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
272 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
274 static struct platform_driver qcom_watchdog_driver = {
275 .probe = qcom_wdt_probe,
277 .name = KBUILD_MODNAME,
278 .of_match_table = qcom_wdt_of_table,
279 .pm = &qcom_wdt_pm_ops,
282 module_platform_driver(qcom_watchdog_driver);
284 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
285 MODULE_LICENSE("GPL v2");