11a13887a71d810ece704c0d1110ee0afd0072e6
[sfrench/cifs-2.6.git] / drivers / usb / renesas_usbhs / rcar3.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas USB driver R-Car Gen. 3 initialization and power control
4  *
5  * Copyright (C) 2016 Renesas Electronics Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  */
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include "common.h"
16 #include "rcar3.h"
17
18 #define LPSTS           0x102
19 #define UGCTRL          0x180   /* 32-bit register */
20 #define UGCTRL2         0x184   /* 32-bit register */
21 #define UGSTS           0x188   /* 32-bit register */
22
23 /* Low Power Status register (LPSTS) */
24 #define LPSTS_SUSPM     0x4000
25
26 /* R-Car D3 only: USB General control register (UGCTRL) */
27 #define UGCTRL_PLLRESET         0x00000001
28 #define UGCTRL_CONNECT          0x00000004
29
30 /*
31  * USB General control register 2 (UGCTRL2)
32  * Remarks: bit[31:11] and bit[9:6] should be 0
33  */
34 #define UGCTRL2_RESERVED_3      0x00000001      /* bit[3:0] should be B'0001 */
35 #define UGCTRL2_USB0SEL_HSUSB   0x00000020
36 #define UGCTRL2_USB0SEL_OTG     0x00000030
37 #define UGCTRL2_VBUSSEL         0x00000400
38
39 /* R-Car D3 only: USB General status register (UGSTS) */
40 #define UGSTS_LOCK              0x00000100
41
42 static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
43 {
44         iowrite32(data, priv->base + reg);
45 }
46
47 static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
48 {
49         return ioread32(priv->base + reg);
50 }
51
52 static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
53                                 void __iomem *base, int enable)
54 {
55         struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
56
57         usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 | UGCTRL2_USB0SEL_OTG |
58                       UGCTRL2_VBUSSEL);
59
60         if (enable) {
61                 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
62                 /* The controller on R-Car Gen3 needs to wait up to 45 usec */
63                 udelay(45);
64         } else {
65                 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
66         }
67
68         return 0;
69 }
70
71 /* R-Car D3 needs to release UGCTRL.PLLRESET */
72 static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
73                                           void __iomem *base, int enable)
74 {
75         struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
76         u32 val;
77         int timeout = 1000;
78
79         if (enable) {
80                 usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */
81                 usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 |
82                               UGCTRL2_USB0SEL_HSUSB);
83
84                 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
85                 do {
86                         val = usbhs_read32(priv, UGSTS);
87                         udelay(1);
88                 } while (!(val & UGSTS_LOCK) && timeout--);
89                 usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT);
90         } else {
91                 usbhs_write32(priv, UGCTRL, 0);
92                 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
93                 usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET);
94         }
95
96         return 0;
97 }
98
99 static int usbhs_rcar3_get_id(struct platform_device *pdev)
100 {
101         return USBHS_GADGET;
102 }
103
104 const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
105         .power_ctrl = usbhs_rcar3_power_ctrl,
106         .get_id = usbhs_rcar3_get_id,
107 };
108
109 const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops = {
110         .power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
111         .get_id = usbhs_rcar3_get_id,
112 };