1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
77 if (result == U32_MAX) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd *xhci)
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
97 cmd = readl(&xhci->op_regs->command);
99 writel(cmd, &xhci->op_regs->command);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd *xhci)
113 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
116 ret = xhci_handshake(&xhci->op_regs->status,
117 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 xhci_warn(xhci, "Host halt failed, %d\n", ret);
122 xhci->xhc_state |= XHCI_STATE_HALTED;
123 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
128 * Set the run bit and wait for the host to be running.
130 int xhci_start(struct xhci_hcd *xhci)
135 temp = readl(&xhci->op_regs->command);
137 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
139 writel(temp, &xhci->op_regs->command);
142 * Wait for the HCHalted Status bit to be 0 to indicate the host is
145 ret = xhci_handshake(&xhci->op_regs->status,
146 STS_HALT, 0, XHCI_MAX_HALT_USEC);
147 if (ret == -ETIMEDOUT)
148 xhci_err(xhci, "Host took too long to start, "
149 "waited %u microseconds.\n",
152 /* clear state flags. Including dying, halted or removing */
161 * This resets pipelines, timers, counters, state machines, etc.
162 * Transactions will be terminated immediately, and operational registers
163 * will be set to their defaults.
165 int xhci_reset(struct xhci_hcd *xhci)
171 state = readl(&xhci->op_regs->status);
173 if (state == ~(u32)0) {
174 xhci_warn(xhci, "Host not accessible, reset failed.\n");
178 if ((state & STS_HALT) == 0) {
179 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
183 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
184 command = readl(&xhci->op_regs->command);
185 command |= CMD_RESET;
186 writel(command, &xhci->op_regs->command);
188 /* Existing Intel xHCI controllers require a delay of 1 mS,
189 * after setting the CMD_RESET bit, and before accessing any
190 * HC registers. This allows the HC to complete the
191 * reset operation and be ready for HC register access.
192 * Without this delay, the subsequent HC register access,
193 * may result in a system hang very rarely.
195 if (xhci->quirks & XHCI_INTEL_HOST)
198 ret = xhci_handshake(&xhci->op_regs->command,
199 CMD_RESET, 0, 10 * 1000 * 1000);
203 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
204 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
206 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
207 "Wait for controller to be ready for doorbell rings");
209 * xHCI cannot write to any doorbells or operational registers other
210 * than status until the "Controller Not Ready" flag is cleared.
212 ret = xhci_handshake(&xhci->op_regs->status,
213 STS_CNR, 0, 10 * 1000 * 1000);
215 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
216 xhci->usb2_rhub.bus_state.suspended_ports = 0;
217 xhci->usb2_rhub.bus_state.resuming_ports = 0;
218 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb3_rhub.bus_state.suspended_ports = 0;
220 xhci->usb3_rhub.bus_state.resuming_ports = 0;
225 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
227 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
254 writel(val, &xhci->op_regs->command);
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
259 writel(val, &xhci->op_regs->status);
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
269 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
270 ARRAY_SIZE(xhci->run_regs->ir_set));
272 for (i = 0; i < intrs; i++) {
273 struct xhci_intr_reg __iomem *ir;
275 ir = &xhci->run_regs->ir_set[i];
276 val = xhci_read_64(xhci, &ir->erst_base);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_base);
279 val= xhci_read_64(xhci, &ir->erst_dequeue);
280 if (upper_32_bits(val))
281 xhci_write_64(xhci, 0, &ir->erst_dequeue);
284 /* Wait for the fault to appear. It will be cleared on reset */
285 err = xhci_handshake(&xhci->op_regs->status,
286 STS_FATAL, STS_FATAL,
289 xhci_info(xhci, "Fault detected\n");
292 #ifdef CONFIG_USB_PCI
296 static int xhci_setup_msi(struct xhci_hcd *xhci)
300 * TODO:Check with MSI Soc for sysdev
302 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
304 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
306 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
307 "failed to allocate MSI entry");
311 ret = request_irq(pdev->irq, xhci_msi_irq,
312 0, "xhci_hcd", xhci_to_hcd(xhci));
314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
315 "disable MSI interrupt");
316 pci_free_irq_vectors(pdev);
325 static int xhci_setup_msix(struct xhci_hcd *xhci)
328 struct usb_hcd *hcd = xhci_to_hcd(xhci);
329 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
332 * calculate number of msi-x vectors supported.
333 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
334 * with max number of interrupters based on the xhci HCSPARAMS1.
335 * - num_online_cpus: maximum msi-x vectors per CPUs core.
336 * Add additional 1 vector to ensure always available interrupt.
338 xhci->msix_count = min(num_online_cpus() + 1,
339 HCS_MAX_INTRS(xhci->hcs_params1));
341 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
344 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
345 "Failed to enable MSI-X");
349 for (i = 0; i < xhci->msix_count; i++) {
350 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
351 "xhci_hcd", xhci_to_hcd(xhci));
356 hcd->msix_enabled = 1;
360 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
362 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
363 pci_free_irq_vectors(pdev);
367 /* Free any IRQs and disable MSI-X */
368 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
370 struct usb_hcd *hcd = xhci_to_hcd(xhci);
371 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
373 if (xhci->quirks & XHCI_PLAT)
376 /* return if using legacy interrupt */
380 if (hcd->msix_enabled) {
383 for (i = 0; i < xhci->msix_count; i++)
384 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
386 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
389 pci_free_irq_vectors(pdev);
390 hcd->msix_enabled = 0;
393 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
395 struct usb_hcd *hcd = xhci_to_hcd(xhci);
397 if (hcd->msix_enabled) {
398 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
401 for (i = 0; i < xhci->msix_count; i++)
402 synchronize_irq(pci_irq_vector(pdev, i));
406 static int xhci_try_enable_msi(struct usb_hcd *hcd)
408 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
409 struct pci_dev *pdev;
412 /* The xhci platform device has set up IRQs through usb_add_hcd. */
413 if (xhci->quirks & XHCI_PLAT)
416 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
418 * Some Fresco Logic host controllers advertise MSI, but fail to
419 * generate interrupts. Don't even try to enable MSI.
421 if (xhci->quirks & XHCI_BROKEN_MSI)
424 /* unregister the legacy interrupt */
426 free_irq(hcd->irq, hcd);
429 ret = xhci_setup_msix(xhci);
431 /* fall back to msi*/
432 ret = xhci_setup_msi(xhci);
435 hcd->msi_enabled = 1;
440 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
445 if (!strlen(hcd->irq_descr))
446 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
447 hcd->driver->description, hcd->self.busnum);
449 /* fall back to legacy interrupt*/
450 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
451 hcd->irq_descr, hcd);
453 xhci_err(xhci, "request interrupt %d failed\n",
457 hcd->irq = pdev->irq;
463 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
468 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
472 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
478 static void compliance_mode_recovery(struct timer_list *t)
480 struct xhci_hcd *xhci;
482 struct xhci_hub *rhub;
486 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
487 rhub = &xhci->usb3_rhub;
489 for (i = 0; i < rhub->num_ports; i++) {
490 temp = readl(rhub->ports[i]->addr);
491 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
493 * Compliance Mode Detected. Letting USB Core
494 * handle the Warm Reset
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Compliance mode detected->port %d",
499 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
500 "Attempting compliance mode recovery");
501 hcd = xhci->shared_hcd;
503 if (hcd->state == HC_STATE_SUSPENDED)
504 usb_hcd_resume_root_hub(hcd);
506 usb_hcd_poll_rh_status(hcd);
510 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
511 mod_timer(&xhci->comp_mode_recovery_timer,
512 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
516 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
517 * that causes ports behind that hardware to enter compliance mode sometimes.
518 * The quirk creates a timer that polls every 2 seconds the link state of
519 * each host controller's port and recovers it by issuing a Warm reset
520 * if Compliance mode is detected, otherwise the port will become "dead" (no
521 * device connections or disconnections will be detected anymore). Becasue no
522 * status event is generated when entering compliance mode (per xhci spec),
523 * this quirk is needed on systems that have the failing hardware installed.
525 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
527 xhci->port_status_u0 = 0;
528 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
530 xhci->comp_mode_recovery_timer.expires = jiffies +
531 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
533 add_timer(&xhci->comp_mode_recovery_timer);
534 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
535 "Compliance mode recovery timer initialized");
539 * This function identifies the systems that have installed the SN65LVPE502CP
540 * USB3.0 re-driver and that need the Compliance Mode Quirk.
542 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
544 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
546 const char *dmi_product_name, *dmi_sys_vendor;
548 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
549 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
550 if (!dmi_product_name || !dmi_sys_vendor)
553 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
556 if (strstr(dmi_product_name, "Z420") ||
557 strstr(dmi_product_name, "Z620") ||
558 strstr(dmi_product_name, "Z820") ||
559 strstr(dmi_product_name, "Z1 Workstation"))
565 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
567 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
572 * Initialize memory for HCD and xHC (one-time init).
574 * Program the PAGESIZE register, initialize the device context array, create
575 * device contexts (?), set up a command ring segment (or two?), create event
576 * ring (one for now).
578 static int xhci_init(struct usb_hcd *hcd)
580 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
583 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
584 spin_lock_init(&xhci->lock);
585 if (xhci->hci_version == 0x95 && link_quirk) {
586 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
587 "QUIRK: Not clearing Link TRB chain bits.");
588 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
590 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
591 "xHCI doesn't need link TRB QUIRK");
593 retval = xhci_mem_init(xhci, GFP_KERNEL);
594 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
596 /* Initializing Compliance Mode Recovery Data If Needed */
597 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
598 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
599 compliance_mode_recovery_timer_init(xhci);
605 /*-------------------------------------------------------------------------*/
608 static int xhci_run_finished(struct xhci_hcd *xhci)
610 if (xhci_start(xhci)) {
614 xhci->shared_hcd->state = HC_STATE_RUNNING;
615 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
617 if (xhci->quirks & XHCI_NEC_HOST)
618 xhci_ring_cmd_db(xhci);
620 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
621 "Finished xhci_run for USB3 roothub");
626 * Start the HC after it was halted.
628 * This function is called by the USB core when the HC driver is added.
629 * Its opposite is xhci_stop().
631 * xhci_init() must be called once before this function can be called.
632 * Reset the HC, enable device slot contexts, program DCBAAP, and
633 * set command ring pointer and event ring pointer.
635 * Setup MSI-X vectors and enable interrupts.
637 int xhci_run(struct usb_hcd *hcd)
642 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
644 /* Start the xHCI host controller running only after the USB 2.0 roothub
648 hcd->uses_new_polling = 1;
649 if (!usb_hcd_is_primary_hcd(hcd))
650 return xhci_run_finished(xhci);
652 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
654 ret = xhci_try_enable_msi(hcd);
658 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
659 temp_64 &= ~ERST_PTR_MASK;
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
663 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
664 "// Set the interrupt modulation register");
665 temp = readl(&xhci->ir_set->irq_control);
666 temp &= ~ER_IRQ_INTERVAL_MASK;
667 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
668 writel(temp, &xhci->ir_set->irq_control);
670 /* Set the HCD state before we enable the irqs */
671 temp = readl(&xhci->op_regs->command);
673 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
674 "// Enable interrupts, cmd = 0x%x.", temp);
675 writel(temp, &xhci->op_regs->command);
677 temp = readl(&xhci->ir_set->irq_pending);
678 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
679 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
680 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
681 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
683 if (xhci->quirks & XHCI_NEC_HOST) {
684 struct xhci_command *command;
686 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
690 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
691 TRB_TYPE(TRB_NEC_GET_FW));
693 xhci_free_command(xhci, command);
695 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
696 "Finished xhci_run for USB2 roothub");
700 xhci_debugfs_init(xhci);
704 EXPORT_SYMBOL_GPL(xhci_run);
709 * This function is called by the USB core when the HC driver is removed.
710 * Its opposite is xhci_run().
712 * Disable device contexts, disable IRQs, and quiesce the HC.
713 * Reset the HC, finish any completed transactions, and cleanup memory.
715 static void xhci_stop(struct usb_hcd *hcd)
718 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
720 mutex_lock(&xhci->mutex);
722 /* Only halt host and free memory after both hcds are removed */
723 if (!usb_hcd_is_primary_hcd(hcd)) {
724 mutex_unlock(&xhci->mutex);
730 spin_lock_irq(&xhci->lock);
731 xhci->xhc_state |= XHCI_STATE_HALTED;
732 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
735 spin_unlock_irq(&xhci->lock);
737 xhci_cleanup_msix(xhci);
739 /* Deleting Compliance Mode Recovery Timer */
740 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
741 (!(xhci_all_ports_seen_u0(xhci)))) {
742 del_timer_sync(&xhci->comp_mode_recovery_timer);
743 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
744 "%s: compliance mode recovery timer deleted",
748 if (xhci->quirks & XHCI_AMD_PLL_FIX)
751 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
752 "// Disabling event ring interrupts");
753 temp = readl(&xhci->op_regs->status);
754 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
755 temp = readl(&xhci->ir_set->irq_pending);
756 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
759 xhci_mem_cleanup(xhci);
760 xhci_debugfs_exit(xhci);
761 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
762 "xhci_stop completed - status = %x",
763 readl(&xhci->op_regs->status));
764 mutex_unlock(&xhci->mutex);
768 * Shutdown HC (not bus-specific)
770 * This is called when the machine is rebooting or halting. We assume that the
771 * machine will be powered off, and the HC's internal state will be reset.
772 * Don't bother to free memory.
774 * This will only ever be called with the main usb_hcd (the USB3 roothub).
776 void xhci_shutdown(struct usb_hcd *hcd)
778 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
780 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
781 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
783 spin_lock_irq(&xhci->lock);
785 /* Workaround for spurious wakeups at shutdown with HSW */
786 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
788 spin_unlock_irq(&xhci->lock);
790 xhci_cleanup_msix(xhci);
792 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
793 "xhci_shutdown completed - status = %x",
794 readl(&xhci->op_regs->status));
796 EXPORT_SYMBOL_GPL(xhci_shutdown);
799 static void xhci_save_registers(struct xhci_hcd *xhci)
801 xhci->s3.command = readl(&xhci->op_regs->command);
802 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
803 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
804 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
805 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
806 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
807 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
808 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
809 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
812 static void xhci_restore_registers(struct xhci_hcd *xhci)
814 writel(xhci->s3.command, &xhci->op_regs->command);
815 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
816 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
817 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
818 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
819 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
820 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
821 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
822 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
825 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
829 /* step 2: initialize command ring buffer */
830 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
831 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
832 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
833 xhci->cmd_ring->dequeue) &
834 (u64) ~CMD_RING_RSVD_BITS) |
835 xhci->cmd_ring->cycle_state;
836 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
837 "// Setting command ring address to 0x%llx",
838 (long unsigned long) val_64);
839 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
843 * The whole command ring must be cleared to zero when we suspend the host.
845 * The host doesn't save the command ring pointer in the suspend well, so we
846 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
847 * aligned, because of the reserved bits in the command ring dequeue pointer
848 * register. Therefore, we can't just set the dequeue pointer back in the
849 * middle of the ring (TRBs are 16-byte aligned).
851 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
853 struct xhci_ring *ring;
854 struct xhci_segment *seg;
856 ring = xhci->cmd_ring;
860 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
861 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
862 cpu_to_le32(~TRB_CYCLE);
864 } while (seg != ring->deq_seg);
866 /* Reset the software enqueue and dequeue pointers */
867 ring->deq_seg = ring->first_seg;
868 ring->dequeue = ring->first_seg->trbs;
869 ring->enq_seg = ring->deq_seg;
870 ring->enqueue = ring->dequeue;
872 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
874 * Ring is now zeroed, so the HW should look for change of ownership
875 * when the cycle bit is set to 1.
877 ring->cycle_state = 1;
880 * Reset the hardware dequeue pointer.
881 * Yes, this will need to be re-written after resume, but we're paranoid
882 * and want to make sure the hardware doesn't access bogus memory
883 * because, say, the BIOS or an SMI started the host without changing
884 * the command ring pointers.
886 xhci_set_cmd_ring_deq(xhci);
890 * Disable port wake bits if do_wakeup is not set.
892 * Also clear a possible internal port wake state left hanging for ports that
893 * detected termination but never successfully enumerated (trained to 0U).
894 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
895 * at enumeration clears this wake, force one here as well for unconnected ports
898 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
899 struct xhci_hub *rhub,
906 spin_lock_irqsave(&xhci->lock, flags);
908 for (i = 0; i < rhub->num_ports; i++) {
909 portsc = readl(rhub->ports[i]->addr);
910 t1 = xhci_port_state_to_neutral(portsc);
913 /* clear wake bits if do_wake is not set */
915 t2 &= ~PORT_WAKE_BITS;
917 /* Don't touch csc bit if connected or connect change is set */
918 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
922 writel(t2, rhub->ports[i]->addr);
923 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
924 rhub->hcd->self.busnum, i + 1, portsc, t2);
927 spin_unlock_irqrestore(&xhci->lock, flags);
930 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
932 struct xhci_port **ports;
937 status = readl(&xhci->op_regs->status);
938 if (status & STS_EINT)
941 * Checking STS_EINT is not enough as there is a lag between a change
942 * bit being set and the Port Status Change Event that it generated
943 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
946 port_index = xhci->usb2_rhub.num_ports;
947 ports = xhci->usb2_rhub.ports;
948 while (port_index--) {
949 portsc = readl(ports[port_index]->addr);
950 if (portsc & PORT_CHANGE_MASK ||
951 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
954 port_index = xhci->usb3_rhub.num_ports;
955 ports = xhci->usb3_rhub.ports;
956 while (port_index--) {
957 portsc = readl(ports[port_index]->addr);
958 if (portsc & PORT_CHANGE_MASK ||
959 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
966 * Stop HC (not bus-specific)
968 * This is called when the machine transition into S3/S4 mode.
971 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
974 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
975 struct usb_hcd *hcd = xhci_to_hcd(xhci);
982 if (hcd->state != HC_STATE_SUSPENDED ||
983 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
986 /* Clear root port wake on bits if wakeup not allowed. */
987 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
988 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
990 if (!HCD_HW_ACCESSIBLE(hcd))
993 xhci_dbc_suspend(xhci);
995 /* Don't poll the roothubs on bus suspend. */
996 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
997 __func__, hcd->self.busnum);
998 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
999 del_timer_sync(&hcd->rh_timer);
1000 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1001 del_timer_sync(&xhci->shared_hcd->rh_timer);
1003 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1004 usleep_range(1000, 1500);
1006 spin_lock_irq(&xhci->lock);
1007 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1008 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1009 /* step 1: stop endpoint */
1010 /* skipped assuming that port suspend has done */
1012 /* step 2: clear Run/Stop bit */
1013 command = readl(&xhci->op_regs->command);
1014 command &= ~CMD_RUN;
1015 writel(command, &xhci->op_regs->command);
1017 /* Some chips from Fresco Logic need an extraordinary delay */
1018 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1020 if (xhci_handshake(&xhci->op_regs->status,
1021 STS_HALT, STS_HALT, delay)) {
1022 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1023 spin_unlock_irq(&xhci->lock);
1026 xhci_clear_command_ring(xhci);
1028 /* step 3: save registers */
1029 xhci_save_registers(xhci);
1031 /* step 4: set CSS flag */
1032 command = readl(&xhci->op_regs->command);
1034 writel(command, &xhci->op_regs->command);
1035 xhci->broken_suspend = 0;
1036 if (xhci_handshake(&xhci->op_regs->status,
1037 STS_SAVE, 0, 20 * 1000)) {
1039 * AMD SNPS xHC 3.0 occasionally does not clear the
1040 * SSS bit of USBSTS and when driver tries to poll
1041 * to see if the xHC clears BIT(8) which never happens
1042 * and driver assumes that controller is not responding
1043 * and times out. To workaround this, its good to check
1044 * if SRE and HCE bits are not set (as per xhci
1045 * Section 5.4.2) and bypass the timeout.
1047 res = readl(&xhci->op_regs->status);
1048 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1049 (((res & STS_SRE) == 0) &&
1050 ((res & STS_HCE) == 0))) {
1051 xhci->broken_suspend = 1;
1053 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1054 spin_unlock_irq(&xhci->lock);
1058 spin_unlock_irq(&xhci->lock);
1061 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1062 * is about to be suspended.
1064 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1065 (!(xhci_all_ports_seen_u0(xhci)))) {
1066 del_timer_sync(&xhci->comp_mode_recovery_timer);
1067 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1068 "%s: compliance mode recovery timer deleted",
1072 /* step 5: remove core well power */
1073 /* synchronize irq when using MSI-X */
1074 xhci_msix_sync_irqs(xhci);
1078 EXPORT_SYMBOL_GPL(xhci_suspend);
1081 * start xHC (not bus-specific)
1083 * This is called when the machine transition from S3/S4 mode.
1086 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1088 u32 command, temp = 0;
1089 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1090 struct usb_hcd *secondary_hcd;
1092 bool comp_timer_running = false;
1093 bool pending_portevent = false;
1094 bool reinit_xhc = false;
1099 /* Wait a bit if either of the roothubs need to settle from the
1100 * transition into bus suspend.
1103 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1104 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1107 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1108 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1110 spin_lock_irq(&xhci->lock);
1112 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1117 * Some controllers might lose power during suspend, so wait
1118 * for controller not ready bit to clear, just as in xHC init.
1120 retval = xhci_handshake(&xhci->op_regs->status,
1121 STS_CNR, 0, 10 * 1000 * 1000);
1123 xhci_warn(xhci, "Controller not ready at resume %d\n",
1125 spin_unlock_irq(&xhci->lock);
1128 /* step 1: restore register */
1129 xhci_restore_registers(xhci);
1130 /* step 2: initialize command ring buffer */
1131 xhci_set_cmd_ring_deq(xhci);
1132 /* step 3: restore state and start state*/
1133 /* step 3: set CRS flag */
1134 command = readl(&xhci->op_regs->command);
1136 writel(command, &xhci->op_regs->command);
1138 * Some controllers take up to 55+ ms to complete the controller
1139 * restore so setting the timeout to 100ms. Xhci specification
1140 * doesn't mention any timeout value.
1142 if (xhci_handshake(&xhci->op_regs->status,
1143 STS_RESTORE, 0, 100 * 1000)) {
1144 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1145 spin_unlock_irq(&xhci->lock);
1150 temp = readl(&xhci->op_regs->status);
1152 /* re-initialize the HC on Restore Error, or Host Controller Error */
1153 if (temp & (STS_SRE | STS_HCE)) {
1155 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1159 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1160 !(xhci_all_ports_seen_u0(xhci))) {
1161 del_timer_sync(&xhci->comp_mode_recovery_timer);
1162 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1163 "Compliance Mode Recovery Timer deleted!");
1166 /* Let the USB core know _both_ roothubs lost power. */
1167 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1168 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1170 xhci_dbg(xhci, "Stop HCD\n");
1172 xhci_zero_64b_regs(xhci);
1173 retval = xhci_reset(xhci);
1174 spin_unlock_irq(&xhci->lock);
1177 xhci_cleanup_msix(xhci);
1179 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1180 temp = readl(&xhci->op_regs->status);
1181 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1182 temp = readl(&xhci->ir_set->irq_pending);
1183 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1185 xhci_dbg(xhci, "cleaning up memory\n");
1186 xhci_mem_cleanup(xhci);
1187 xhci_debugfs_exit(xhci);
1188 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1189 readl(&xhci->op_regs->status));
1191 /* USB core calls the PCI reinit and start functions twice:
1192 * first with the primary HCD, and then with the secondary HCD.
1193 * If we don't do the same, the host will never be started.
1195 if (!usb_hcd_is_primary_hcd(hcd))
1196 secondary_hcd = hcd;
1198 secondary_hcd = xhci->shared_hcd;
1200 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1201 retval = xhci_init(hcd->primary_hcd);
1204 comp_timer_running = true;
1206 xhci_dbg(xhci, "Start the primary HCD\n");
1207 retval = xhci_run(hcd->primary_hcd);
1209 xhci_dbg(xhci, "Start the secondary HCD\n");
1210 retval = xhci_run(secondary_hcd);
1212 hcd->state = HC_STATE_SUSPENDED;
1213 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1217 /* step 4: set Run/Stop bit */
1218 command = readl(&xhci->op_regs->command);
1220 writel(command, &xhci->op_regs->command);
1221 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1224 /* step 5: walk topology and initialize portsc,
1225 * portpmsc and portli
1227 /* this is done in bus_resume */
1229 /* step 6: restart each of the previously
1230 * Running endpoints by ringing their doorbells
1233 spin_unlock_irq(&xhci->lock);
1235 xhci_dbc_resume(xhci);
1240 * Resume roothubs only if there are pending events.
1241 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1242 * the first wake signalling failed, give it that chance.
1244 pending_portevent = xhci_pending_portevent(xhci);
1245 if (!pending_portevent) {
1247 pending_portevent = xhci_pending_portevent(xhci);
1250 if (pending_portevent) {
1251 usb_hcd_resume_root_hub(xhci->shared_hcd);
1252 usb_hcd_resume_root_hub(hcd);
1256 * If system is subject to the Quirk, Compliance Mode Timer needs to
1257 * be re-initialized Always after a system resume. Ports are subject
1258 * to suffer the Compliance Mode issue again. It doesn't matter if
1259 * ports have entered previously to U0 before system's suspension.
1261 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1262 compliance_mode_recovery_timer_init(xhci);
1264 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1265 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1267 /* Re-enable port polling. */
1268 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1269 __func__, hcd->self.busnum);
1270 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1271 usb_hcd_poll_rh_status(xhci->shared_hcd);
1272 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1273 usb_hcd_poll_rh_status(hcd);
1277 EXPORT_SYMBOL_GPL(xhci_resume);
1278 #endif /* CONFIG_PM */
1280 /*-------------------------------------------------------------------------*/
1282 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1286 unsigned int buf_len;
1287 enum dma_data_direction dir;
1289 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1290 buf_len = urb->transfer_buffer_length;
1292 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1293 dev_to_node(hcd->self.sysdev));
1295 if (usb_urb_dir_out(urb))
1296 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1299 urb->transfer_buffer = temp;
1300 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1301 urb->transfer_buffer,
1302 urb->transfer_buffer_length,
1305 if (dma_mapping_error(hcd->self.sysdev,
1306 urb->transfer_dma)) {
1310 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1316 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1321 unsigned int len = 0;
1322 unsigned int trb_size;
1323 unsigned int max_pkt;
1324 struct scatterlist *sg;
1325 struct scatterlist *tail_sg;
1328 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1333 if (urb->dev->speed >= USB_SPEED_SUPER)
1334 trb_size = TRB_CACHE_SIZE_SS;
1336 trb_size = TRB_CACHE_SIZE_HS;
1338 if (urb->transfer_buffer_length != 0 &&
1339 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1340 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1341 len = len + sg->length;
1342 if (i > trb_size - 2) {
1343 len = len - tail_sg->length;
1344 if (len < max_pkt) {
1349 tail_sg = sg_next(tail_sg);
1356 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1359 unsigned int buf_len;
1360 enum dma_data_direction dir;
1362 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1364 buf_len = urb->transfer_buffer_length;
1366 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1367 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1368 dma_unmap_single(hcd->self.sysdev,
1370 urb->transfer_buffer_length,
1373 if (usb_urb_dir_in(urb)) {
1374 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1375 urb->transfer_buffer,
1378 if (len != buf_len) {
1379 xhci_dbg(hcd_to_xhci(hcd),
1380 "Copy from tmp buf to urb sg list failed\n");
1381 urb->actual_length = len;
1384 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1385 kfree(urb->transfer_buffer);
1386 urb->transfer_buffer = NULL;
1390 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1391 * we'll copy the actual data into the TRB address register. This is limited to
1392 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1393 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1395 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1398 struct xhci_hcd *xhci;
1400 xhci = hcd_to_xhci(hcd);
1402 if (xhci_urb_suitable_for_idt(urb))
1405 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1406 if (xhci_urb_temp_buffer_required(hcd, urb))
1407 return xhci_map_temp_buffer(hcd, urb);
1409 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1412 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1414 struct xhci_hcd *xhci;
1415 bool unmap_temp_buf = false;
1417 xhci = hcd_to_xhci(hcd);
1419 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1420 unmap_temp_buf = true;
1422 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1423 xhci_unmap_temp_buf(hcd, urb);
1425 usb_hcd_unmap_urb_for_dma(hcd, urb);
1429 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1430 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1431 * value to right shift 1 for the bitmask.
1433 * Index = (epnum * 2) + direction - 1,
1434 * where direction = 0 for OUT, 1 for IN.
1435 * For control endpoints, the IN index is used (OUT index is unused), so
1436 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1438 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1441 if (usb_endpoint_xfer_control(desc))
1442 index = (unsigned int) (usb_endpoint_num(desc)*2);
1444 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1445 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1448 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1450 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1451 * address from the XHCI endpoint index.
1453 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1455 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1456 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1457 return direction | number;
1460 /* Find the flag for this endpoint (for use in the control context). Use the
1461 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1464 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1466 return 1 << (xhci_get_endpoint_index(desc) + 1);
1469 /* Compute the last valid endpoint context index. Basically, this is the
1470 * endpoint index plus one. For slot contexts with more than valid endpoint,
1471 * we find the most significant bit set in the added contexts flags.
1472 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1473 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1475 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1477 return fls(added_ctxs) - 1;
1480 /* Returns 1 if the arguments are OK;
1481 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1483 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1484 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1486 struct xhci_hcd *xhci;
1487 struct xhci_virt_device *virt_dev;
1489 if (!hcd || (check_ep && !ep) || !udev) {
1490 pr_debug("xHCI %s called with invalid args\n", func);
1493 if (!udev->parent) {
1494 pr_debug("xHCI %s called for root hub\n", func);
1498 xhci = hcd_to_xhci(hcd);
1499 if (check_virt_dev) {
1500 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1501 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1506 virt_dev = xhci->devs[udev->slot_id];
1507 if (virt_dev->udev != udev) {
1508 xhci_dbg(xhci, "xHCI %s called with udev and "
1509 "virt_dev does not match\n", func);
1514 if (xhci->xhc_state & XHCI_STATE_HALTED)
1520 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1521 struct usb_device *udev, struct xhci_command *command,
1522 bool ctx_change, bool must_succeed);
1525 * Full speed devices may have a max packet size greater than 8 bytes, but the
1526 * USB core doesn't know that until it reads the first 8 bytes of the
1527 * descriptor. If the usb_device's max packet size changes after that point,
1528 * we need to issue an evaluate context command and wait on it.
1530 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1531 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1533 struct xhci_container_ctx *out_ctx;
1534 struct xhci_input_control_ctx *ctrl_ctx;
1535 struct xhci_ep_ctx *ep_ctx;
1536 struct xhci_command *command;
1537 int max_packet_size;
1538 int hw_max_packet_size;
1541 out_ctx = xhci->devs[slot_id]->out_ctx;
1542 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1543 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1544 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1545 if (hw_max_packet_size != max_packet_size) {
1546 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1547 "Max Packet Size for ep 0 changed.");
1548 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1549 "Max packet size in usb_device = %d",
1551 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1552 "Max packet size in xHCI HW = %d",
1553 hw_max_packet_size);
1554 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1555 "Issuing evaluate context command.");
1557 /* Set up the input context flags for the command */
1558 /* FIXME: This won't work if a non-default control endpoint
1559 * changes max packet sizes.
1562 command = xhci_alloc_command(xhci, true, mem_flags);
1566 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1567 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1569 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1572 goto command_cleanup;
1574 /* Set up the modified control endpoint 0 */
1575 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1576 xhci->devs[slot_id]->out_ctx, ep_index);
1578 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1579 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1580 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1581 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1583 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1584 ctrl_ctx->drop_flags = 0;
1586 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1589 /* Clean up the input context for later use by bandwidth
1592 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1594 kfree(command->completion);
1601 * non-error returns are a promise to giveback() the urb later
1602 * we drop ownership so next owner (or urb unlink) can get it
1604 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1607 unsigned long flags;
1609 unsigned int slot_id, ep_index;
1610 unsigned int *ep_state;
1611 struct urb_priv *urb_priv;
1616 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1617 true, true, __func__);
1619 return ret ? ret : -EINVAL;
1621 slot_id = urb->dev->slot_id;
1622 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1623 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1625 if (!HCD_HW_ACCESSIBLE(hcd))
1628 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1629 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1633 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1634 num_tds = urb->number_of_packets;
1635 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1636 urb->transfer_buffer_length > 0 &&
1637 urb->transfer_flags & URB_ZERO_PACKET &&
1638 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1643 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1647 urb_priv->num_tds = num_tds;
1648 urb_priv->num_tds_done = 0;
1649 urb->hcpriv = urb_priv;
1651 trace_xhci_urb_enqueue(urb);
1653 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1654 /* Check to see if the max packet size for the default control
1655 * endpoint changed during FS device enumeration
1657 if (urb->dev->speed == USB_SPEED_FULL) {
1658 ret = xhci_check_maxpacket(xhci, slot_id,
1659 ep_index, urb, mem_flags);
1661 xhci_urb_free_priv(urb_priv);
1668 spin_lock_irqsave(&xhci->lock, flags);
1670 if (xhci->xhc_state & XHCI_STATE_DYING) {
1671 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1672 urb->ep->desc.bEndpointAddress, urb);
1676 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1677 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1682 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1683 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1688 switch (usb_endpoint_type(&urb->ep->desc)) {
1690 case USB_ENDPOINT_XFER_CONTROL:
1691 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1694 case USB_ENDPOINT_XFER_BULK:
1695 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1698 case USB_ENDPOINT_XFER_INT:
1699 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1702 case USB_ENDPOINT_XFER_ISOC:
1703 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1709 xhci_urb_free_priv(urb_priv);
1712 spin_unlock_irqrestore(&xhci->lock, flags);
1717 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1718 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1719 * should pick up where it left off in the TD, unless a Set Transfer Ring
1720 * Dequeue Pointer is issued.
1722 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1723 * the ring. Since the ring is a contiguous structure, they can't be physically
1724 * removed. Instead, there are two options:
1726 * 1) If the HC is in the middle of processing the URB to be canceled, we
1727 * simply move the ring's dequeue pointer past those TRBs using the Set
1728 * Transfer Ring Dequeue Pointer command. This will be the common case,
1729 * when drivers timeout on the last submitted URB and attempt to cancel.
1731 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1732 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1733 * HC will need to invalidate the any TRBs it has cached after the stop
1734 * endpoint command, as noted in the xHCI 0.95 errata.
1736 * 3) The TD may have completed by the time the Stop Endpoint Command
1737 * completes, so software needs to handle that case too.
1739 * This function should protect against the TD enqueueing code ringing the
1740 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1741 * It also needs to account for multiple cancellations on happening at the same
1742 * time for the same endpoint.
1744 * Note that this function can be called in any context, or so says
1745 * usb_hcd_unlink_urb()
1747 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1749 unsigned long flags;
1752 struct xhci_hcd *xhci;
1753 struct urb_priv *urb_priv;
1755 unsigned int ep_index;
1756 struct xhci_ring *ep_ring;
1757 struct xhci_virt_ep *ep;
1758 struct xhci_command *command;
1759 struct xhci_virt_device *vdev;
1761 xhci = hcd_to_xhci(hcd);
1762 spin_lock_irqsave(&xhci->lock, flags);
1764 trace_xhci_urb_dequeue(urb);
1766 /* Make sure the URB hasn't completed or been unlinked already */
1767 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1771 /* give back URB now if we can't queue it for cancel */
1772 vdev = xhci->devs[urb->dev->slot_id];
1773 urb_priv = urb->hcpriv;
1774 if (!vdev || !urb_priv)
1777 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1778 ep = &vdev->eps[ep_index];
1779 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1780 if (!ep || !ep_ring)
1783 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1784 temp = readl(&xhci->op_regs->status);
1785 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1791 * check ring is not re-allocated since URB was enqueued. If it is, then
1792 * make sure none of the ring related pointers in this URB private data
1793 * are touched, such as td_list, otherwise we overwrite freed data
1795 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1796 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1797 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1798 td = &urb_priv->td[i];
1799 if (!list_empty(&td->cancelled_td_list))
1800 list_del_init(&td->cancelled_td_list);
1805 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1806 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1807 "HC halted, freeing TD manually.");
1808 for (i = urb_priv->num_tds_done;
1809 i < urb_priv->num_tds;
1811 td = &urb_priv->td[i];
1812 if (!list_empty(&td->td_list))
1813 list_del_init(&td->td_list);
1814 if (!list_empty(&td->cancelled_td_list))
1815 list_del_init(&td->cancelled_td_list);
1820 i = urb_priv->num_tds_done;
1821 if (i < urb_priv->num_tds)
1822 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1823 "Cancel URB %p, dev %s, ep 0x%x, "
1824 "starting at offset 0x%llx",
1825 urb, urb->dev->devpath,
1826 urb->ep->desc.bEndpointAddress,
1827 (unsigned long long) xhci_trb_virt_to_dma(
1828 urb_priv->td[i].start_seg,
1829 urb_priv->td[i].first_trb));
1831 for (; i < urb_priv->num_tds; i++) {
1832 td = &urb_priv->td[i];
1833 /* TD can already be on cancelled list if ep halted on it */
1834 if (list_empty(&td->cancelled_td_list)) {
1835 td->cancel_status = TD_DIRTY;
1836 list_add_tail(&td->cancelled_td_list,
1837 &ep->cancelled_td_list);
1841 /* Queue a stop endpoint command, but only if this is
1842 * the first cancellation to be handled.
1844 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1845 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1850 ep->ep_state |= EP_STOP_CMD_PENDING;
1851 ep->stop_cmd_timer.expires = jiffies +
1852 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1853 add_timer(&ep->stop_cmd_timer);
1854 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1856 xhci_ring_cmd_db(xhci);
1859 spin_unlock_irqrestore(&xhci->lock, flags);
1864 xhci_urb_free_priv(urb_priv);
1865 usb_hcd_unlink_urb_from_ep(hcd, urb);
1866 spin_unlock_irqrestore(&xhci->lock, flags);
1867 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1871 /* Drop an endpoint from a new bandwidth configuration for this device.
1872 * Only one call to this function is allowed per endpoint before
1873 * check_bandwidth() or reset_bandwidth() must be called.
1874 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1875 * add the endpoint to the schedule with possibly new parameters denoted by a
1876 * different endpoint descriptor in usb_host_endpoint.
1877 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1880 * The USB core will not allow URBs to be queued to an endpoint that is being
1881 * disabled, so there's no need for mutual exclusion to protect
1882 * the xhci->devs[slot_id] structure.
1884 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1885 struct usb_host_endpoint *ep)
1887 struct xhci_hcd *xhci;
1888 struct xhci_container_ctx *in_ctx, *out_ctx;
1889 struct xhci_input_control_ctx *ctrl_ctx;
1890 unsigned int ep_index;
1891 struct xhci_ep_ctx *ep_ctx;
1893 u32 new_add_flags, new_drop_flags;
1896 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1899 xhci = hcd_to_xhci(hcd);
1900 if (xhci->xhc_state & XHCI_STATE_DYING)
1903 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1904 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1905 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1906 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1907 __func__, drop_flag);
1911 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1912 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1913 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1915 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1920 ep_index = xhci_get_endpoint_index(&ep->desc);
1921 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1922 /* If the HC already knows the endpoint is disabled,
1923 * or the HCD has noted it is disabled, ignore this request
1925 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1926 le32_to_cpu(ctrl_ctx->drop_flags) &
1927 xhci_get_endpoint_flag(&ep->desc)) {
1928 /* Do not warn when called after a usb_device_reset */
1929 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1930 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1935 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1936 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1938 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1939 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1941 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1943 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1945 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1946 (unsigned int) ep->desc.bEndpointAddress,
1948 (unsigned int) new_drop_flags,
1949 (unsigned int) new_add_flags);
1952 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1954 /* Add an endpoint to a new possible bandwidth configuration for this device.
1955 * Only one call to this function is allowed per endpoint before
1956 * check_bandwidth() or reset_bandwidth() must be called.
1957 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1958 * add the endpoint to the schedule with possibly new parameters denoted by a
1959 * different endpoint descriptor in usb_host_endpoint.
1960 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1963 * The USB core will not allow URBs to be queued to an endpoint until the
1964 * configuration or alt setting is installed in the device, so there's no need
1965 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1967 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1968 struct usb_host_endpoint *ep)
1970 struct xhci_hcd *xhci;
1971 struct xhci_container_ctx *in_ctx;
1972 unsigned int ep_index;
1973 struct xhci_input_control_ctx *ctrl_ctx;
1974 struct xhci_ep_ctx *ep_ctx;
1976 u32 new_add_flags, new_drop_flags;
1977 struct xhci_virt_device *virt_dev;
1980 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1982 /* So we won't queue a reset ep command for a root hub */
1986 xhci = hcd_to_xhci(hcd);
1987 if (xhci->xhc_state & XHCI_STATE_DYING)
1990 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1991 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1992 /* FIXME when we have to issue an evaluate endpoint command to
1993 * deal with ep0 max packet size changing once we get the
1996 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1997 __func__, added_ctxs);
2001 virt_dev = xhci->devs[udev->slot_id];
2002 in_ctx = virt_dev->in_ctx;
2003 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2005 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2010 ep_index = xhci_get_endpoint_index(&ep->desc);
2011 /* If this endpoint is already in use, and the upper layers are trying
2012 * to add it again without dropping it, reject the addition.
2014 if (virt_dev->eps[ep_index].ring &&
2015 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2016 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2017 "without dropping it.\n",
2018 (unsigned int) ep->desc.bEndpointAddress);
2022 /* If the HCD has already noted the endpoint is enabled,
2023 * ignore this request.
2025 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2026 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2032 * Configuration and alternate setting changes must be done in
2033 * process context, not interrupt context (or so documenation
2034 * for usb_set_interface() and usb_set_configuration() claim).
2036 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2037 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2038 __func__, ep->desc.bEndpointAddress);
2042 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2043 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2045 /* If xhci_endpoint_disable() was called for this endpoint, but the
2046 * xHC hasn't been notified yet through the check_bandwidth() call,
2047 * this re-adds a new state for the endpoint from the new endpoint
2048 * descriptors. We must drop and re-add this endpoint, so we leave the
2051 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2053 /* Store the usb_device pointer for later use */
2056 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2057 trace_xhci_add_endpoint(ep_ctx);
2059 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2060 (unsigned int) ep->desc.bEndpointAddress,
2062 (unsigned int) new_drop_flags,
2063 (unsigned int) new_add_flags);
2066 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2068 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2070 struct xhci_input_control_ctx *ctrl_ctx;
2071 struct xhci_ep_ctx *ep_ctx;
2072 struct xhci_slot_ctx *slot_ctx;
2075 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2077 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2082 /* When a device's add flag and drop flag are zero, any subsequent
2083 * configure endpoint command will leave that endpoint's state
2084 * untouched. Make sure we don't leave any old state in the input
2085 * endpoint contexts.
2087 ctrl_ctx->drop_flags = 0;
2088 ctrl_ctx->add_flags = 0;
2089 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2090 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2091 /* Endpoint 0 is always valid */
2092 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2093 for (i = 1; i < 31; i++) {
2094 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2095 ep_ctx->ep_info = 0;
2096 ep_ctx->ep_info2 = 0;
2098 ep_ctx->tx_info = 0;
2102 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2103 struct usb_device *udev, u32 *cmd_status)
2107 switch (*cmd_status) {
2108 case COMP_COMMAND_ABORTED:
2109 case COMP_COMMAND_RING_STOPPED:
2110 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2113 case COMP_RESOURCE_ERROR:
2114 dev_warn(&udev->dev,
2115 "Not enough host controller resources for new device state.\n");
2117 /* FIXME: can we allocate more resources for the HC? */
2119 case COMP_BANDWIDTH_ERROR:
2120 case COMP_SECONDARY_BANDWIDTH_ERROR:
2121 dev_warn(&udev->dev,
2122 "Not enough bandwidth for new device state.\n");
2124 /* FIXME: can we go back to the old state? */
2126 case COMP_TRB_ERROR:
2127 /* the HCD set up something wrong */
2128 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2130 "and endpoint is not disabled.\n");
2133 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2134 dev_warn(&udev->dev,
2135 "ERROR: Incompatible device for endpoint configure command.\n");
2139 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2140 "Successful Endpoint Configure command");
2144 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2152 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2153 struct usb_device *udev, u32 *cmd_status)
2157 switch (*cmd_status) {
2158 case COMP_COMMAND_ABORTED:
2159 case COMP_COMMAND_RING_STOPPED:
2160 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2163 case COMP_PARAMETER_ERROR:
2164 dev_warn(&udev->dev,
2165 "WARN: xHCI driver setup invalid evaluate context command.\n");
2168 case COMP_SLOT_NOT_ENABLED_ERROR:
2169 dev_warn(&udev->dev,
2170 "WARN: slot not enabled for evaluate context command.\n");
2173 case COMP_CONTEXT_STATE_ERROR:
2174 dev_warn(&udev->dev,
2175 "WARN: invalid context state for evaluate context command.\n");
2178 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2179 dev_warn(&udev->dev,
2180 "ERROR: Incompatible device for evaluate context command.\n");
2183 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2184 /* Max Exit Latency too large error */
2185 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2189 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2190 "Successful evaluate context command");
2194 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2202 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2203 struct xhci_input_control_ctx *ctrl_ctx)
2205 u32 valid_add_flags;
2206 u32 valid_drop_flags;
2208 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2209 * (bit 1). The default control endpoint is added during the Address
2210 * Device command and is never removed until the slot is disabled.
2212 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2213 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2215 /* Use hweight32 to count the number of ones in the add flags, or
2216 * number of endpoints added. Don't count endpoints that are changed
2217 * (both added and dropped).
2219 return hweight32(valid_add_flags) -
2220 hweight32(valid_add_flags & valid_drop_flags);
2223 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2224 struct xhci_input_control_ctx *ctrl_ctx)
2226 u32 valid_add_flags;
2227 u32 valid_drop_flags;
2229 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2230 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2232 return hweight32(valid_drop_flags) -
2233 hweight32(valid_add_flags & valid_drop_flags);
2237 * We need to reserve the new number of endpoints before the configure endpoint
2238 * command completes. We can't subtract the dropped endpoints from the number
2239 * of active endpoints until the command completes because we can oversubscribe
2240 * the host in this case:
2242 * - the first configure endpoint command drops more endpoints than it adds
2243 * - a second configure endpoint command that adds more endpoints is queued
2244 * - the first configure endpoint command fails, so the config is unchanged
2245 * - the second command may succeed, even though there isn't enough resources
2247 * Must be called with xhci->lock held.
2249 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2250 struct xhci_input_control_ctx *ctrl_ctx)
2254 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2255 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2256 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2257 "Not enough ep ctxs: "
2258 "%u active, need to add %u, limit is %u.",
2259 xhci->num_active_eps, added_eps,
2260 xhci->limit_active_eps);
2263 xhci->num_active_eps += added_eps;
2264 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2265 "Adding %u ep ctxs, %u now active.", added_eps,
2266 xhci->num_active_eps);
2271 * The configure endpoint was failed by the xHC for some other reason, so we
2272 * need to revert the resources that failed configuration would have used.
2274 * Must be called with xhci->lock held.
2276 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2277 struct xhci_input_control_ctx *ctrl_ctx)
2281 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2282 xhci->num_active_eps -= num_failed_eps;
2283 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2284 "Removing %u failed ep ctxs, %u now active.",
2286 xhci->num_active_eps);
2290 * Now that the command has completed, clean up the active endpoint count by
2291 * subtracting out the endpoints that were dropped (but not changed).
2293 * Must be called with xhci->lock held.
2295 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2296 struct xhci_input_control_ctx *ctrl_ctx)
2298 u32 num_dropped_eps;
2300 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2301 xhci->num_active_eps -= num_dropped_eps;
2302 if (num_dropped_eps)
2303 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2304 "Removing %u dropped ep ctxs, %u now active.",
2306 xhci->num_active_eps);
2309 static unsigned int xhci_get_block_size(struct usb_device *udev)
2311 switch (udev->speed) {
2313 case USB_SPEED_FULL:
2315 case USB_SPEED_HIGH:
2317 case USB_SPEED_SUPER:
2318 case USB_SPEED_SUPER_PLUS:
2320 case USB_SPEED_UNKNOWN:
2321 case USB_SPEED_WIRELESS:
2323 /* Should never happen */
2329 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2331 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2333 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2338 /* If we are changing a LS/FS device under a HS hub,
2339 * make sure (if we are activating a new TT) that the HS bus has enough
2340 * bandwidth for this new TT.
2342 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2343 struct xhci_virt_device *virt_dev,
2346 struct xhci_interval_bw_table *bw_table;
2347 struct xhci_tt_bw_info *tt_info;
2349 /* Find the bandwidth table for the root port this TT is attached to. */
2350 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2351 tt_info = virt_dev->tt_info;
2352 /* If this TT already had active endpoints, the bandwidth for this TT
2353 * has already been added. Removing all periodic endpoints (and thus
2354 * making the TT enactive) will only decrease the bandwidth used.
2358 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2359 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2363 /* Not sure why we would have no new active endpoints...
2365 * Maybe because of an Evaluate Context change for a hub update or a
2366 * control endpoint 0 max packet size change?
2367 * FIXME: skip the bandwidth calculation in that case.
2372 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2373 struct xhci_virt_device *virt_dev)
2375 unsigned int bw_reserved;
2377 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2378 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2381 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2382 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2389 * This algorithm is a very conservative estimate of the worst-case scheduling
2390 * scenario for any one interval. The hardware dynamically schedules the
2391 * packets, so we can't tell which microframe could be the limiting factor in
2392 * the bandwidth scheduling. This only takes into account periodic endpoints.
2394 * Obviously, we can't solve an NP complete problem to find the minimum worst
2395 * case scenario. Instead, we come up with an estimate that is no less than
2396 * the worst case bandwidth used for any one microframe, but may be an
2399 * We walk the requirements for each endpoint by interval, starting with the
2400 * smallest interval, and place packets in the schedule where there is only one
2401 * possible way to schedule packets for that interval. In order to simplify
2402 * this algorithm, we record the largest max packet size for each interval, and
2403 * assume all packets will be that size.
2405 * For interval 0, we obviously must schedule all packets for each interval.
2406 * The bandwidth for interval 0 is just the amount of data to be transmitted
2407 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2408 * the number of packets).
2410 * For interval 1, we have two possible microframes to schedule those packets
2411 * in. For this algorithm, if we can schedule the same number of packets for
2412 * each possible scheduling opportunity (each microframe), we will do so. The
2413 * remaining number of packets will be saved to be transmitted in the gaps in
2414 * the next interval's scheduling sequence.
2416 * As we move those remaining packets to be scheduled with interval 2 packets,
2417 * we have to double the number of remaining packets to transmit. This is
2418 * because the intervals are actually powers of 2, and we would be transmitting
2419 * the previous interval's packets twice in this interval. We also have to be
2420 * sure that when we look at the largest max packet size for this interval, we
2421 * also look at the largest max packet size for the remaining packets and take
2422 * the greater of the two.
2424 * The algorithm continues to evenly distribute packets in each scheduling
2425 * opportunity, and push the remaining packets out, until we get to the last
2426 * interval. Then those packets and their associated overhead are just added
2427 * to the bandwidth used.
2429 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2430 struct xhci_virt_device *virt_dev,
2433 unsigned int bw_reserved;
2434 unsigned int max_bandwidth;
2435 unsigned int bw_used;
2436 unsigned int block_size;
2437 struct xhci_interval_bw_table *bw_table;
2438 unsigned int packet_size = 0;
2439 unsigned int overhead = 0;
2440 unsigned int packets_transmitted = 0;
2441 unsigned int packets_remaining = 0;
2444 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2445 return xhci_check_ss_bw(xhci, virt_dev);
2447 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2448 max_bandwidth = HS_BW_LIMIT;
2449 /* Convert percent of bus BW reserved to blocks reserved */
2450 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2452 max_bandwidth = FS_BW_LIMIT;
2453 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2456 bw_table = virt_dev->bw_table;
2457 /* We need to translate the max packet size and max ESIT payloads into
2458 * the units the hardware uses.
2460 block_size = xhci_get_block_size(virt_dev->udev);
2462 /* If we are manipulating a LS/FS device under a HS hub, double check
2463 * that the HS bus has enough bandwidth if we are activing a new TT.
2465 if (virt_dev->tt_info) {
2466 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2467 "Recalculating BW for rootport %u",
2468 virt_dev->real_port);
2469 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2470 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2471 "newly activated TT.\n");
2474 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2475 "Recalculating BW for TT slot %u port %u",
2476 virt_dev->tt_info->slot_id,
2477 virt_dev->tt_info->ttport);
2479 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2480 "Recalculating BW for rootport %u",
2481 virt_dev->real_port);
2484 /* Add in how much bandwidth will be used for interval zero, or the
2485 * rounded max ESIT payload + number of packets * largest overhead.
2487 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2488 bw_table->interval_bw[0].num_packets *
2489 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2491 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2492 unsigned int bw_added;
2493 unsigned int largest_mps;
2494 unsigned int interval_overhead;
2497 * How many packets could we transmit in this interval?
2498 * If packets didn't fit in the previous interval, we will need
2499 * to transmit that many packets twice within this interval.
2501 packets_remaining = 2 * packets_remaining +
2502 bw_table->interval_bw[i].num_packets;
2504 /* Find the largest max packet size of this or the previous
2507 if (list_empty(&bw_table->interval_bw[i].endpoints))
2510 struct xhci_virt_ep *virt_ep;
2511 struct list_head *ep_entry;
2513 ep_entry = bw_table->interval_bw[i].endpoints.next;
2514 virt_ep = list_entry(ep_entry,
2515 struct xhci_virt_ep, bw_endpoint_list);
2516 /* Convert to blocks, rounding up */
2517 largest_mps = DIV_ROUND_UP(
2518 virt_ep->bw_info.max_packet_size,
2521 if (largest_mps > packet_size)
2522 packet_size = largest_mps;
2524 /* Use the larger overhead of this or the previous interval. */
2525 interval_overhead = xhci_get_largest_overhead(
2526 &bw_table->interval_bw[i]);
2527 if (interval_overhead > overhead)
2528 overhead = interval_overhead;
2530 /* How many packets can we evenly distribute across
2531 * (1 << (i + 1)) possible scheduling opportunities?
2533 packets_transmitted = packets_remaining >> (i + 1);
2535 /* Add in the bandwidth used for those scheduled packets */
2536 bw_added = packets_transmitted * (overhead + packet_size);
2538 /* How many packets do we have remaining to transmit? */
2539 packets_remaining = packets_remaining % (1 << (i + 1));
2541 /* What largest max packet size should those packets have? */
2542 /* If we've transmitted all packets, don't carry over the
2543 * largest packet size.
2545 if (packets_remaining == 0) {
2548 } else if (packets_transmitted > 0) {
2549 /* Otherwise if we do have remaining packets, and we've
2550 * scheduled some packets in this interval, take the
2551 * largest max packet size from endpoints with this
2554 packet_size = largest_mps;
2555 overhead = interval_overhead;
2557 /* Otherwise carry over packet_size and overhead from the last
2558 * time we had a remainder.
2560 bw_used += bw_added;
2561 if (bw_used > max_bandwidth) {
2562 xhci_warn(xhci, "Not enough bandwidth. "
2563 "Proposed: %u, Max: %u\n",
2564 bw_used, max_bandwidth);
2569 * Ok, we know we have some packets left over after even-handedly
2570 * scheduling interval 15. We don't know which microframes they will
2571 * fit into, so we over-schedule and say they will be scheduled every
2574 if (packets_remaining > 0)
2575 bw_used += overhead + packet_size;
2577 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2578 unsigned int port_index = virt_dev->real_port - 1;
2580 /* OK, we're manipulating a HS device attached to a
2581 * root port bandwidth domain. Include the number of active TTs
2582 * in the bandwidth used.
2584 bw_used += TT_HS_OVERHEAD *
2585 xhci->rh_bw[port_index].num_active_tts;
2588 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2589 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2590 "Available: %u " "percent",
2591 bw_used, max_bandwidth, bw_reserved,
2592 (max_bandwidth - bw_used - bw_reserved) * 100 /
2595 bw_used += bw_reserved;
2596 if (bw_used > max_bandwidth) {
2597 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2598 bw_used, max_bandwidth);
2602 bw_table->bw_used = bw_used;
2606 static bool xhci_is_async_ep(unsigned int ep_type)
2608 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2609 ep_type != ISOC_IN_EP &&
2610 ep_type != INT_IN_EP);
2613 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2615 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2618 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2620 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2622 if (ep_bw->ep_interval == 0)
2623 return SS_OVERHEAD_BURST +
2624 (ep_bw->mult * ep_bw->num_packets *
2625 (SS_OVERHEAD + mps));
2626 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2627 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2628 1 << ep_bw->ep_interval);
2632 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2633 struct xhci_bw_info *ep_bw,
2634 struct xhci_interval_bw_table *bw_table,
2635 struct usb_device *udev,
2636 struct xhci_virt_ep *virt_ep,
2637 struct xhci_tt_bw_info *tt_info)
2639 struct xhci_interval_bw *interval_bw;
2640 int normalized_interval;
2642 if (xhci_is_async_ep(ep_bw->type))
2645 if (udev->speed >= USB_SPEED_SUPER) {
2646 if (xhci_is_sync_in_ep(ep_bw->type))
2647 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2648 xhci_get_ss_bw_consumed(ep_bw);
2650 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2651 xhci_get_ss_bw_consumed(ep_bw);
2655 /* SuperSpeed endpoints never get added to intervals in the table, so
2656 * this check is only valid for HS/FS/LS devices.
2658 if (list_empty(&virt_ep->bw_endpoint_list))
2660 /* For LS/FS devices, we need to translate the interval expressed in
2661 * microframes to frames.
2663 if (udev->speed == USB_SPEED_HIGH)
2664 normalized_interval = ep_bw->ep_interval;
2666 normalized_interval = ep_bw->ep_interval - 3;
2668 if (normalized_interval == 0)
2669 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2670 interval_bw = &bw_table->interval_bw[normalized_interval];
2671 interval_bw->num_packets -= ep_bw->num_packets;
2672 switch (udev->speed) {
2674 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2676 case USB_SPEED_FULL:
2677 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2679 case USB_SPEED_HIGH:
2680 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2682 case USB_SPEED_SUPER:
2683 case USB_SPEED_SUPER_PLUS:
2684 case USB_SPEED_UNKNOWN:
2685 case USB_SPEED_WIRELESS:
2686 /* Should never happen because only LS/FS/HS endpoints will get
2687 * added to the endpoint list.
2692 tt_info->active_eps -= 1;
2693 list_del_init(&virt_ep->bw_endpoint_list);
2696 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2697 struct xhci_bw_info *ep_bw,
2698 struct xhci_interval_bw_table *bw_table,
2699 struct usb_device *udev,
2700 struct xhci_virt_ep *virt_ep,
2701 struct xhci_tt_bw_info *tt_info)
2703 struct xhci_interval_bw *interval_bw;
2704 struct xhci_virt_ep *smaller_ep;
2705 int normalized_interval;
2707 if (xhci_is_async_ep(ep_bw->type))
2710 if (udev->speed == USB_SPEED_SUPER) {
2711 if (xhci_is_sync_in_ep(ep_bw->type))
2712 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2713 xhci_get_ss_bw_consumed(ep_bw);
2715 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2716 xhci_get_ss_bw_consumed(ep_bw);
2720 /* For LS/FS devices, we need to translate the interval expressed in
2721 * microframes to frames.
2723 if (udev->speed == USB_SPEED_HIGH)
2724 normalized_interval = ep_bw->ep_interval;
2726 normalized_interval = ep_bw->ep_interval - 3;
2728 if (normalized_interval == 0)
2729 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2730 interval_bw = &bw_table->interval_bw[normalized_interval];
2731 interval_bw->num_packets += ep_bw->num_packets;
2732 switch (udev->speed) {
2734 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2736 case USB_SPEED_FULL:
2737 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2739 case USB_SPEED_HIGH:
2740 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2742 case USB_SPEED_SUPER:
2743 case USB_SPEED_SUPER_PLUS:
2744 case USB_SPEED_UNKNOWN:
2745 case USB_SPEED_WIRELESS:
2746 /* Should never happen because only LS/FS/HS endpoints will get
2747 * added to the endpoint list.
2753 tt_info->active_eps += 1;
2754 /* Insert the endpoint into the list, largest max packet size first. */
2755 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2757 if (ep_bw->max_packet_size >=
2758 smaller_ep->bw_info.max_packet_size) {
2759 /* Add the new ep before the smaller endpoint */
2760 list_add_tail(&virt_ep->bw_endpoint_list,
2761 &smaller_ep->bw_endpoint_list);
2765 /* Add the new endpoint at the end of the list. */
2766 list_add_tail(&virt_ep->bw_endpoint_list,
2767 &interval_bw->endpoints);
2770 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2771 struct xhci_virt_device *virt_dev,
2774 struct xhci_root_port_bw_info *rh_bw_info;
2775 if (!virt_dev->tt_info)
2778 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2779 if (old_active_eps == 0 &&
2780 virt_dev->tt_info->active_eps != 0) {
2781 rh_bw_info->num_active_tts += 1;
2782 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2783 } else if (old_active_eps != 0 &&
2784 virt_dev->tt_info->active_eps == 0) {
2785 rh_bw_info->num_active_tts -= 1;
2786 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2790 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2791 struct xhci_virt_device *virt_dev,
2792 struct xhci_container_ctx *in_ctx)
2794 struct xhci_bw_info ep_bw_info[31];
2796 struct xhci_input_control_ctx *ctrl_ctx;
2797 int old_active_eps = 0;
2799 if (virt_dev->tt_info)
2800 old_active_eps = virt_dev->tt_info->active_eps;
2802 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2804 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2809 for (i = 0; i < 31; i++) {
2810 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2813 /* Make a copy of the BW info in case we need to revert this */
2814 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2815 sizeof(ep_bw_info[i]));
2816 /* Drop the endpoint from the interval table if the endpoint is
2817 * being dropped or changed.
2819 if (EP_IS_DROPPED(ctrl_ctx, i))
2820 xhci_drop_ep_from_interval_table(xhci,
2821 &virt_dev->eps[i].bw_info,
2827 /* Overwrite the information stored in the endpoints' bw_info */
2828 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2829 for (i = 0; i < 31; i++) {
2830 /* Add any changed or added endpoints to the interval table */
2831 if (EP_IS_ADDED(ctrl_ctx, i))
2832 xhci_add_ep_to_interval_table(xhci,
2833 &virt_dev->eps[i].bw_info,
2840 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2841 /* Ok, this fits in the bandwidth we have.
2842 * Update the number of active TTs.
2844 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2848 /* We don't have enough bandwidth for this, revert the stored info. */
2849 for (i = 0; i < 31; i++) {
2850 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2853 /* Drop the new copies of any added or changed endpoints from
2854 * the interval table.
2856 if (EP_IS_ADDED(ctrl_ctx, i)) {
2857 xhci_drop_ep_from_interval_table(xhci,
2858 &virt_dev->eps[i].bw_info,
2864 /* Revert the endpoint back to its old information */
2865 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2866 sizeof(ep_bw_info[i]));
2867 /* Add any changed or dropped endpoints back into the table */
2868 if (EP_IS_DROPPED(ctrl_ctx, i))
2869 xhci_add_ep_to_interval_table(xhci,
2870 &virt_dev->eps[i].bw_info,
2880 /* Issue a configure endpoint command or evaluate context command
2881 * and wait for it to finish.
2883 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2884 struct usb_device *udev,
2885 struct xhci_command *command,
2886 bool ctx_change, bool must_succeed)
2889 unsigned long flags;
2890 struct xhci_input_control_ctx *ctrl_ctx;
2891 struct xhci_virt_device *virt_dev;
2892 struct xhci_slot_ctx *slot_ctx;
2897 spin_lock_irqsave(&xhci->lock, flags);
2899 if (xhci->xhc_state & XHCI_STATE_DYING) {
2900 spin_unlock_irqrestore(&xhci->lock, flags);
2904 virt_dev = xhci->devs[udev->slot_id];
2906 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2908 spin_unlock_irqrestore(&xhci->lock, flags);
2909 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2914 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2915 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2916 spin_unlock_irqrestore(&xhci->lock, flags);
2917 xhci_warn(xhci, "Not enough host resources, "
2918 "active endpoint contexts = %u\n",
2919 xhci->num_active_eps);
2922 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2923 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2924 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2925 xhci_free_host_resources(xhci, ctrl_ctx);
2926 spin_unlock_irqrestore(&xhci->lock, flags);
2927 xhci_warn(xhci, "Not enough bandwidth\n");
2931 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2933 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2934 trace_xhci_configure_endpoint(slot_ctx);
2937 ret = xhci_queue_configure_endpoint(xhci, command,
2938 command->in_ctx->dma,
2939 udev->slot_id, must_succeed);
2941 ret = xhci_queue_evaluate_context(xhci, command,
2942 command->in_ctx->dma,
2943 udev->slot_id, must_succeed);
2945 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2946 xhci_free_host_resources(xhci, ctrl_ctx);
2947 spin_unlock_irqrestore(&xhci->lock, flags);
2948 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2949 "FIXME allocate a new ring segment");
2952 xhci_ring_cmd_db(xhci);
2953 spin_unlock_irqrestore(&xhci->lock, flags);
2955 /* Wait for the configure endpoint command to complete */
2956 wait_for_completion(command->completion);
2959 ret = xhci_configure_endpoint_result(xhci, udev,
2962 ret = xhci_evaluate_context_result(xhci, udev,
2965 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2966 spin_lock_irqsave(&xhci->lock, flags);
2967 /* If the command failed, remove the reserved resources.
2968 * Otherwise, clean up the estimate to include dropped eps.
2971 xhci_free_host_resources(xhci, ctrl_ctx);
2973 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2974 spin_unlock_irqrestore(&xhci->lock, flags);
2979 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2980 struct xhci_virt_device *vdev, int i)
2982 struct xhci_virt_ep *ep = &vdev->eps[i];
2984 if (ep->ep_state & EP_HAS_STREAMS) {
2985 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2986 xhci_get_endpoint_address(i));
2987 xhci_free_stream_info(xhci, ep->stream_info);
2988 ep->stream_info = NULL;
2989 ep->ep_state &= ~EP_HAS_STREAMS;
2993 /* Called after one or more calls to xhci_add_endpoint() or
2994 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2995 * to call xhci_reset_bandwidth().
2997 * Since we are in the middle of changing either configuration or
2998 * installing a new alt setting, the USB core won't allow URBs to be
2999 * enqueued for any endpoint on the old config or interface. Nothing
3000 * else should be touching the xhci->devs[slot_id] structure, so we
3001 * don't need to take the xhci->lock for manipulating that.
3003 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3007 struct xhci_hcd *xhci;
3008 struct xhci_virt_device *virt_dev;
3009 struct xhci_input_control_ctx *ctrl_ctx;
3010 struct xhci_slot_ctx *slot_ctx;
3011 struct xhci_command *command;
3013 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3016 xhci = hcd_to_xhci(hcd);
3017 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3018 (xhci->xhc_state & XHCI_STATE_REMOVING))
3021 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3022 virt_dev = xhci->devs[udev->slot_id];
3024 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3028 command->in_ctx = virt_dev->in_ctx;
3030 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3031 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3033 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3036 goto command_cleanup;
3038 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3039 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3040 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3042 /* Don't issue the command if there's no endpoints to update. */
3043 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3044 ctrl_ctx->drop_flags == 0) {
3046 goto command_cleanup;
3048 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3049 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3050 for (i = 31; i >= 1; i--) {
3051 __le32 le32 = cpu_to_le32(BIT(i));
3053 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3054 || (ctrl_ctx->add_flags & le32) || i == 1) {
3055 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3056 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3061 ret = xhci_configure_endpoint(xhci, udev, command,
3064 /* Callee should call reset_bandwidth() */
3065 goto command_cleanup;
3067 /* Free any rings that were dropped, but not changed. */
3068 for (i = 1; i < 31; i++) {
3069 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3070 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3071 xhci_free_endpoint_ring(xhci, virt_dev, i);
3072 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3075 xhci_zero_in_ctx(xhci, virt_dev);
3077 * Install any rings for completely new endpoints or changed endpoints,
3078 * and free any old rings from changed endpoints.
3080 for (i = 1; i < 31; i++) {
3081 if (!virt_dev->eps[i].new_ring)
3083 /* Only free the old ring if it exists.
3084 * It may not if this is the first add of an endpoint.
3086 if (virt_dev->eps[i].ring) {
3087 xhci_free_endpoint_ring(xhci, virt_dev, i);
3089 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3090 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3091 virt_dev->eps[i].new_ring = NULL;
3092 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3095 kfree(command->completion);
3100 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3102 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3104 struct xhci_hcd *xhci;
3105 struct xhci_virt_device *virt_dev;
3108 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3111 xhci = hcd_to_xhci(hcd);
3113 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3114 virt_dev = xhci->devs[udev->slot_id];
3115 /* Free any rings allocated for added endpoints */
3116 for (i = 0; i < 31; i++) {
3117 if (virt_dev->eps[i].new_ring) {
3118 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3119 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3120 virt_dev->eps[i].new_ring = NULL;
3123 xhci_zero_in_ctx(xhci, virt_dev);
3125 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3127 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3128 struct xhci_container_ctx *in_ctx,
3129 struct xhci_container_ctx *out_ctx,
3130 struct xhci_input_control_ctx *ctrl_ctx,
3131 u32 add_flags, u32 drop_flags)
3133 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3134 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3135 xhci_slot_copy(xhci, in_ctx, out_ctx);
3136 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3139 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3140 struct usb_host_endpoint *host_ep)
3142 struct xhci_hcd *xhci;
3143 struct xhci_virt_device *vdev;
3144 struct xhci_virt_ep *ep;
3145 struct usb_device *udev;
3146 unsigned long flags;
3147 unsigned int ep_index;
3149 xhci = hcd_to_xhci(hcd);
3151 spin_lock_irqsave(&xhci->lock, flags);
3153 udev = (struct usb_device *)host_ep->hcpriv;
3154 if (!udev || !udev->slot_id)
3157 vdev = xhci->devs[udev->slot_id];
3161 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3162 ep = &vdev->eps[ep_index];
3166 /* wait for hub_tt_work to finish clearing hub TT */
3167 if (ep->ep_state & EP_CLEARING_TT) {
3168 spin_unlock_irqrestore(&xhci->lock, flags);
3169 schedule_timeout_uninterruptible(1);
3174 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3177 host_ep->hcpriv = NULL;
3178 spin_unlock_irqrestore(&xhci->lock, flags);
3182 * Called after usb core issues a clear halt control message.
3183 * The host side of the halt should already be cleared by a reset endpoint
3184 * command issued when the STALL event was received.
3186 * The reset endpoint command may only be issued to endpoints in the halted
3187 * state. For software that wishes to reset the data toggle or sequence number
3188 * of an endpoint that isn't in the halted state this function will issue a
3189 * configure endpoint command with the Drop and Add bits set for the target
3190 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3193 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3194 struct usb_host_endpoint *host_ep)
3196 struct xhci_hcd *xhci;
3197 struct usb_device *udev;
3198 struct xhci_virt_device *vdev;
3199 struct xhci_virt_ep *ep;
3200 struct xhci_input_control_ctx *ctrl_ctx;
3201 struct xhci_command *stop_cmd, *cfg_cmd;
3202 unsigned int ep_index;
3203 unsigned long flags;
3207 xhci = hcd_to_xhci(hcd);
3208 if (!host_ep->hcpriv)
3210 udev = (struct usb_device *) host_ep->hcpriv;
3211 vdev = xhci->devs[udev->slot_id];
3214 * vdev may be lost due to xHC restore error and re-initialization
3215 * during S3/S4 resume. A new vdev will be allocated later by
3216 * xhci_discover_or_reset_device()
3218 if (!udev->slot_id || !vdev)
3220 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3221 ep = &vdev->eps[ep_index];
3225 /* Bail out if toggle is already being cleared by a endpoint reset */
3226 spin_lock_irqsave(&xhci->lock, flags);
3227 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3228 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3229 spin_unlock_irqrestore(&xhci->lock, flags);
3232 spin_unlock_irqrestore(&xhci->lock, flags);
3233 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3234 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3235 usb_endpoint_xfer_isoc(&host_ep->desc))
3238 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3240 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3243 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3247 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3251 spin_lock_irqsave(&xhci->lock, flags);
3253 /* block queuing new trbs and ringing ep doorbell */
3254 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3257 * Make sure endpoint ring is empty before resetting the toggle/seq.
3258 * Driver is required to synchronously cancel all transfer request.
3259 * Stop the endpoint to force xHC to update the output context
3262 if (!list_empty(&ep->ring->td_list)) {
3263 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3264 spin_unlock_irqrestore(&xhci->lock, flags);
3265 xhci_free_command(xhci, cfg_cmd);
3269 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3272 spin_unlock_irqrestore(&xhci->lock, flags);
3273 xhci_free_command(xhci, cfg_cmd);
3274 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3279 xhci_ring_cmd_db(xhci);
3280 spin_unlock_irqrestore(&xhci->lock, flags);
3282 wait_for_completion(stop_cmd->completion);
3284 spin_lock_irqsave(&xhci->lock, flags);
3286 /* config ep command clears toggle if add and drop ep flags are set */
3287 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3289 spin_unlock_irqrestore(&xhci->lock, flags);
3290 xhci_free_command(xhci, cfg_cmd);
3291 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3296 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3297 ctrl_ctx, ep_flag, ep_flag);
3298 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3300 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3301 udev->slot_id, false);
3303 spin_unlock_irqrestore(&xhci->lock, flags);
3304 xhci_free_command(xhci, cfg_cmd);
3305 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3310 xhci_ring_cmd_db(xhci);
3311 spin_unlock_irqrestore(&xhci->lock, flags);
3313 wait_for_completion(cfg_cmd->completion);
3315 xhci_free_command(xhci, cfg_cmd);
3317 xhci_free_command(xhci, stop_cmd);
3318 spin_lock_irqsave(&xhci->lock, flags);
3319 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3320 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3321 spin_unlock_irqrestore(&xhci->lock, flags);
3324 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3325 struct usb_device *udev, struct usb_host_endpoint *ep,
3326 unsigned int slot_id)
3329 unsigned int ep_index;
3330 unsigned int ep_state;
3334 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3336 return ret ? ret : -EINVAL;
3337 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3338 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3339 " descriptor for ep 0x%x does not support streams\n",
3340 ep->desc.bEndpointAddress);
3344 ep_index = xhci_get_endpoint_index(&ep->desc);
3345 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3346 if (ep_state & EP_HAS_STREAMS ||
3347 ep_state & EP_GETTING_STREAMS) {
3348 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3349 "already has streams set up.\n",
3350 ep->desc.bEndpointAddress);
3351 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3352 "dynamic stream context array reallocation.\n");
3355 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3356 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3357 "endpoint 0x%x; URBs are pending.\n",
3358 ep->desc.bEndpointAddress);
3364 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3365 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3367 unsigned int max_streams;
3369 /* The stream context array size must be a power of two */
3370 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3372 * Find out how many primary stream array entries the host controller
3373 * supports. Later we may use secondary stream arrays (similar to 2nd
3374 * level page entries), but that's an optional feature for xHCI host
3375 * controllers. xHCs must support at least 4 stream IDs.
3377 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3378 if (*num_stream_ctxs > max_streams) {
3379 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3381 *num_stream_ctxs = max_streams;
3382 *num_streams = max_streams;
3386 /* Returns an error code if one of the endpoint already has streams.
3387 * This does not change any data structures, it only checks and gathers
3390 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3391 struct usb_device *udev,
3392 struct usb_host_endpoint **eps, unsigned int num_eps,
3393 unsigned int *num_streams, u32 *changed_ep_bitmask)
3395 unsigned int max_streams;
3396 unsigned int endpoint_flag;
3400 for (i = 0; i < num_eps; i++) {
3401 ret = xhci_check_streams_endpoint(xhci, udev,
3402 eps[i], udev->slot_id);
3406 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3407 if (max_streams < (*num_streams - 1)) {
3408 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3409 eps[i]->desc.bEndpointAddress,
3411 *num_streams = max_streams+1;
3414 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3415 if (*changed_ep_bitmask & endpoint_flag)
3417 *changed_ep_bitmask |= endpoint_flag;
3422 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3423 struct usb_device *udev,
3424 struct usb_host_endpoint **eps, unsigned int num_eps)
3426 u32 changed_ep_bitmask = 0;
3427 unsigned int slot_id;
3428 unsigned int ep_index;
3429 unsigned int ep_state;
3432 slot_id = udev->slot_id;
3433 if (!xhci->devs[slot_id])
3436 for (i = 0; i < num_eps; i++) {
3437 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3438 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3439 /* Are streams already being freed for the endpoint? */
3440 if (ep_state & EP_GETTING_NO_STREAMS) {
3441 xhci_warn(xhci, "WARN Can't disable streams for "
3443 "streams are being disabled already\n",
3444 eps[i]->desc.bEndpointAddress);
3447 /* Are there actually any streams to free? */
3448 if (!(ep_state & EP_HAS_STREAMS) &&
3449 !(ep_state & EP_GETTING_STREAMS)) {
3450 xhci_warn(xhci, "WARN Can't disable streams for "
3452 "streams are already disabled!\n",
3453 eps[i]->desc.bEndpointAddress);
3454 xhci_warn(xhci, "WARN xhci_free_streams() called "
3455 "with non-streams endpoint\n");
3458 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3460 return changed_ep_bitmask;
3464 * The USB device drivers use this function (through the HCD interface in USB
3465 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3466 * coordinate mass storage command queueing across multiple endpoints (basically
3467 * a stream ID == a task ID).
3469 * Setting up streams involves allocating the same size stream context array
3470 * for each endpoint and issuing a configure endpoint command for all endpoints.
3472 * Don't allow the call to succeed if one endpoint only supports one stream
3473 * (which means it doesn't support streams at all).
3475 * Drivers may get less stream IDs than they asked for, if the host controller
3476 * hardware or endpoints claim they can't support the number of requested
3479 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3480 struct usb_host_endpoint **eps, unsigned int num_eps,
3481 unsigned int num_streams, gfp_t mem_flags)
3484 struct xhci_hcd *xhci;
3485 struct xhci_virt_device *vdev;
3486 struct xhci_command *config_cmd;
3487 struct xhci_input_control_ctx *ctrl_ctx;
3488 unsigned int ep_index;
3489 unsigned int num_stream_ctxs;
3490 unsigned int max_packet;
3491 unsigned long flags;
3492 u32 changed_ep_bitmask = 0;
3497 /* Add one to the number of streams requested to account for
3498 * stream 0 that is reserved for xHCI usage.
3501 xhci = hcd_to_xhci(hcd);
3502 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3505 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3506 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3507 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3508 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3512 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3516 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3518 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3520 xhci_free_command(xhci, config_cmd);
3524 /* Check to make sure all endpoints are not already configured for
3525 * streams. While we're at it, find the maximum number of streams that
3526 * all the endpoints will support and check for duplicate endpoints.
3528 spin_lock_irqsave(&xhci->lock, flags);
3529 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3530 num_eps, &num_streams, &changed_ep_bitmask);
3532 xhci_free_command(xhci, config_cmd);
3533 spin_unlock_irqrestore(&xhci->lock, flags);
3536 if (num_streams <= 1) {
3537 xhci_warn(xhci, "WARN: endpoints can't handle "
3538 "more than one stream.\n");
3539 xhci_free_command(xhci, config_cmd);
3540 spin_unlock_irqrestore(&xhci->lock, flags);
3543 vdev = xhci->devs[udev->slot_id];
3544 /* Mark each endpoint as being in transition, so
3545 * xhci_urb_enqueue() will reject all URBs.
3547 for (i = 0; i < num_eps; i++) {
3548 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3549 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3551 spin_unlock_irqrestore(&xhci->lock, flags);
3553 /* Setup internal data structures and allocate HW data structures for
3554 * streams (but don't install the HW structures in the input context
3555 * until we're sure all memory allocation succeeded).
3557 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3558 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3559 num_stream_ctxs, num_streams);
3561 for (i = 0; i < num_eps; i++) {
3562 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3563 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3564 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3567 max_packet, mem_flags);
3568 if (!vdev->eps[ep_index].stream_info)
3570 /* Set maxPstreams in endpoint context and update deq ptr to
3571 * point to stream context array. FIXME
3575 /* Set up the input context for a configure endpoint command. */
3576 for (i = 0; i < num_eps; i++) {
3577 struct xhci_ep_ctx *ep_ctx;
3579 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3580 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3582 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3583 vdev->out_ctx, ep_index);
3584 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3585 vdev->eps[ep_index].stream_info);
3587 /* Tell the HW to drop its old copy of the endpoint context info
3588 * and add the updated copy from the input context.
3590 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3591 vdev->out_ctx, ctrl_ctx,
3592 changed_ep_bitmask, changed_ep_bitmask);
3594 /* Issue and wait for the configure endpoint command */
3595 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3598 /* xHC rejected the configure endpoint command for some reason, so we
3599 * leave the old ring intact and free our internal streams data
3605 spin_lock_irqsave(&xhci->lock, flags);
3606 for (i = 0; i < num_eps; i++) {
3607 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3608 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3609 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3610 udev->slot_id, ep_index);
3611 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3613 xhci_free_command(xhci, config_cmd);
3614 spin_unlock_irqrestore(&xhci->lock, flags);
3616 for (i = 0; i < num_eps; i++) {
3617 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3618 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3620 /* Subtract 1 for stream 0, which drivers can't use */
3621 return num_streams - 1;
3624 /* If it didn't work, free the streams! */
3625 for (i = 0; i < num_eps; i++) {
3626 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3627 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3628 vdev->eps[ep_index].stream_info = NULL;
3629 /* FIXME Unset maxPstreams in endpoint context and
3630 * update deq ptr to point to normal string ring.
3632 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3633 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3634 xhci_endpoint_zero(xhci, vdev, eps[i]);
3636 xhci_free_command(xhci, config_cmd);
3640 /* Transition the endpoint from using streams to being a "normal" endpoint
3643 * Modify the endpoint context state, submit a configure endpoint command,
3644 * and free all endpoint rings for streams if that completes successfully.
3646 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3647 struct usb_host_endpoint **eps, unsigned int num_eps,
3651 struct xhci_hcd *xhci;
3652 struct xhci_virt_device *vdev;
3653 struct xhci_command *command;
3654 struct xhci_input_control_ctx *ctrl_ctx;
3655 unsigned int ep_index;
3656 unsigned long flags;
3657 u32 changed_ep_bitmask;
3659 xhci = hcd_to_xhci(hcd);
3660 vdev = xhci->devs[udev->slot_id];
3662 /* Set up a configure endpoint command to remove the streams rings */
3663 spin_lock_irqsave(&xhci->lock, flags);
3664 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3665 udev, eps, num_eps);
3666 if (changed_ep_bitmask == 0) {
3667 spin_unlock_irqrestore(&xhci->lock, flags);
3671 /* Use the xhci_command structure from the first endpoint. We may have
3672 * allocated too many, but the driver may call xhci_free_streams() for
3673 * each endpoint it grouped into one call to xhci_alloc_streams().
3675 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3676 command = vdev->eps[ep_index].stream_info->free_streams_command;
3677 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3679 spin_unlock_irqrestore(&xhci->lock, flags);
3680 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3685 for (i = 0; i < num_eps; i++) {
3686 struct xhci_ep_ctx *ep_ctx;
3688 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3689 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3690 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3691 EP_GETTING_NO_STREAMS;
3693 xhci_endpoint_copy(xhci, command->in_ctx,
3694 vdev->out_ctx, ep_index);
3695 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3696 &vdev->eps[ep_index]);
3698 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3699 vdev->out_ctx, ctrl_ctx,
3700 changed_ep_bitmask, changed_ep_bitmask);
3701 spin_unlock_irqrestore(&xhci->lock, flags);
3703 /* Issue and wait for the configure endpoint command,
3704 * which must succeed.
3706 ret = xhci_configure_endpoint(xhci, udev, command,
3709 /* xHC rejected the configure endpoint command for some reason, so we
3710 * leave the streams rings intact.
3715 spin_lock_irqsave(&xhci->lock, flags);
3716 for (i = 0; i < num_eps; i++) {
3717 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3718 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3719 vdev->eps[ep_index].stream_info = NULL;
3720 /* FIXME Unset maxPstreams in endpoint context and
3721 * update deq ptr to point to normal string ring.
3723 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3724 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3726 spin_unlock_irqrestore(&xhci->lock, flags);
3732 * Deletes endpoint resources for endpoints that were active before a Reset
3733 * Device command, or a Disable Slot command. The Reset Device command leaves
3734 * the control endpoint intact, whereas the Disable Slot command deletes it.
3736 * Must be called with xhci->lock held.
3738 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3739 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3742 unsigned int num_dropped_eps = 0;
3743 unsigned int drop_flags = 0;
3745 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3746 if (virt_dev->eps[i].ring) {
3747 drop_flags |= 1 << i;
3751 xhci->num_active_eps -= num_dropped_eps;
3752 if (num_dropped_eps)
3753 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3754 "Dropped %u ep ctxs, flags = 0x%x, "
3756 num_dropped_eps, drop_flags,
3757 xhci->num_active_eps);
3761 * This submits a Reset Device Command, which will set the device state to 0,
3762 * set the device address to 0, and disable all the endpoints except the default
3763 * control endpoint. The USB core should come back and call
3764 * xhci_address_device(), and then re-set up the configuration. If this is
3765 * called because of a usb_reset_and_verify_device(), then the old alternate
3766 * settings will be re-installed through the normal bandwidth allocation
3769 * Wait for the Reset Device command to finish. Remove all structures
3770 * associated with the endpoints that were disabled. Clear the input device
3771 * structure? Reset the control endpoint 0 max packet size?
3773 * If the virt_dev to be reset does not exist or does not match the udev,
3774 * it means the device is lost, possibly due to the xHC restore error and
3775 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3776 * re-allocate the device.
3778 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3779 struct usb_device *udev)
3782 unsigned long flags;
3783 struct xhci_hcd *xhci;
3784 unsigned int slot_id;
3785 struct xhci_virt_device *virt_dev;
3786 struct xhci_command *reset_device_cmd;
3787 struct xhci_slot_ctx *slot_ctx;
3788 int old_active_eps = 0;
3790 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3793 xhci = hcd_to_xhci(hcd);
3794 slot_id = udev->slot_id;
3795 virt_dev = xhci->devs[slot_id];
3797 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3798 "not exist. Re-allocate the device\n", slot_id);
3799 ret = xhci_alloc_dev(hcd, udev);
3806 if (virt_dev->tt_info)
3807 old_active_eps = virt_dev->tt_info->active_eps;
3809 if (virt_dev->udev != udev) {
3810 /* If the virt_dev and the udev does not match, this virt_dev
3811 * may belong to another udev.
3812 * Re-allocate the device.
3814 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3815 "not match the udev. Re-allocate the device\n",
3817 ret = xhci_alloc_dev(hcd, udev);
3824 /* If device is not setup, there is no point in resetting it */
3825 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3826 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3827 SLOT_STATE_DISABLED)
3830 trace_xhci_discover_or_reset_device(slot_ctx);
3832 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3833 /* Allocate the command structure that holds the struct completion.
3834 * Assume we're in process context, since the normal device reset
3835 * process has to wait for the device anyway. Storage devices are
3836 * reset as part of error handling, so use GFP_NOIO instead of
3839 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3840 if (!reset_device_cmd) {
3841 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3845 /* Attempt to submit the Reset Device command to the command ring */
3846 spin_lock_irqsave(&xhci->lock, flags);
3848 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3850 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3851 spin_unlock_irqrestore(&xhci->lock, flags);
3852 goto command_cleanup;
3854 xhci_ring_cmd_db(xhci);
3855 spin_unlock_irqrestore(&xhci->lock, flags);
3857 /* Wait for the Reset Device command to finish */
3858 wait_for_completion(reset_device_cmd->completion);
3860 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3861 * unless we tried to reset a slot ID that wasn't enabled,
3862 * or the device wasn't in the addressed or configured state.
3864 ret = reset_device_cmd->status;
3866 case COMP_COMMAND_ABORTED:
3867 case COMP_COMMAND_RING_STOPPED:
3868 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3870 goto command_cleanup;
3871 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3872 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3873 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3875 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3876 xhci_dbg(xhci, "Not freeing device rings.\n");
3877 /* Don't treat this as an error. May change my mind later. */
3879 goto command_cleanup;
3881 xhci_dbg(xhci, "Successful reset device command.\n");
3884 if (xhci_is_vendor_info_code(xhci, ret))
3886 xhci_warn(xhci, "Unknown completion code %u for "
3887 "reset device command.\n", ret);
3889 goto command_cleanup;
3892 /* Free up host controller endpoint resources */
3893 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3894 spin_lock_irqsave(&xhci->lock, flags);
3895 /* Don't delete the default control endpoint resources */
3896 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3897 spin_unlock_irqrestore(&xhci->lock, flags);
3900 /* Everything but endpoint 0 is disabled, so free the rings. */
3901 for (i = 1; i < 31; i++) {
3902 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3904 if (ep->ep_state & EP_HAS_STREAMS) {
3905 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3906 xhci_get_endpoint_address(i));
3907 xhci_free_stream_info(xhci, ep->stream_info);
3908 ep->stream_info = NULL;
3909 ep->ep_state &= ~EP_HAS_STREAMS;
3913 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3914 xhci_free_endpoint_ring(xhci, virt_dev, i);
3916 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3917 xhci_drop_ep_from_interval_table(xhci,
3918 &virt_dev->eps[i].bw_info,
3923 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3925 /* If necessary, update the number of active TTs on this root port */
3926 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3927 virt_dev->flags = 0;
3931 xhci_free_command(xhci, reset_device_cmd);
3936 * At this point, the struct usb_device is about to go away, the device has
3937 * disconnected, and all traffic has been stopped and the endpoints have been
3938 * disabled. Free any HC data structures associated with that device.
3940 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3942 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3943 struct xhci_virt_device *virt_dev;
3944 struct xhci_slot_ctx *slot_ctx;
3948 * We called pm_runtime_get_noresume when the device was attached.
3949 * Decrement the counter here to allow controller to runtime suspend
3950 * if no devices remain.
3952 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3953 pm_runtime_put_noidle(hcd->self.controller);
3955 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3956 /* If the host is halted due to driver unload, we still need to free the
3959 if (ret <= 0 && ret != -ENODEV)
3962 virt_dev = xhci->devs[udev->slot_id];
3963 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3964 trace_xhci_free_dev(slot_ctx);
3966 /* Stop any wayward timer functions (which may grab the lock) */
3967 for (i = 0; i < 31; i++) {
3968 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3969 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3971 virt_dev->udev = NULL;
3972 xhci_disable_slot(xhci, udev->slot_id);
3973 xhci_free_virt_device(xhci, udev->slot_id);
3976 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3978 struct xhci_command *command;
3979 unsigned long flags;
3983 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3987 xhci_debugfs_remove_slot(xhci, slot_id);
3989 spin_lock_irqsave(&xhci->lock, flags);
3990 /* Don't disable the slot if the host controller is dead. */
3991 state = readl(&xhci->op_regs->status);
3992 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3993 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3994 spin_unlock_irqrestore(&xhci->lock, flags);
3999 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4002 spin_unlock_irqrestore(&xhci->lock, flags);
4006 xhci_ring_cmd_db(xhci);
4007 spin_unlock_irqrestore(&xhci->lock, flags);
4009 wait_for_completion(command->completion);
4011 if (command->status != COMP_SUCCESS)
4012 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4013 slot_id, command->status);
4015 xhci_free_command(xhci, command);
4021 * Checks if we have enough host controller resources for the default control
4024 * Must be called with xhci->lock held.
4026 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4028 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4029 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4030 "Not enough ep ctxs: "
4031 "%u active, need to add 1, limit is %u.",
4032 xhci->num_active_eps, xhci->limit_active_eps);
4035 xhci->num_active_eps += 1;
4036 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4037 "Adding 1 ep ctx, %u now active.",
4038 xhci->num_active_eps);
4044 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4045 * timed out, or allocating memory failed. Returns 1 on success.
4047 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4049 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4050 struct xhci_virt_device *vdev;
4051 struct xhci_slot_ctx *slot_ctx;
4052 unsigned long flags;
4054 struct xhci_command *command;
4056 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4060 spin_lock_irqsave(&xhci->lock, flags);
4061 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4063 spin_unlock_irqrestore(&xhci->lock, flags);
4064 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4065 xhci_free_command(xhci, command);
4068 xhci_ring_cmd_db(xhci);
4069 spin_unlock_irqrestore(&xhci->lock, flags);
4071 wait_for_completion(command->completion);
4072 slot_id = command->slot_id;
4074 if (!slot_id || command->status != COMP_SUCCESS) {
4075 xhci_err(xhci, "Error while assigning device slot ID\n");
4076 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4078 readl(&xhci->cap_regs->hcs_params1)));
4079 xhci_free_command(xhci, command);
4083 xhci_free_command(xhci, command);
4085 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4086 spin_lock_irqsave(&xhci->lock, flags);
4087 ret = xhci_reserve_host_control_ep_resources(xhci);
4089 spin_unlock_irqrestore(&xhci->lock, flags);
4090 xhci_warn(xhci, "Not enough host resources, "
4091 "active endpoint contexts = %u\n",
4092 xhci->num_active_eps);
4095 spin_unlock_irqrestore(&xhci->lock, flags);
4097 /* Use GFP_NOIO, since this function can be called from
4098 * xhci_discover_or_reset_device(), which may be called as part of
4099 * mass storage driver error handling.
4101 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4102 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4105 vdev = xhci->devs[slot_id];
4106 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4107 trace_xhci_alloc_dev(slot_ctx);
4109 udev->slot_id = slot_id;
4111 xhci_debugfs_create_slot(xhci, slot_id);
4114 * If resetting upon resume, we can't put the controller into runtime
4115 * suspend if there is a device attached.
4117 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4118 pm_runtime_get_noresume(hcd->self.controller);
4120 /* Is this a LS or FS device under a HS hub? */
4121 /* Hub or peripherial? */
4125 xhci_disable_slot(xhci, udev->slot_id);
4126 xhci_free_virt_device(xhci, udev->slot_id);
4132 * Issue an Address Device command and optionally send a corresponding
4133 * SetAddress request to the device.
4135 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4136 enum xhci_setup_dev setup)
4138 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4139 unsigned long flags;
4140 struct xhci_virt_device *virt_dev;
4142 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4143 struct xhci_slot_ctx *slot_ctx;
4144 struct xhci_input_control_ctx *ctrl_ctx;
4146 struct xhci_command *command = NULL;
4148 mutex_lock(&xhci->mutex);
4150 if (xhci->xhc_state) { /* dying, removing or halted */
4155 if (!udev->slot_id) {
4156 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4157 "Bad Slot ID %d", udev->slot_id);
4162 virt_dev = xhci->devs[udev->slot_id];
4164 if (WARN_ON(!virt_dev)) {
4166 * In plug/unplug torture test with an NEC controller,
4167 * a zero-dereference was observed once due to virt_dev = 0.
4168 * Print useful debug rather than crash if it is observed again!
4170 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4175 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4176 trace_xhci_setup_device_slot(slot_ctx);
4178 if (setup == SETUP_CONTEXT_ONLY) {
4179 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4180 SLOT_STATE_DEFAULT) {
4181 xhci_dbg(xhci, "Slot already in default state\n");
4186 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4192 command->in_ctx = virt_dev->in_ctx;
4194 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4195 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4197 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4203 * If this is the first Set Address since device plug-in or
4204 * virt_device realloaction after a resume with an xHCI power loss,
4205 * then set up the slot context.
4207 if (!slot_ctx->dev_info)
4208 xhci_setup_addressable_virt_dev(xhci, udev);
4209 /* Otherwise, update the control endpoint ring enqueue pointer. */
4211 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4212 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4213 ctrl_ctx->drop_flags = 0;
4215 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4216 le32_to_cpu(slot_ctx->dev_info) >> 27);
4218 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4219 spin_lock_irqsave(&xhci->lock, flags);
4220 trace_xhci_setup_device(virt_dev);
4221 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4222 udev->slot_id, setup);
4224 spin_unlock_irqrestore(&xhci->lock, flags);
4225 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4226 "FIXME: allocate a command ring segment");
4229 xhci_ring_cmd_db(xhci);
4230 spin_unlock_irqrestore(&xhci->lock, flags);
4232 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4233 wait_for_completion(command->completion);
4235 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4236 * the SetAddress() "recovery interval" required by USB and aborting the
4237 * command on a timeout.
4239 switch (command->status) {
4240 case COMP_COMMAND_ABORTED:
4241 case COMP_COMMAND_RING_STOPPED:
4242 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4245 case COMP_CONTEXT_STATE_ERROR:
4246 case COMP_SLOT_NOT_ENABLED_ERROR:
4247 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4248 act, udev->slot_id);
4251 case COMP_USB_TRANSACTION_ERROR:
4252 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4254 mutex_unlock(&xhci->mutex);
4255 ret = xhci_disable_slot(xhci, udev->slot_id);
4256 xhci_free_virt_device(xhci, udev->slot_id);
4258 xhci_alloc_dev(hcd, udev);
4259 kfree(command->completion);
4262 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4263 dev_warn(&udev->dev,
4264 "ERROR: Incompatible device for setup %s command\n", act);
4268 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4269 "Successful setup %s command", act);
4273 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4274 act, command->status);
4275 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4281 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4282 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4283 "Op regs DCBAA ptr = %#016llx", temp_64);
4284 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4285 "Slot ID %d dcbaa entry @%p = %#016llx",
4287 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4288 (unsigned long long)
4289 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4290 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4291 "Output Context DMA address = %#08llx",
4292 (unsigned long long)virt_dev->out_ctx->dma);
4293 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4294 le32_to_cpu(slot_ctx->dev_info) >> 27);
4296 * USB core uses address 1 for the roothubs, so we add one to the
4297 * address given back to us by the HC.
4299 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4300 le32_to_cpu(slot_ctx->dev_info) >> 27);
4301 /* Zero the input context control for later use */
4302 ctrl_ctx->add_flags = 0;
4303 ctrl_ctx->drop_flags = 0;
4304 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4305 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4307 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4308 "Internal device address = %d",
4309 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4311 mutex_unlock(&xhci->mutex);
4313 kfree(command->completion);
4319 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4321 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4324 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4326 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4330 * Transfer the port index into real index in the HW port status
4331 * registers. Caculate offset between the port's PORTSC register
4332 * and port status base. Divide the number of per port register
4333 * to get the real index. The raw port number bases 1.
4335 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4337 struct xhci_hub *rhub;
4339 rhub = xhci_get_rhub(hcd);
4340 return rhub->ports[port1 - 1]->hw_portnum + 1;
4344 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4345 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4347 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4348 struct usb_device *udev, u16 max_exit_latency)
4350 struct xhci_virt_device *virt_dev;
4351 struct xhci_command *command;
4352 struct xhci_input_control_ctx *ctrl_ctx;
4353 struct xhci_slot_ctx *slot_ctx;
4354 unsigned long flags;
4357 spin_lock_irqsave(&xhci->lock, flags);
4359 virt_dev = xhci->devs[udev->slot_id];
4362 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4363 * xHC was re-initialized. Exit latency will be set later after
4364 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4367 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4368 spin_unlock_irqrestore(&xhci->lock, flags);
4372 /* Attempt to issue an Evaluate Context command to change the MEL. */
4373 command = xhci->lpm_command;
4374 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4376 spin_unlock_irqrestore(&xhci->lock, flags);
4377 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4382 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4383 spin_unlock_irqrestore(&xhci->lock, flags);
4385 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4386 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4387 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4388 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4389 slot_ctx->dev_state = 0;
4391 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4392 "Set up evaluate context for LPM MEL change.");
4394 /* Issue and wait for the evaluate context command. */
4395 ret = xhci_configure_endpoint(xhci, udev, command,
4399 spin_lock_irqsave(&xhci->lock, flags);
4400 virt_dev->current_mel = max_exit_latency;
4401 spin_unlock_irqrestore(&xhci->lock, flags);
4408 /* BESL to HIRD Encoding array for USB2 LPM */
4409 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4410 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4412 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4413 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4414 struct usb_device *udev)
4416 int u2del, besl, besl_host;
4417 int besl_device = 0;
4420 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4421 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4423 if (field & USB_BESL_SUPPORT) {
4424 for (besl_host = 0; besl_host < 16; besl_host++) {
4425 if (xhci_besl_encoding[besl_host] >= u2del)
4428 /* Use baseline BESL value as default */
4429 if (field & USB_BESL_BASELINE_VALID)
4430 besl_device = USB_GET_BESL_BASELINE(field);
4431 else if (field & USB_BESL_DEEP_VALID)
4432 besl_device = USB_GET_BESL_DEEP(field);
4437 besl_host = (u2del - 51) / 75 + 1;
4440 besl = besl_host + besl_device;
4447 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4448 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4455 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4457 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4458 l1 = udev->l1_params.timeout / 256;
4460 /* device has preferred BESLD */
4461 if (field & USB_BESL_DEEP_VALID) {
4462 besld = USB_GET_BESL_DEEP(field);
4466 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4469 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4470 struct usb_device *udev, int enable)
4472 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4473 struct xhci_port **ports;
4474 __le32 __iomem *pm_addr, *hlpm_addr;
4475 u32 pm_val, hlpm_val, field;
4476 unsigned int port_num;
4477 unsigned long flags;
4478 int hird, exit_latency;
4481 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4484 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4488 if (!udev->parent || udev->parent->parent ||
4489 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4492 if (udev->usb2_hw_lpm_capable != 1)
4495 spin_lock_irqsave(&xhci->lock, flags);
4497 ports = xhci->usb2_rhub.ports;
4498 port_num = udev->portnum - 1;
4499 pm_addr = ports[port_num]->addr + PORTPMSC;
4500 pm_val = readl(pm_addr);
4501 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4503 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4504 enable ? "enable" : "disable", port_num + 1);
4507 /* Host supports BESL timeout instead of HIRD */
4508 if (udev->usb2_hw_lpm_besl_capable) {
4509 /* if device doesn't have a preferred BESL value use a
4510 * default one which works with mixed HIRD and BESL
4511 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4513 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4514 if ((field & USB_BESL_SUPPORT) &&
4515 (field & USB_BESL_BASELINE_VALID))
4516 hird = USB_GET_BESL_BASELINE(field);
4518 hird = udev->l1_params.besl;
4520 exit_latency = xhci_besl_encoding[hird];
4521 spin_unlock_irqrestore(&xhci->lock, flags);
4523 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4524 * input context for link powermanagement evaluate
4525 * context commands. It is protected by hcd->bandwidth
4526 * mutex and is shared by all devices. We need to set
4527 * the max ext latency in USB 2 BESL LPM as well, so
4528 * use the same mutex and xhci_change_max_exit_latency()
4530 mutex_lock(hcd->bandwidth_mutex);
4531 ret = xhci_change_max_exit_latency(xhci, udev,
4533 mutex_unlock(hcd->bandwidth_mutex);
4537 spin_lock_irqsave(&xhci->lock, flags);
4539 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4540 writel(hlpm_val, hlpm_addr);
4544 hird = xhci_calculate_hird_besl(xhci, udev);
4547 pm_val &= ~PORT_HIRD_MASK;
4548 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4549 writel(pm_val, pm_addr);
4550 pm_val = readl(pm_addr);
4552 writel(pm_val, pm_addr);
4556 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4557 writel(pm_val, pm_addr);
4560 if (udev->usb2_hw_lpm_besl_capable) {
4561 spin_unlock_irqrestore(&xhci->lock, flags);
4562 mutex_lock(hcd->bandwidth_mutex);
4563 xhci_change_max_exit_latency(xhci, udev, 0);
4564 mutex_unlock(hcd->bandwidth_mutex);
4565 readl_poll_timeout(ports[port_num]->addr, pm_val,
4566 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4572 spin_unlock_irqrestore(&xhci->lock, flags);
4576 /* check if a usb2 port supports a given extened capability protocol
4577 * only USB2 ports extended protocol capability values are cached.
4578 * Return 1 if capability is supported
4580 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4581 unsigned capability)
4583 u32 port_offset, port_count;
4586 for (i = 0; i < xhci->num_ext_caps; i++) {
4587 if (xhci->ext_caps[i] & capability) {
4588 /* port offsets starts at 1 */
4589 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4590 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4591 if (port >= port_offset &&
4592 port < port_offset + port_count)
4599 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4601 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4602 int portnum = udev->portnum - 1;
4604 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4607 /* we only support lpm for non-hub device connected to root hub yet */
4608 if (!udev->parent || udev->parent->parent ||
4609 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4612 if (xhci->hw_lpm_support == 1 &&
4613 xhci_check_usb2_port_capability(
4614 xhci, portnum, XHCI_HLC)) {
4615 udev->usb2_hw_lpm_capable = 1;
4616 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4617 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4618 if (xhci_check_usb2_port_capability(xhci, portnum,
4620 udev->usb2_hw_lpm_besl_capable = 1;
4626 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4628 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4629 static unsigned long long xhci_service_interval_to_ns(
4630 struct usb_endpoint_descriptor *desc)
4632 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4635 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4636 enum usb3_link_state state)
4638 unsigned long long sel;
4639 unsigned long long pel;
4640 unsigned int max_sel_pel;
4645 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4646 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4647 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4648 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4652 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4653 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4654 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4658 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4660 return USB3_LPM_DISABLED;
4663 if (sel <= max_sel_pel && pel <= max_sel_pel)
4664 return USB3_LPM_DEVICE_INITIATED;
4666 if (sel > max_sel_pel)
4667 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4668 "due to long SEL %llu ms\n",
4671 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4672 "due to long PEL %llu ms\n",
4674 return USB3_LPM_DISABLED;
4677 /* The U1 timeout should be the maximum of the following values:
4678 * - For control endpoints, U1 system exit latency (SEL) * 3
4679 * - For bulk endpoints, U1 SEL * 5
4680 * - For interrupt endpoints:
4681 * - Notification EPs, U1 SEL * 3
4682 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4683 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4685 static unsigned long long xhci_calculate_intel_u1_timeout(
4686 struct usb_device *udev,
4687 struct usb_endpoint_descriptor *desc)
4689 unsigned long long timeout_ns;
4693 ep_type = usb_endpoint_type(desc);
4695 case USB_ENDPOINT_XFER_CONTROL:
4696 timeout_ns = udev->u1_params.sel * 3;
4698 case USB_ENDPOINT_XFER_BULK:
4699 timeout_ns = udev->u1_params.sel * 5;
4701 case USB_ENDPOINT_XFER_INT:
4702 intr_type = usb_endpoint_interrupt_type(desc);
4703 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4704 timeout_ns = udev->u1_params.sel * 3;
4707 /* Otherwise the calculation is the same as isoc eps */
4709 case USB_ENDPOINT_XFER_ISOC:
4710 timeout_ns = xhci_service_interval_to_ns(desc);
4711 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4712 if (timeout_ns < udev->u1_params.sel * 2)
4713 timeout_ns = udev->u1_params.sel * 2;
4722 /* Returns the hub-encoded U1 timeout value. */
4723 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4724 struct usb_device *udev,
4725 struct usb_endpoint_descriptor *desc)
4727 unsigned long long timeout_ns;
4729 /* Prevent U1 if service interval is shorter than U1 exit latency */
4730 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4731 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4732 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4733 return USB3_LPM_DISABLED;
4737 if (xhci->quirks & XHCI_INTEL_HOST)
4738 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4740 timeout_ns = udev->u1_params.sel;
4742 /* The U1 timeout is encoded in 1us intervals.
4743 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4745 if (timeout_ns == USB3_LPM_DISABLED)
4748 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4750 /* If the necessary timeout value is bigger than what we can set in the
4751 * USB 3.0 hub, we have to disable hub-initiated U1.
4753 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4755 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4756 "due to long timeout %llu ms\n", timeout_ns);
4757 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4760 /* The U2 timeout should be the maximum of:
4761 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4762 * - largest bInterval of any active periodic endpoint (to avoid going
4763 * into lower power link states between intervals).
4764 * - the U2 Exit Latency of the device
4766 static unsigned long long xhci_calculate_intel_u2_timeout(
4767 struct usb_device *udev,
4768 struct usb_endpoint_descriptor *desc)
4770 unsigned long long timeout_ns;
4771 unsigned long long u2_del_ns;
4773 timeout_ns = 10 * 1000 * 1000;
4775 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4776 (xhci_service_interval_to_ns(desc) > timeout_ns))
4777 timeout_ns = xhci_service_interval_to_ns(desc);
4779 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4780 if (u2_del_ns > timeout_ns)
4781 timeout_ns = u2_del_ns;
4786 /* Returns the hub-encoded U2 timeout value. */
4787 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4788 struct usb_device *udev,
4789 struct usb_endpoint_descriptor *desc)
4791 unsigned long long timeout_ns;
4793 /* Prevent U2 if service interval is shorter than U2 exit latency */
4794 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4795 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4796 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4797 return USB3_LPM_DISABLED;
4801 if (xhci->quirks & XHCI_INTEL_HOST)
4802 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4804 timeout_ns = udev->u2_params.sel;
4806 /* The U2 timeout is encoded in 256us intervals */
4807 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4808 /* If the necessary timeout value is bigger than what we can set in the
4809 * USB 3.0 hub, we have to disable hub-initiated U2.
4811 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4813 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4814 "due to long timeout %llu ms\n", timeout_ns);
4815 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4818 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4819 struct usb_device *udev,
4820 struct usb_endpoint_descriptor *desc,
4821 enum usb3_link_state state,
4824 if (state == USB3_LPM_U1)
4825 return xhci_calculate_u1_timeout(xhci, udev, desc);
4826 else if (state == USB3_LPM_U2)
4827 return xhci_calculate_u2_timeout(xhci, udev, desc);
4829 return USB3_LPM_DISABLED;
4832 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4833 struct usb_device *udev,
4834 struct usb_endpoint_descriptor *desc,
4835 enum usb3_link_state state,
4840 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4841 desc, state, timeout);
4843 /* If we found we can't enable hub-initiated LPM, and
4844 * the U1 or U2 exit latency was too high to allow
4845 * device-initiated LPM as well, then we will disable LPM
4846 * for this device, so stop searching any further.
4848 if (alt_timeout == USB3_LPM_DISABLED) {
4849 *timeout = alt_timeout;
4852 if (alt_timeout > *timeout)
4853 *timeout = alt_timeout;
4857 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4858 struct usb_device *udev,
4859 struct usb_host_interface *alt,
4860 enum usb3_link_state state,
4865 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4866 if (xhci_update_timeout_for_endpoint(xhci, udev,
4867 &alt->endpoint[j].desc, state, timeout))
4873 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4874 enum usb3_link_state state)
4876 struct usb_device *parent;
4877 unsigned int num_hubs;
4879 if (state == USB3_LPM_U2)
4882 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4883 for (parent = udev->parent, num_hubs = 0; parent->parent;
4884 parent = parent->parent)
4890 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4891 " below second-tier hub.\n");
4892 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4893 "to decrease power consumption.\n");
4897 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4898 struct usb_device *udev,
4899 enum usb3_link_state state)
4901 if (xhci->quirks & XHCI_INTEL_HOST)
4902 return xhci_check_intel_tier_policy(udev, state);
4907 /* Returns the U1 or U2 timeout that should be enabled.
4908 * If the tier check or timeout setting functions return with a non-zero exit
4909 * code, that means the timeout value has been finalized and we shouldn't look
4910 * at any more endpoints.
4912 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4913 struct usb_device *udev, enum usb3_link_state state)
4915 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4916 struct usb_host_config *config;
4919 u16 timeout = USB3_LPM_DISABLED;
4921 if (state == USB3_LPM_U1)
4923 else if (state == USB3_LPM_U2)
4926 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4931 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4934 /* Gather some information about the currently installed configuration
4935 * and alternate interface settings.
4937 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4941 config = udev->actconfig;
4945 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4946 struct usb_driver *driver;
4947 struct usb_interface *intf = config->interface[i];
4952 /* Check if any currently bound drivers want hub-initiated LPM
4955 if (intf->dev.driver) {
4956 driver = to_usb_driver(intf->dev.driver);
4957 if (driver && driver->disable_hub_initiated_lpm) {
4958 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4959 state_name, driver->name);
4960 timeout = xhci_get_timeout_no_hub_lpm(udev,
4962 if (timeout == USB3_LPM_DISABLED)
4967 /* Not sure how this could happen... */
4968 if (!intf->cur_altsetting)
4971 if (xhci_update_timeout_for_interface(xhci, udev,
4972 intf->cur_altsetting,
4979 static int calculate_max_exit_latency(struct usb_device *udev,
4980 enum usb3_link_state state_changed,
4981 u16 hub_encoded_timeout)
4983 unsigned long long u1_mel_us = 0;
4984 unsigned long long u2_mel_us = 0;
4985 unsigned long long mel_us = 0;
4991 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4992 hub_encoded_timeout == USB3_LPM_DISABLED);
4993 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4994 hub_encoded_timeout == USB3_LPM_DISABLED);
4996 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4997 hub_encoded_timeout != USB3_LPM_DISABLED);
4998 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4999 hub_encoded_timeout != USB3_LPM_DISABLED);
5001 /* If U1 was already enabled and we're not disabling it,
5002 * or we're going to enable U1, account for the U1 max exit latency.
5004 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5006 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5007 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5009 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5011 mel_us = max(u1_mel_us, u2_mel_us);
5013 /* xHCI host controller max exit latency field is only 16 bits wide. */
5014 if (mel_us > MAX_EXIT) {
5015 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5016 "is too big.\n", mel_us);
5022 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5023 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5024 struct usb_device *udev, enum usb3_link_state state)
5026 struct xhci_hcd *xhci;
5027 u16 hub_encoded_timeout;
5031 xhci = hcd_to_xhci(hcd);
5032 /* The LPM timeout values are pretty host-controller specific, so don't
5033 * enable hub-initiated timeouts unless the vendor has provided
5034 * information about their timeout algorithm.
5036 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5037 !xhci->devs[udev->slot_id])
5038 return USB3_LPM_DISABLED;
5040 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5041 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5043 /* Max Exit Latency is too big, disable LPM. */
5044 hub_encoded_timeout = USB3_LPM_DISABLED;
5048 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5051 return hub_encoded_timeout;
5054 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5055 struct usb_device *udev, enum usb3_link_state state)
5057 struct xhci_hcd *xhci;
5060 xhci = hcd_to_xhci(hcd);
5061 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5062 !xhci->devs[udev->slot_id])
5065 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5066 return xhci_change_max_exit_latency(xhci, udev, mel);
5068 #else /* CONFIG_PM */
5070 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5071 struct usb_device *udev, int enable)
5076 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5081 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5082 struct usb_device *udev, enum usb3_link_state state)
5084 return USB3_LPM_DISABLED;
5087 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5088 struct usb_device *udev, enum usb3_link_state state)
5092 #endif /* CONFIG_PM */
5094 /*-------------------------------------------------------------------------*/
5096 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5097 * internal data structures for the device.
5099 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5100 struct usb_tt *tt, gfp_t mem_flags)
5102 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5103 struct xhci_virt_device *vdev;
5104 struct xhci_command *config_cmd;
5105 struct xhci_input_control_ctx *ctrl_ctx;
5106 struct xhci_slot_ctx *slot_ctx;
5107 unsigned long flags;
5108 unsigned think_time;
5111 /* Ignore root hubs */
5115 vdev = xhci->devs[hdev->slot_id];
5117 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5121 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5125 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5127 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5129 xhci_free_command(xhci, config_cmd);
5133 spin_lock_irqsave(&xhci->lock, flags);
5134 if (hdev->speed == USB_SPEED_HIGH &&
5135 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5136 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5137 xhci_free_command(xhci, config_cmd);
5138 spin_unlock_irqrestore(&xhci->lock, flags);
5142 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5143 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5144 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5145 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5147 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5148 * but it may be already set to 1 when setup an xHCI virtual
5149 * device, so clear it anyway.
5152 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5153 else if (hdev->speed == USB_SPEED_FULL)
5154 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5156 if (xhci->hci_version > 0x95) {
5157 xhci_dbg(xhci, "xHCI version %x needs hub "
5158 "TT think time and number of ports\n",
5159 (unsigned int) xhci->hci_version);
5160 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5161 /* Set TT think time - convert from ns to FS bit times.
5162 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5163 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5165 * xHCI 1.0: this field shall be 0 if the device is not a
5168 think_time = tt->think_time;
5169 if (think_time != 0)
5170 think_time = (think_time / 666) - 1;
5171 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5172 slot_ctx->tt_info |=
5173 cpu_to_le32(TT_THINK_TIME(think_time));
5175 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5176 "TT think time or number of ports\n",
5177 (unsigned int) xhci->hci_version);
5179 slot_ctx->dev_state = 0;
5180 spin_unlock_irqrestore(&xhci->lock, flags);
5182 xhci_dbg(xhci, "Set up %s for hub device.\n",
5183 (xhci->hci_version > 0x95) ?
5184 "configure endpoint" : "evaluate context");
5186 /* Issue and wait for the configure endpoint or
5187 * evaluate context command.
5189 if (xhci->hci_version > 0x95)
5190 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5193 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5196 xhci_free_command(xhci, config_cmd);
5200 static int xhci_get_frame(struct usb_hcd *hcd)
5202 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5203 /* EHCI mods by the periodic size. Why? */
5204 return readl(&xhci->run_regs->microframe_index) >> 3;
5207 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5209 struct xhci_hcd *xhci;
5211 * TODO: Check with DWC3 clients for sysdev according to
5214 struct device *dev = hcd->self.sysdev;
5215 unsigned int minor_rev;
5218 /* Accept arbitrarily long scatter-gather lists */
5219 hcd->self.sg_tablesize = ~0;
5221 /* support to build packet from discontinuous buffers */
5222 hcd->self.no_sg_constraint = 1;
5224 /* XHCI controllers don't stop the ep queue on short packets :| */
5225 hcd->self.no_stop_on_short = 1;
5227 xhci = hcd_to_xhci(hcd);
5229 if (usb_hcd_is_primary_hcd(hcd)) {
5230 xhci->main_hcd = hcd;
5231 xhci->usb2_rhub.hcd = hcd;
5232 /* Mark the first roothub as being USB 2.0.
5233 * The xHCI driver will register the USB 3.0 roothub.
5235 hcd->speed = HCD_USB2;
5236 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5238 * USB 2.0 roothub under xHCI has an integrated TT,
5239 * (rate matching hub) as opposed to having an OHCI/UHCI
5240 * companion controller.
5245 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5246 * should return 0x31 for sbrn, or that the minor revision
5247 * is a two digit BCD containig minor and sub-minor numbers.
5248 * This was later clarified in xHCI 1.2.
5250 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5251 * minor revision set to 0x1 instead of 0x10.
5253 if (xhci->usb3_rhub.min_rev == 0x1)
5256 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5258 switch (minor_rev) {
5260 hcd->speed = HCD_USB32;
5261 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5262 hcd->self.root_hub->rx_lanes = 2;
5263 hcd->self.root_hub->tx_lanes = 2;
5264 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5267 hcd->speed = HCD_USB31;
5268 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5269 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5272 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5274 minor_rev ? "Enhanced " : "");
5276 xhci->usb3_rhub.hcd = hcd;
5277 /* xHCI private pointer was set in xhci_pci_probe for the second
5278 * registered roothub.
5283 mutex_init(&xhci->mutex);
5284 xhci->cap_regs = hcd->regs;
5285 xhci->op_regs = hcd->regs +
5286 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5287 xhci->run_regs = hcd->regs +
5288 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5289 /* Cache read-only capability registers */
5290 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5291 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5292 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5293 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5294 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5295 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5296 if (xhci->hci_version > 0x100)
5297 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5299 xhci->quirks |= quirks;
5301 get_quirks(dev, xhci);
5303 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5304 * success event after a short transfer. This quirk will ignore such
5307 if (xhci->hci_version > 0x96)
5308 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5310 /* Make sure the HC is halted. */
5311 retval = xhci_halt(xhci);
5315 xhci_zero_64b_regs(xhci);
5317 xhci_dbg(xhci, "Resetting HCD\n");
5318 /* Reset the internal HC memory state and registers. */
5319 retval = xhci_reset(xhci);
5322 xhci_dbg(xhci, "Reset complete\n");
5325 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5326 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5327 * address memory pointers actually. So, this driver clears the AC64
5328 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5329 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5331 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5332 xhci->hcc_params &= ~BIT(0);
5334 /* Set dma_mask and coherent_dma_mask to 64-bits,
5335 * if xHC supports 64-bit addressing */
5336 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5337 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5338 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5339 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5342 * This is to avoid error in cases where a 32-bit USB
5343 * controller is used on a 64-bit capable system.
5345 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5348 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5349 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5352 xhci_dbg(xhci, "Calling HCD init\n");
5353 /* Initialize HCD and host controller data structures. */
5354 retval = xhci_init(hcd);
5357 xhci_dbg(xhci, "Called HCD init\n");
5359 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5360 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5364 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5366 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5367 struct usb_host_endpoint *ep)
5369 struct xhci_hcd *xhci;
5370 struct usb_device *udev;
5371 unsigned int slot_id;
5372 unsigned int ep_index;
5373 unsigned long flags;
5375 xhci = hcd_to_xhci(hcd);
5377 spin_lock_irqsave(&xhci->lock, flags);
5378 udev = (struct usb_device *)ep->hcpriv;
5379 slot_id = udev->slot_id;
5380 ep_index = xhci_get_endpoint_index(&ep->desc);
5382 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5383 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5384 spin_unlock_irqrestore(&xhci->lock, flags);
5387 static const struct hc_driver xhci_hc_driver = {
5388 .description = "xhci-hcd",
5389 .product_desc = "xHCI Host Controller",
5390 .hcd_priv_size = sizeof(struct xhci_hcd),
5393 * generic hardware linkage
5396 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5400 * basic lifecycle operations
5402 .reset = NULL, /* set in xhci_init_driver() */
5405 .shutdown = xhci_shutdown,
5408 * managing i/o requests and associated device resources
5410 .map_urb_for_dma = xhci_map_urb_for_dma,
5411 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5412 .urb_enqueue = xhci_urb_enqueue,
5413 .urb_dequeue = xhci_urb_dequeue,
5414 .alloc_dev = xhci_alloc_dev,
5415 .free_dev = xhci_free_dev,
5416 .alloc_streams = xhci_alloc_streams,
5417 .free_streams = xhci_free_streams,
5418 .add_endpoint = xhci_add_endpoint,
5419 .drop_endpoint = xhci_drop_endpoint,
5420 .endpoint_disable = xhci_endpoint_disable,
5421 .endpoint_reset = xhci_endpoint_reset,
5422 .check_bandwidth = xhci_check_bandwidth,
5423 .reset_bandwidth = xhci_reset_bandwidth,
5424 .address_device = xhci_address_device,
5425 .enable_device = xhci_enable_device,
5426 .update_hub_device = xhci_update_hub_device,
5427 .reset_device = xhci_discover_or_reset_device,
5430 * scheduling support
5432 .get_frame_number = xhci_get_frame,
5437 .hub_control = xhci_hub_control,
5438 .hub_status_data = xhci_hub_status_data,
5439 .bus_suspend = xhci_bus_suspend,
5440 .bus_resume = xhci_bus_resume,
5441 .get_resuming_ports = xhci_get_resuming_ports,
5444 * call back when device connected and addressed
5446 .update_device = xhci_update_device,
5447 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5448 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5449 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5450 .find_raw_port_number = xhci_find_raw_port_number,
5451 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5454 void xhci_init_driver(struct hc_driver *drv,
5455 const struct xhci_driver_overrides *over)
5459 /* Copy the generic table to drv then apply the overrides */
5460 *drv = xhci_hc_driver;
5463 drv->hcd_priv_size += over->extra_priv_size;
5465 drv->reset = over->reset;
5467 drv->start = over->start;
5468 if (over->add_endpoint)
5469 drv->add_endpoint = over->add_endpoint;
5470 if (over->drop_endpoint)
5471 drv->drop_endpoint = over->drop_endpoint;
5472 if (over->check_bandwidth)
5473 drv->check_bandwidth = over->check_bandwidth;
5474 if (over->reset_bandwidth)
5475 drv->reset_bandwidth = over->reset_bandwidth;
5478 EXPORT_SYMBOL_GPL(xhci_init_driver);
5480 MODULE_DESCRIPTION(DRIVER_DESC);
5481 MODULE_AUTHOR(DRIVER_AUTHOR);
5482 MODULE_LICENSE("GPL");
5484 static int __init xhci_hcd_init(void)
5487 * Check the compiler generated sizes of structures that must be laid
5488 * out in specific ways for hardware access.
5490 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5491 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5492 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5493 /* xhci_device_control has eight fields, and also
5494 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5496 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5497 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5498 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5499 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5500 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5501 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5502 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5507 xhci_debugfs_create_root();
5513 * If an init function is provided, an exit function must also be provided
5514 * to allow module unload.
5516 static void __exit xhci_hcd_fini(void)
5518 xhci_debugfs_remove_root();
5521 module_init(xhci_hcd_init);
5522 module_exit(xhci_hcd_fini);