drivers/usb/host/xhci-rcar.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver for R-Car SoCs
   4  *
   5  * Copyright (C) 2014 Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/firmware.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/usb/phy.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-plat.h"
  18 #include "xhci-rzv2m.h"
  19
  20 #define XHCI_RCAR_FIRMWARE_NAME_V1      "r8a779x_usb3_v1.dlmem"
  21 #define XHCI_RCAR_FIRMWARE_NAME_V3      "r8a779x_usb3_v3.dlmem"
  22
  23 /*
  24 * - The V3 firmware is for all R-Car Gen3
  25 * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
  26 *   performance degradation. So, this driver continues to use the V1 if R-Car
  27 *   Gen2.
  28 * - The V1 firmware is impossible to use on R-Car Gen3.
  29 */
  30 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
  31 MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
  32
  33 /*** Register Offset ***/
  34 #define RCAR_USB3_AXH_STA       0x104   /* AXI Host Control Status */
  35 #define RCAR_USB3_INT_ENA       0x224   /* Interrupt Enable */
  36 #define RCAR_USB3_DL_CTRL       0x250   /* FW Download Control & Status */
  37 #define RCAR_USB3_FW_DATA0      0x258   /* FW Data0 */
  38
  39 #define RCAR_USB3_LCLK          0xa44   /* LCLK Select */
  40 #define RCAR_USB3_CONF1         0xa48   /* USB3.0 Configuration1 */
  41 #define RCAR_USB3_CONF2         0xa5c   /* USB3.0 Configuration2 */
  42 #define RCAR_USB3_CONF3         0xaa8   /* USB3.0 Configuration3 */
  43 #define RCAR_USB3_RX_POL        0xab0   /* USB3.0 RX Polarity */
  44 #define RCAR_USB3_TX_POL        0xab8   /* USB3.0 TX Polarity */
  45
  46 /*** Register Settings ***/
  47 /* AXI Host Control Status */
  48 #define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE         0x00010000
  49 #define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE         0x00000001
  50 #define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
  51                                            RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
  52
  53 /* Interrupt Enable */
  54 #define RCAR_USB3_INT_XHC_ENA   0x00000001
  55 #define RCAR_USB3_INT_PME_ENA   0x00000002
  56 #define RCAR_USB3_INT_HSE_ENA   0x00000004
  57 #define RCAR_USB3_INT_ENA_VAL   (RCAR_USB3_INT_XHC_ENA | \
  58                                 RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
  59
  60 /* FW Download Control & Status */
  61 #define RCAR_USB3_DL_CTRL_ENABLE        0x00000001
  62 #define RCAR_USB3_DL_CTRL_FW_SUCCESS    0x00000010
  63 #define RCAR_USB3_DL_CTRL_FW_SET_DATA0  0x00000100
  64
  65 /* LCLK Select */
  66 #define RCAR_USB3_LCLK_ENA_VAL  0x01030001
  67
  68 /* USB3.0 Configuration */
  69 #define RCAR_USB3_CONF1_VAL     0x00030204
  70 #define RCAR_USB3_CONF2_VAL     0x00030300
  71 #define RCAR_USB3_CONF3_VAL     0x13802007
  72
  73 /* USB3.0 Polarity */
  74 #define RCAR_USB3_RX_POL_VAL    BIT(21)
  75 #define RCAR_USB3_TX_POL_VAL    BIT(4)
  76
  77 static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
  78 {
  79         /* LCLK Select */
  80         writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
  81         /* USB3.0 Configuration */
  82         writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
  83         writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
  84         writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
  85         /* USB3.0 Polarity */
  86         writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
  87         writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
  88 }
  89
  90 static int xhci_rcar_is_gen2(struct device *dev)
  91 {
  92         struct device_node *node = dev->of_node;
  93
  94         return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
  95                 of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
  96                 of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
  97                 of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
  98 }
  99
 100 static void xhci_rcar_start(struct usb_hcd *hcd)
 101 {
 102         u32 temp;
 103
 104         if (hcd->regs != NULL) {
 105                 /* Interrupt Enable */
 106                 temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
 107                 temp |= RCAR_USB3_INT_ENA_VAL;
 108                 writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
 109                 if (xhci_rcar_is_gen2(hcd->self.controller))
 110                         xhci_rcar_start_gen2(hcd);
 111         }
 112 }
 113
 114 static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
 115 {
 116         struct device *dev = hcd->self.controller;
 117         void __iomem *regs = hcd->regs;
 118         struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
 119         const struct firmware *fw;
 120         int retval, index, j;
 121         u32 data, val, temp;
 122
 123         /*
 124          * According to the datasheet, "Upon the completion of FW Download,
 125          * there is no need to write or reload FW".
 126          */
 127         if (readl(regs + RCAR_USB3_DL_CTRL) & RCAR_USB3_DL_CTRL_FW_SUCCESS)
 128                 return 0;
 129
 130         /* request R-Car USB3.0 firmware */
 131         retval = request_firmware(&fw, priv->firmware_name, dev);
 132         if (retval)
 133                 return retval;
 134
 135         /* download R-Car USB3.0 firmware */
 136         temp = readl(regs + RCAR_USB3_DL_CTRL);
 137         temp |= RCAR_USB3_DL_CTRL_ENABLE;
 138         writel(temp, regs + RCAR_USB3_DL_CTRL);
 139
 140         for (index = 0; index < fw->size; index += 4) {
 141                 /* to avoid reading beyond the end of the buffer */
 142                 for (data = 0, j = 3; j >= 0; j--) {
 143                         if ((j + index) < fw->size)
 144                                 data |= fw->data[index + j] << (8 * j);
 145                 }
 146                 writel(data, regs + RCAR_USB3_FW_DATA0);
 147                 temp = readl(regs + RCAR_USB3_DL_CTRL);
 148                 temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
 149                 writel(temp, regs + RCAR_USB3_DL_CTRL);
 150
 151                 retval = readl_poll_timeout_atomic(regs + RCAR_USB3_DL_CTRL,
 152                                 val, !(val & RCAR_USB3_DL_CTRL_FW_SET_DATA0),
 153                                 1, 10000);
 154                 if (retval < 0)
 155                         break;
 156         }
 157
 158         temp = readl(regs + RCAR_USB3_DL_CTRL);
 159         temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
 160         writel(temp, regs + RCAR_USB3_DL_CTRL);
 161
 162         retval = readl_poll_timeout_atomic((regs + RCAR_USB3_DL_CTRL),
 163                         val, val & RCAR_USB3_DL_CTRL_FW_SUCCESS, 1, 10000);
 164
 165         release_firmware(fw);
 166
 167         return retval;
 168 }
 169
 170 static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
 171 {
 172         int retval;
 173         u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
 174
 175         retval = readl_poll_timeout_atomic(hcd->regs + RCAR_USB3_AXH_STA,
 176                         val, (val & mask) == mask, 1, 1000);
 177         return !retval;
 178 }
 179
 180 /* This function needs to initialize a "phy" of usb before */
 181 static int xhci_rcar_init_quirk(struct usb_hcd *hcd)
 182 {
 183         /* If hcd->regs is NULL, we don't just call the following function */
 184         if (!hcd->regs)
 185                 return 0;
 186
 187         if (!xhci_rcar_wait_for_pll_active(hcd))
 188                 return -ETIMEDOUT;
 189
 190         return xhci_rcar_download_firmware(hcd);
 191 }
 192
 193 static int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
 194 {
 195         int ret;
 196
 197         ret = xhci_rcar_download_firmware(hcd);
 198         if (!ret)
 199                 xhci_rcar_start(hcd);
 200
 201         return ret;
 202 }
 203
 204 /*
 205  * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
 206  * to 1. However, these SoCs don't support 64-bit address memory
 207  * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
 208  * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
 209  * xhci_gen_setup() by using the XHCI_NO_64BIT_SUPPORT quirk.
 210  *
 211  * And, since the firmware/internal CPU control the USBSTS.STS_HALT
 212  * and the process speed is down when the roothub port enters U3,
 213  * long delay for the handshake of STS_HALT is neeed in xhci_suspend()
 214  * by using the XHCI_SLOW_SUSPEND quirk.
 215  */
 216 #define SET_XHCI_PLAT_PRIV_FOR_RCAR(firmware)                           \
 217         .firmware_name = firmware,                                      \
 218         .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH |        \
 219                   XHCI_SLOW_SUSPEND,                                    \
 220         .init_quirk = xhci_rcar_init_quirk,                             \
 221         .plat_start = xhci_rcar_start,                                  \
 222         .resume_quirk = xhci_rcar_resume_quirk,
 223
 224 static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen2 = {
 225         SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V1)
 226 };
 227
 228 static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = {
 229         SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V3)
 230 };
 231
 232 static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
 233         .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH |
 234                   XHCI_SLOW_SUSPEND,
 235         .init_quirk = xhci_rzv2m_init_quirk,
 236         .plat_start = xhci_rzv2m_start,
 237 };
 238
 239 static const struct of_device_id usb_xhci_of_match[] = {
 240         {
 241                 .compatible = "renesas,xhci-r8a7790",
 242                 .data = &xhci_plat_renesas_rcar_gen2,
 243         }, {
 244                 .compatible = "renesas,xhci-r8a7791",
 245                 .data = &xhci_plat_renesas_rcar_gen2,
 246         }, {
 247                 .compatible = "renesas,xhci-r8a7793",
 248                 .data = &xhci_plat_renesas_rcar_gen2,
 249         }, {
 250                 .compatible = "renesas,xhci-r8a7795",
 251                 .data = &xhci_plat_renesas_rcar_gen3,
 252         }, {
 253                 .compatible = "renesas,xhci-r8a7796",
 254                 .data = &xhci_plat_renesas_rcar_gen3,
 255         }, {
 256                 .compatible = "renesas,rcar-gen2-xhci",
 257                 .data = &xhci_plat_renesas_rcar_gen2,
 258         }, {
 259                 .compatible = "renesas,rcar-gen3-xhci",
 260                 .data = &xhci_plat_renesas_rcar_gen3,
 261         }, {
 262                 .compatible = "renesas,rzv2m-xhci",
 263                 .data = &xhci_plat_renesas_rzv2m,
 264         },
 265         { },
 266 };
 267 MODULE_DEVICE_TABLE(of, usb_xhci_of_match);
 268
 269 static int xhci_renesas_probe(struct platform_device *pdev)
 270 {
 271         const struct xhci_plat_priv *priv_match;
 272
 273         priv_match = of_device_get_match_data(&pdev->dev);
 274
 275         return xhci_plat_probe(pdev, NULL, priv_match);
 276 }
 277
 278 static struct platform_driver usb_xhci_renesas_driver = {
 279         .probe = xhci_renesas_probe,
 280         .remove_new = xhci_plat_remove,
 281         .shutdown = usb_hcd_platform_shutdown,
 282         .driver = {
 283                 .name = "xhci-renesas-hcd",
 284                 .pm = &xhci_plat_pm_ops,
 285                 .of_match_table = usb_xhci_of_match,
 286         },
 287 };
 288 module_platform_driver(usb_xhci_renesas_driver);
 289
 290 MODULE_DESCRIPTION("xHCI Platform Host Controller Driver for Renesas R-Car and RZ");
 291 MODULE_LICENSE("GPL");