1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek xHCI Host Controller Driver
5 * Copyright (c) 2015 MediaTek Inc.
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #include <linux/dma-mapping.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/reset.h>
26 /* ip_pw_ctrl0 register */
27 #define CTRL0_IP_SW_RST BIT(0)
29 /* ip_pw_ctrl1 register */
30 #define CTRL1_IP_HOST_PDN BIT(0)
32 /* ip_pw_ctrl2 register */
33 #define CTRL2_IP_DEV_PDN BIT(0)
35 /* ip_pw_sts1 register */
36 #define STS1_IP_SLEEP_STS BIT(30)
37 #define STS1_U3_MAC_RST BIT(16)
38 #define STS1_XHCI_RST BIT(11)
39 #define STS1_SYS125_RST BIT(10)
40 #define STS1_REF_RST BIT(8)
41 #define STS1_SYSPLL_STABLE BIT(0)
43 /* ip_xhci_cap register */
44 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
45 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
47 /* u3_ctrl_p register */
48 #define CTRL_U3_PORT_HOST_SEL BIT(2)
49 #define CTRL_U3_PORT_PDN BIT(1)
50 #define CTRL_U3_PORT_DIS BIT(0)
52 /* u2_ctrl_p register */
53 #define CTRL_U2_PORT_HOST_SEL BIT(2)
54 #define CTRL_U2_PORT_PDN BIT(1)
55 #define CTRL_U2_PORT_DIS BIT(0)
57 /* u2_phy_pll register */
58 #define CTRL_U2_FORCE_PLL_STB BIT(28)
61 #define LS_EOF_CFG 0x930
62 #define LSEOF_OFFSET 0x89
64 #define FS_EOF_CFG 0x934
65 #define FSEOF_OFFSET 0x2e
67 #define SS_GEN1_EOF_CFG 0x93c
68 #define SSG1EOF_OFFSET 0x78
70 #define HFCNTR_CFG 0x944
71 #define ITP_DELTA_CLK (0xa << 1)
72 #define ITP_DELTA_CLK_MASK GENMASK(5, 1)
73 #define FRMCNT_LEV1_RANG (0x12b << 8)
74 #define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
76 #define SS_GEN2_EOF_CFG 0x990
77 #define SSG2EOF_OFFSET 0x3c
79 #define XSEOF_OFFSET_MASK GENMASK(11, 0)
81 /* usb remote wakeup registers in syscon */
84 #define PERI_WK_CTRL1 0x4
85 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
86 #define WC1_IS_EN BIT(25)
87 #define WC1_IS_P BIT(6) /* polarity for ip sleep */
90 #define PERI_WK_CTRL0 0x0
91 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
92 #define WC0_IS_P BIT(12) /* polarity */
93 #define WC0_IS_EN BIT(6)
96 #define WC0_SSUSB0_CDEN BIT(6)
97 #define WC0_IS_SPM_EN BIT(1)
100 #define PERI_WK_CTRL0_8195 0x04
101 #define WC0_IS_P_95 BIT(30) /* polarity */
102 #define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27))
103 #define WC0_IS_EN_P3_95 BIT(26)
104 #define WC0_IS_EN_P2_95 BIT(25)
105 #define WC0_IS_EN_P1_95 BIT(24)
107 #define PERI_WK_CTRL1_8195 0x20
108 #define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28))
109 #define WC1_IS_P_95 BIT(12)
110 #define WC1_IS_EN_P0_95 BIT(6)
113 #define PERI_SSUSB_SPM_CTRL 0x0
114 #define SSC_IP_SLEEP_EN BIT(4)
115 #define SSC_SPM_INT_EN BIT(1)
117 enum ssusb_uwk_vers {
120 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
121 SSUSB_UWK_V1_2, /* specific revision 1.2 */
122 SSUSB_UWK_V1_3, /* mt8195 IP0 */
123 SSUSB_UWK_V1_4, /* mt8195 IP1 */
124 SSUSB_UWK_V1_5, /* mt8195 IP2 */
125 SSUSB_UWK_V1_6, /* mt8195 IP3 */
129 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
130 * is calculated from the frame counter clock 24M, but in fact, the clock
131 * is 48M, add workaround for it.
133 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
135 struct device *dev = mtk->dev;
136 struct usb_hcd *hcd = mtk->hcd;
139 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
142 value = readl(hcd->regs + HFCNTR_CFG);
143 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
144 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
145 writel(value, hcd->regs + HFCNTR_CFG);
147 value = readl(hcd->regs + LS_EOF_CFG);
148 value &= ~XSEOF_OFFSET_MASK;
149 value |= LSEOF_OFFSET;
150 writel(value, hcd->regs + LS_EOF_CFG);
152 value = readl(hcd->regs + FS_EOF_CFG);
153 value &= ~XSEOF_OFFSET_MASK;
154 value |= FSEOF_OFFSET;
155 writel(value, hcd->regs + FS_EOF_CFG);
157 value = readl(hcd->regs + SS_GEN1_EOF_CFG);
158 value &= ~XSEOF_OFFSET_MASK;
159 value |= SSG1EOF_OFFSET;
160 writel(value, hcd->regs + SS_GEN1_EOF_CFG);
162 value = readl(hcd->regs + SS_GEN2_EOF_CFG);
163 value &= ~XSEOF_OFFSET_MASK;
164 value |= SSG2EOF_OFFSET;
165 writel(value, hcd->regs + SS_GEN2_EOF_CFG);
168 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
170 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
171 u32 value, check_val;
172 int u3_ports_disabled = 0;
179 /* power on host ip */
180 value = readl(&ippc->ip_pw_ctr1);
181 value &= ~CTRL1_IP_HOST_PDN;
182 writel(value, &ippc->ip_pw_ctr1);
184 /* power on and enable u3 ports except skipped ones */
185 for (i = 0; i < mtk->num_u3_ports; i++) {
186 if ((0x1 << i) & mtk->u3p_dis_msk) {
191 value = readl(&ippc->u3_ctrl_p[i]);
192 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
193 value |= CTRL_U3_PORT_HOST_SEL;
194 writel(value, &ippc->u3_ctrl_p[i]);
197 /* power on and enable all u2 ports except skipped ones */
198 for (i = 0; i < mtk->num_u2_ports; i++) {
199 if (BIT(i) & mtk->u2p_dis_msk)
202 value = readl(&ippc->u2_ctrl_p[i]);
203 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
204 value |= CTRL_U2_PORT_HOST_SEL;
205 writel(value, &ippc->u2_ctrl_p[i]);
209 * wait for clocks to be stable, and clock domains reset to
210 * be inactive after power on and enable ports
212 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
213 STS1_SYS125_RST | STS1_XHCI_RST;
215 if (mtk->num_u3_ports > u3_ports_disabled)
216 check_val |= STS1_U3_MAC_RST;
218 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
219 (check_val == (value & check_val)), 100, 20000);
221 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
228 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
230 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
238 /* power down u3 ports except skipped ones */
239 for (i = 0; i < mtk->num_u3_ports; i++) {
240 if ((0x1 << i) & mtk->u3p_dis_msk)
243 value = readl(&ippc->u3_ctrl_p[i]);
244 value |= CTRL_U3_PORT_PDN;
245 writel(value, &ippc->u3_ctrl_p[i]);
248 /* power down all u2 ports except skipped ones */
249 for (i = 0; i < mtk->num_u2_ports; i++) {
250 if (BIT(i) & mtk->u2p_dis_msk)
253 value = readl(&ippc->u2_ctrl_p[i]);
254 value |= CTRL_U2_PORT_PDN;
255 writel(value, &ippc->u2_ctrl_p[i]);
258 /* power down host ip */
259 value = readl(&ippc->ip_pw_ctr1);
260 value |= CTRL1_IP_HOST_PDN;
261 writel(value, &ippc->ip_pw_ctr1);
263 /* wait for host ip to sleep */
264 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
265 (value & STS1_IP_SLEEP_STS), 100, 100000);
267 dev_err(mtk->dev, "ip sleep failed!!!\n");
268 else /* workaound for platforms using low level latch */
269 usleep_range(100, 200);
274 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
276 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
283 value = readl(&ippc->ip_pw_ctr0);
284 value |= CTRL0_IP_SW_RST;
285 writel(value, &ippc->ip_pw_ctr0);
287 value = readl(&ippc->ip_pw_ctr0);
288 value &= ~CTRL0_IP_SW_RST;
289 writel(value, &ippc->ip_pw_ctr0);
292 * device ip is default power-on in fact
293 * power down device ip, otherwise ip-sleep will fail
295 value = readl(&ippc->ip_pw_ctr2);
296 value |= CTRL2_IP_DEV_PDN;
297 writel(value, &ippc->ip_pw_ctr2);
299 value = readl(&ippc->ip_xhci_cap);
300 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
301 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
302 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
303 mtk->num_u2_ports, mtk->num_u3_ports);
305 return xhci_mtk_host_enable(mtk);
308 /* only clocks can be turn off for ip-sleep wakeup mode */
309 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
313 switch (mtk->uwk_vers) {
315 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
316 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
317 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
320 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
321 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
322 val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;
325 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
326 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
327 val = enable ? msk : 0;
330 reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
331 msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
332 val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
335 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
336 msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
337 val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
340 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
341 msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
342 val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
345 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
346 msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
347 val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
350 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
351 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
352 val = enable ? msk : 0;
357 regmap_update_bits(mtk->uwk, reg, msk, val);
360 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
361 struct device_node *dn)
363 struct of_phandle_args args;
366 /* Wakeup function is optional */
367 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
371 ret = of_parse_phandle_with_fixed_args(dn,
372 "mediatek,syscon-wakeup", 2, 0, &args);
376 mtk->uwk_reg_base = args.args[0];
377 mtk->uwk_vers = args.args[1];
378 mtk->uwk = syscon_node_to_regmap(args.np);
379 of_node_put(args.np);
380 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
381 mtk->uwk_reg_base, mtk->uwk_vers);
383 return PTR_ERR_OR_ZERO(mtk->uwk);
386 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
389 usb_wakeup_ip_sleep_set(mtk, enable);
392 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
394 struct clk_bulk_data *clks = mtk->clks;
396 clks[0].id = "sys_ck";
397 clks[1].id = "xhci_ck";
398 clks[2].id = "ref_ck";
399 clks[3].id = "mcu_ck";
400 clks[4].id = "dma_ck";
401 clks[5].id = "frmcnt_ck";
403 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
406 static int xhci_mtk_vregs_get(struct xhci_hcd_mtk *mtk)
408 struct regulator_bulk_data *supplies = mtk->supplies;
410 supplies[0].supply = "vbus";
411 supplies[1].supply = "vusb33";
413 return devm_regulator_bulk_get(mtk->dev, BULK_VREGS_NUM, supplies);
416 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
418 struct usb_hcd *hcd = xhci_to_hcd(xhci);
419 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
422 * As of now platform drivers don't provide MSI support so we ensure
423 * here that the generic code does not try to make a pci_dev from our
424 * dev struct in order to setup MSI
426 xhci->quirks |= XHCI_PLAT;
427 xhci->quirks |= XHCI_MTK_HOST;
429 * MTK host controller gives a spurious successful event after a
430 * short transfer. Ignore it.
432 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
433 if (mtk->lpm_support)
434 xhci->quirks |= XHCI_LPM_SUPPORT;
435 if (mtk->u2_lpm_disable)
436 xhci->quirks |= XHCI_HW_LPM_DISABLE;
439 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
440 * and it's 3 when support it.
442 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
443 xhci->quirks |= XHCI_BROKEN_STREAMS;
446 /* called during probe() after chip reset completes */
447 static int xhci_mtk_setup(struct usb_hcd *hcd)
449 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
452 if (usb_hcd_is_primary_hcd(hcd)) {
453 ret = xhci_mtk_ssusb_config(mtk);
457 /* workaround only for mt8195 */
458 xhci_mtk_set_frame_interval(mtk);
461 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
465 if (usb_hcd_is_primary_hcd(hcd))
466 ret = xhci_mtk_sch_init(mtk);
471 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
472 .reset = xhci_mtk_setup,
473 .add_endpoint = xhci_mtk_add_ep,
474 .drop_endpoint = xhci_mtk_drop_ep,
475 .check_bandwidth = xhci_mtk_check_bandwidth,
476 .reset_bandwidth = xhci_mtk_reset_bandwidth,
479 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
481 static int xhci_mtk_probe(struct platform_device *pdev)
483 struct device *dev = &pdev->dev;
484 struct device_node *node = dev->of_node;
485 struct xhci_hcd_mtk *mtk;
486 const struct hc_driver *driver;
487 struct xhci_hcd *xhci;
488 struct resource *res;
489 struct usb_hcd *usb3_hcd;
498 driver = &xhci_mtk_hc_driver;
499 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
505 ret = xhci_mtk_vregs_get(mtk);
507 return dev_err_probe(dev, ret, "Failed to get regulators\n");
509 ret = xhci_mtk_clks_get(mtk);
513 irq = platform_get_irq_byname_optional(pdev, "host");
515 if (irq == -EPROBE_DEFER)
518 /* for backward compatibility */
519 irq = platform_get_irq(pdev, 0);
524 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
525 if (wakeup_irq == -EPROBE_DEFER)
528 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
529 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
530 /* optional property, ignore the error if it does not exist */
531 of_property_read_u32(node, "mediatek,u3p-dis-msk",
533 of_property_read_u32(node, "mediatek,u2p-dis-msk",
536 ret = usb_wakeup_of_property_parse(mtk, node);
538 dev_err(dev, "failed to parse uwk property\n");
542 pm_runtime_set_active(dev);
543 pm_runtime_use_autosuspend(dev);
544 pm_runtime_set_autosuspend_delay(dev, 4000);
545 pm_runtime_enable(dev);
546 pm_runtime_get_sync(dev);
548 ret = regulator_bulk_enable(BULK_VREGS_NUM, mtk->supplies);
552 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
556 ret = device_reset_optional(dev);
558 dev_err_probe(dev, ret, "failed to reset controller\n");
562 hcd = usb_create_hcd(driver, dev, dev_name(dev));
569 * USB 2.0 roothub is stored in the platform_device.
570 * Swap it with mtk HCD.
572 mtk->hcd = platform_get_drvdata(pdev);
573 platform_set_drvdata(pdev, mtk);
575 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
576 hcd->regs = devm_ioremap_resource(dev, res);
577 if (IS_ERR(hcd->regs)) {
578 ret = PTR_ERR(hcd->regs);
581 hcd->rsrc_start = res->start;
582 hcd->rsrc_len = resource_size(res);
584 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
585 if (res) { /* ippc register is optional */
586 mtk->ippc_regs = devm_ioremap_resource(dev, res);
587 if (IS_ERR(mtk->ippc_regs)) {
588 ret = PTR_ERR(mtk->ippc_regs);
591 mtk->has_ippc = true;
594 device_init_wakeup(dev, true);
596 xhci = hcd_to_xhci(hcd);
597 xhci->main_hcd = hcd;
598 xhci->allow_single_roothub = 1;
601 * imod_interval is the interrupt moderation value in nanoseconds.
602 * The increment interval is 8 times as much as that defined in
603 * the xHCI spec on MTK's controller.
605 xhci->imod_interval = 5000;
606 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
608 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
610 goto disable_device_wakeup;
612 if (!xhci_has_one_roothub(xhci)) {
613 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
615 if (!xhci->shared_hcd) {
617 goto dealloc_usb2_hcd;
621 usb3_hcd = xhci_get_usb3_hcd(xhci);
622 if (usb3_hcd && HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
623 !(xhci->quirks & XHCI_BROKEN_STREAMS))
624 usb3_hcd->can_do_streams = 1;
626 if (xhci->shared_hcd) {
627 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
632 if (wakeup_irq > 0) {
633 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq);
635 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
636 goto dealloc_usb3_hcd;
638 dev_info(dev, "wakeup irq %d\n", wakeup_irq);
641 device_enable_async_suspend(dev);
642 pm_runtime_mark_last_busy(dev);
643 pm_runtime_put_autosuspend(dev);
644 pm_runtime_forbid(dev);
649 usb_remove_hcd(xhci->shared_hcd);
652 usb_put_hcd(xhci->shared_hcd);
655 xhci_mtk_sch_exit(mtk);
658 disable_device_wakeup:
659 device_init_wakeup(dev, false);
665 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
668 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
671 pm_runtime_put_noidle(dev);
672 pm_runtime_disable(dev);
676 static int xhci_mtk_remove(struct platform_device *pdev)
678 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
679 struct usb_hcd *hcd = mtk->hcd;
680 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
681 struct usb_hcd *shared_hcd = xhci->shared_hcd;
682 struct device *dev = &pdev->dev;
684 pm_runtime_get_sync(dev);
685 xhci->xhc_state |= XHCI_STATE_REMOVING;
686 dev_pm_clear_wake_irq(dev);
687 device_init_wakeup(dev, false);
690 usb_remove_hcd(shared_hcd);
691 xhci->shared_hcd = NULL;
696 usb_put_hcd(shared_hcd);
699 xhci_mtk_sch_exit(mtk);
700 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
701 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
703 pm_runtime_disable(dev);
704 pm_runtime_put_noidle(dev);
705 pm_runtime_set_suspended(dev);
710 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
712 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
713 struct usb_hcd *hcd = mtk->hcd;
714 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
715 struct usb_hcd *shared_hcd = xhci->shared_hcd;
718 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
719 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
720 del_timer_sync(&hcd->rh_timer);
722 clear_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
723 del_timer_sync(&shared_hcd->rh_timer);
726 ret = xhci_mtk_host_disable(mtk);
728 goto restart_poll_rh;
730 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
731 usb_wakeup_set(mtk, true);
735 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
737 set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
738 usb_hcd_poll_rh_status(shared_hcd);
740 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
741 usb_hcd_poll_rh_status(hcd);
745 static int __maybe_unused xhci_mtk_resume(struct device *dev)
747 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
748 struct usb_hcd *hcd = mtk->hcd;
749 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
750 struct usb_hcd *shared_hcd = xhci->shared_hcd;
753 usb_wakeup_set(mtk, false);
754 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
758 ret = xhci_mtk_host_enable(mtk);
762 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
764 set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
765 usb_hcd_poll_rh_status(shared_hcd);
767 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
768 usb_hcd_poll_rh_status(hcd);
772 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
774 usb_wakeup_set(mtk, true);
778 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
780 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
781 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
787 if (device_may_wakeup(dev))
788 ret = xhci_mtk_suspend(dev);
790 /* -EBUSY: let PM automatically reschedule another autosuspend */
791 return ret ? -EBUSY : 0;
794 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
796 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
797 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
803 if (device_may_wakeup(dev))
804 ret = xhci_mtk_resume(dev);
809 static const struct dev_pm_ops xhci_mtk_pm_ops = {
810 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
811 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
812 xhci_mtk_runtime_resume, NULL)
815 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
817 static const struct of_device_id mtk_xhci_of_match[] = {
818 { .compatible = "mediatek,mt8173-xhci"},
819 { .compatible = "mediatek,mt8195-xhci"},
820 { .compatible = "mediatek,mtk-xhci"},
823 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
825 static struct platform_driver mtk_xhci_driver = {
826 .probe = xhci_mtk_probe,
827 .remove = xhci_mtk_remove,
831 .of_match_table = mtk_xhci_of_match,
835 static int __init xhci_mtk_init(void)
837 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
838 return platform_driver_register(&mtk_xhci_driver);
840 module_init(xhci_mtk_init);
842 static void __exit xhci_mtk_exit(void)
844 platform_driver_unregister(&mtk_xhci_driver);
846 module_exit(xhci_mtk_exit);
848 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
849 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
850 MODULE_LICENSE("GPL v2");