drivers/usb/dwc3/ep0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/list.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/usb/composite.h>
  24
  25 #include "core.h"
  26 #include "debug.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                 struct dwc3_ep *dep, struct dwc3_request *req);
  33
  34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  35                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  36 {
  37         struct dwc3_trb                 *trb;
  38         struct dwc3                     *dwc;
  39
  40         dwc = dep->dwc;
  41         trb = &dwc->ep0_trb[dep->trb_enqueue];
  42
  43         if (chain)
  44                 dep->trb_enqueue++;
  45
  46         trb->bpl = lower_32_bits(buf_dma);
  47         trb->bph = upper_32_bits(buf_dma);
  48         trb->size = len;
  49         trb->ctrl = type;
  50
  51         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  52                         | DWC3_TRB_CTRL_ISP_IMI);
  53
  54         if (chain)
  55                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  56         else
  57                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  58                                 | DWC3_TRB_CTRL_LST);
  59
  60         trace_dwc3_prepare_trb(dep, trb);
  61 }
  62
  63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  64 {
  65         struct dwc3_gadget_ep_cmd_params params;
  66         struct dwc3                     *dwc;
  67         int                             ret;
  68
  69         if (dep->flags & DWC3_EP_TRANSFER_STARTED)
  70                 return 0;
  71
  72         dwc = dep->dwc;
  73
  74         memset(&params, 0, sizeof(params));
  75         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  76         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  77
  78         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  79         if (ret < 0)
  80                 return ret;
  81
  82         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  83
  84         return 0;
  85 }
  86
  87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  88                 struct dwc3_request *req)
  89 {
  90         struct dwc3             *dwc = dep->dwc;
  91
  92         req->request.actual     = 0;
  93         req->request.status     = -EINPROGRESS;
  94         req->epnum              = dep->number;
  95
  96         list_add_tail(&req->list, &dep->pending_list);
  97
  98         /*
  99          * Gadget driver might not be quick enough to queue a request
 100          * before we get a Transfer Not Ready event on this endpoint.
 101          *
 102          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 103          * flag is set, it's telling us that as soon as Gadget queues the
 104          * required request, we should kick the transfer here because the
 105          * IRQ we were waiting for is long gone.
 106          */
 107         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 108                 unsigned int direction;
 109
 110                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 111
 112                 if (dwc->ep0state != EP0_DATA_PHASE) {
 113                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 114                         return 0;
 115                 }
 116
 117                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 118
 119                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 120                                 DWC3_EP0_DIR_IN);
 121
 122                 return 0;
 123         }
 124
 125         /*
 126          * In case gadget driver asked us to delay the STATUS phase,
 127          * handle it here.
 128          */
 129         if (dwc->delayed_status) {
 130                 unsigned int direction;
 131
 132                 direction = !dwc->ep0_expect_in;
 133                 dwc->delayed_status = false;
 134                 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
 135
 136                 if (dwc->ep0state == EP0_STATUS_PHASE)
 137                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 138
 139                 return 0;
 140         }
 141
 142         /*
 143          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 144          *
 145          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 146          * come before issueing Start Transfer command, but if we do, we will
 147          * miss situations where the host starts another SETUP phase instead of
 148          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 149          * Layer Compliance Suite.
 150          *
 151          * The problem surfaces due to the fact that in case of back-to-back
 152          * SETUP packets there will be no XferNotReady(DATA) generated and we
 153          * will be stuck waiting for XferNotReady(DATA) forever.
 154          *
 155          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 156          * it tells us to start Data Phase right away. It also mentions that if
 157          * we receive a SETUP phase instead of the DATA phase, core will issue
 158          * XferComplete for the DATA phase, before actually initiating it in
 159          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 160          * can only be used to print some debugging logs, as the core expects
 161          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 162          * just so it completes right away, without transferring anything and,
 163          * only then, we can go back to the SETUP phase.
 164          *
 165          * Because of this scenario, SNPS decided to change the programming
 166          * model of control transfers and support on-demand transfers only for
 167          * the STATUS phase. To fix the issue we have now, we will always wait
 168          * for gadget driver to queue the DATA phase's struct usb_request, then
 169          * start it right away.
 170          *
 171          * If we're actually in a 2-stage transfer, we will wait for
 172          * XferNotReady(STATUS).
 173          */
 174         if (dwc->three_stage_setup) {
 175                 unsigned int direction;
 176
 177                 direction = dwc->ep0_expect_in;
 178                 dwc->ep0state = EP0_DATA_PHASE;
 179
 180                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 181
 182                 dep->flags &= ~DWC3_EP0_DIR_IN;
 183         }
 184
 185         return 0;
 186 }
 187
 188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 189                 gfp_t gfp_flags)
 190 {
 191         struct dwc3_request             *req = to_dwc3_request(request);
 192         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 193         struct dwc3                     *dwc = dep->dwc;
 194
 195         unsigned long                   flags;
 196
 197         int                             ret;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         if (!dep->endpoint.desc || !dwc->pullups_connected) {
 201                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 202                                 dep->name);
 203                 ret = -ESHUTDOWN;
 204                 goto out;
 205         }
 206
 207         /* we share one TRB for ep0/1 */
 208         if (!list_empty(&dep->pending_list)) {
 209                 ret = -EBUSY;
 210                 goto out;
 211         }
 212
 213         ret = __dwc3_gadget_ep0_queue(dep, req);
 214
 215 out:
 216         spin_unlock_irqrestore(&dwc->lock, flags);
 217
 218         return ret;
 219 }
 220
 221 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 222 {
 223         struct dwc3_ep          *dep;
 224
 225         /* reinitialize physical ep1 */
 226         dep = dwc->eps[1];
 227         dep->flags = DWC3_EP_ENABLED;
 228
 229         /* stall is always issued on EP0 */
 230         dep = dwc->eps[0];
 231         __dwc3_gadget_ep_set_halt(dep, 1, false);
 232         dep->flags = DWC3_EP_ENABLED;
 233         dwc->delayed_status = false;
 234
 235         if (!list_empty(&dep->pending_list)) {
 236                 struct dwc3_request     *req;
 237
 238                 req = next_request(&dep->pending_list);
 239                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 240         }
 241
 242         dwc->ep0state = EP0_SETUP_PHASE;
 243         dwc3_ep0_out_start(dwc);
 244 }
 245
 246 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 247 {
 248         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 249         struct dwc3                     *dwc = dep->dwc;
 250
 251         dwc3_ep0_stall_and_restart(dwc);
 252
 253         return 0;
 254 }
 255
 256 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 257 {
 258         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 259         struct dwc3                     *dwc = dep->dwc;
 260         unsigned long                   flags;
 261         int                             ret;
 262
 263         spin_lock_irqsave(&dwc->lock, flags);
 264         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 265         spin_unlock_irqrestore(&dwc->lock, flags);
 266
 267         return ret;
 268 }
 269
 270 void dwc3_ep0_out_start(struct dwc3 *dwc)
 271 {
 272         struct dwc3_ep                  *dep;
 273         int                             ret;
 274
 275         complete(&dwc->ep0_in_setup);
 276
 277         dep = dwc->eps[0];
 278         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 279                         DWC3_TRBCTL_CONTROL_SETUP, false);
 280         ret = dwc3_ep0_start_trans(dep);
 281         WARN_ON(ret < 0);
 282 }
 283
 284 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 285 {
 286         struct dwc3_ep          *dep;
 287         u32                     windex = le16_to_cpu(wIndex_le);
 288         u32                     epnum;
 289
 290         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 291         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 292                 epnum |= 1;
 293
 294         dep = dwc->eps[epnum];
 295         if (dep->flags & DWC3_EP_ENABLED)
 296                 return dep;
 297
 298         return NULL;
 299 }
 300
 301 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 302 {
 303 }
 304 /*
 305  * ch 9.4.5
 306  */
 307 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 308                 struct usb_ctrlrequest *ctrl)
 309 {
 310         struct dwc3_ep          *dep;
 311         u32                     recip;
 312         u32                     value;
 313         u32                     reg;
 314         u16                     usb_status = 0;
 315         __le16                  *response_pkt;
 316
 317         /* We don't support PTM_STATUS */
 318         value = le16_to_cpu(ctrl->wValue);
 319         if (value != 0)
 320                 return -EINVAL;
 321
 322         recip = ctrl->bRequestType & USB_RECIP_MASK;
 323         switch (recip) {
 324         case USB_RECIP_DEVICE:
 325                 /*
 326                  * LTM will be set once we know how to set this in HW.
 327                  */
 328                 usb_status |= dwc->gadget->is_selfpowered;
 329
 330                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 331                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 332                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 333                         if (reg & DWC3_DCTL_INITU1ENA)
 334                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 335                         if (reg & DWC3_DCTL_INITU2ENA)
 336                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 337                 }
 338
 339                 break;
 340
 341         case USB_RECIP_INTERFACE:
 342                 /*
 343                  * Function Remote Wake Capable D0
 344                  * Function Remote Wakeup       D1
 345                  */
 346                 break;
 347
 348         case USB_RECIP_ENDPOINT:
 349                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 350                 if (!dep)
 351                         return -EINVAL;
 352
 353                 if (dep->flags & DWC3_EP_STALL)
 354                         usb_status = 1 << USB_ENDPOINT_HALT;
 355                 break;
 356         default:
 357                 return -EINVAL;
 358         }
 359
 360         response_pkt = (__le16 *) dwc->setup_buf;
 361         *response_pkt = cpu_to_le16(usb_status);
 362
 363         dep = dwc->eps[0];
 364         dwc->ep0_usb_req.dep = dep;
 365         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 366         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 367         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 368
 369         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 370 }
 371
 372 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 373                 int set)
 374 {
 375         u32 reg;
 376
 377         if (state != USB_STATE_CONFIGURED)
 378                 return -EINVAL;
 379         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 380                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 381                 return -EINVAL;
 382         if (set && dwc->dis_u1_entry_quirk)
 383                 return -EINVAL;
 384
 385         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 386         if (set)
 387                 reg |= DWC3_DCTL_INITU1ENA;
 388         else
 389                 reg &= ~DWC3_DCTL_INITU1ENA;
 390         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 391
 392         return 0;
 393 }
 394
 395 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 396                 int set)
 397 {
 398         u32 reg;
 399
 400
 401         if (state != USB_STATE_CONFIGURED)
 402                 return -EINVAL;
 403         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 404                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 405                 return -EINVAL;
 406         if (set && dwc->dis_u2_entry_quirk)
 407                 return -EINVAL;
 408
 409         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 410         if (set)
 411                 reg |= DWC3_DCTL_INITU2ENA;
 412         else
 413                 reg &= ~DWC3_DCTL_INITU2ENA;
 414         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 415
 416         return 0;
 417 }
 418
 419 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 420                 u32 wIndex, int set)
 421 {
 422         if ((wIndex & 0xff) != 0)
 423                 return -EINVAL;
 424         if (!set)
 425                 return -EINVAL;
 426
 427         switch (wIndex >> 8) {
 428         case USB_TEST_J:
 429         case USB_TEST_K:
 430         case USB_TEST_SE0_NAK:
 431         case USB_TEST_PACKET:
 432         case USB_TEST_FORCE_ENABLE:
 433                 dwc->test_mode_nr = wIndex >> 8;
 434                 dwc->test_mode = true;
 435                 break;
 436         default:
 437                 return -EINVAL;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 444                 struct usb_ctrlrequest *ctrl, int set)
 445 {
 446         enum usb_device_state   state;
 447         u32                     wValue;
 448         u32                     wIndex;
 449         int                     ret = 0;
 450
 451         wValue = le16_to_cpu(ctrl->wValue);
 452         wIndex = le16_to_cpu(ctrl->wIndex);
 453         state = dwc->gadget->state;
 454
 455         switch (wValue) {
 456         case USB_DEVICE_REMOTE_WAKEUP:
 457                 break;
 458         /*
 459          * 9.4.1 says only only for SS, in AddressState only for
 460          * default control pipe
 461          */
 462         case USB_DEVICE_U1_ENABLE:
 463                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 464                 break;
 465         case USB_DEVICE_U2_ENABLE:
 466                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 467                 break;
 468         case USB_DEVICE_LTM_ENABLE:
 469                 ret = -EINVAL;
 470                 break;
 471         case USB_DEVICE_TEST_MODE:
 472                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 473                 break;
 474         default:
 475                 ret = -EINVAL;
 476         }
 477
 478         return ret;
 479 }
 480
 481 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 482                 struct usb_ctrlrequest *ctrl, int set)
 483 {
 484         u32                     wValue;
 485         int                     ret = 0;
 486
 487         wValue = le16_to_cpu(ctrl->wValue);
 488
 489         switch (wValue) {
 490         case USB_INTRF_FUNC_SUSPEND:
 491                 /*
 492                  * REVISIT: Ideally we would enable some low power mode here,
 493                  * however it's unclear what we should be doing here.
 494                  *
 495                  * For now, we're not doing anything, just making sure we return
 496                  * 0 so USB Command Verifier tests pass without any errors.
 497                  */
 498                 break;
 499         default:
 500                 ret = -EINVAL;
 501         }
 502
 503         return ret;
 504 }
 505
 506 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 507                 struct usb_ctrlrequest *ctrl, int set)
 508 {
 509         struct dwc3_ep          *dep;
 510         u32                     wValue;
 511         int                     ret;
 512
 513         wValue = le16_to_cpu(ctrl->wValue);
 514
 515         switch (wValue) {
 516         case USB_ENDPOINT_HALT:
 517                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 518                 if (!dep)
 519                         return -EINVAL;
 520
 521                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 522                         break;
 523
 524                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 525                 if (ret)
 526                         return -EINVAL;
 527
 528                 /* ClearFeature(Halt) may need delayed status */
 529                 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
 530                         return USB_GADGET_DELAYED_STATUS;
 531
 532                 break;
 533         default:
 534                 return -EINVAL;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 541                 struct usb_ctrlrequest *ctrl, int set)
 542 {
 543         u32                     recip;
 544         int                     ret;
 545
 546         recip = ctrl->bRequestType & USB_RECIP_MASK;
 547
 548         switch (recip) {
 549         case USB_RECIP_DEVICE:
 550                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 551                 break;
 552         case USB_RECIP_INTERFACE:
 553                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 554                 break;
 555         case USB_RECIP_ENDPOINT:
 556                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 557                 break;
 558         default:
 559                 ret = -EINVAL;
 560         }
 561
 562         return ret;
 563 }
 564
 565 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 566 {
 567         enum usb_device_state state = dwc->gadget->state;
 568         u32 addr;
 569         u32 reg;
 570
 571         addr = le16_to_cpu(ctrl->wValue);
 572         if (addr > 127) {
 573                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 574                 return -EINVAL;
 575         }
 576
 577         if (state == USB_STATE_CONFIGURED) {
 578                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 579                 return -EINVAL;
 580         }
 581
 582         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 583         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 584         reg |= DWC3_DCFG_DEVADDR(addr);
 585         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 586
 587         if (addr)
 588                 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
 589         else
 590                 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
 591
 592         return 0;
 593 }
 594
 595 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 596 {
 597         int ret;
 598
 599         spin_unlock(&dwc->lock);
 600         ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
 601         spin_lock(&dwc->lock);
 602         return ret;
 603 }
 604
 605 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 606 {
 607         enum usb_device_state state = dwc->gadget->state;
 608         u32 cfg;
 609         int ret;
 610         u32 reg;
 611
 612         cfg = le16_to_cpu(ctrl->wValue);
 613
 614         switch (state) {
 615         case USB_STATE_DEFAULT:
 616                 return -EINVAL;
 617
 618         case USB_STATE_ADDRESS:
 619                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 620                 /* if the cfg matches and the cfg is non zero */
 621                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 622
 623                         /*
 624                          * only change state if set_config has already
 625                          * been processed. If gadget driver returns
 626                          * USB_GADGET_DELAYED_STATUS, we will wait
 627                          * to change the state on the next usb_ep_queue()
 628                          */
 629                         if (ret == 0)
 630                                 usb_gadget_set_state(dwc->gadget,
 631                                                 USB_STATE_CONFIGURED);
 632
 633                         /*
 634                          * Enable transition to U1/U2 state when
 635                          * nothing is pending from application.
 636                          */
 637                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 638                         if (!dwc->dis_u1_entry_quirk)
 639                                 reg |= DWC3_DCTL_ACCEPTU1ENA;
 640                         if (!dwc->dis_u2_entry_quirk)
 641                                 reg |= DWC3_DCTL_ACCEPTU2ENA;
 642                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 643                 }
 644                 break;
 645
 646         case USB_STATE_CONFIGURED:
 647                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 648                 if (!cfg && !ret)
 649                         usb_gadget_set_state(dwc->gadget,
 650                                         USB_STATE_ADDRESS);
 651                 break;
 652         default:
 653                 ret = -EINVAL;
 654         }
 655         return ret;
 656 }
 657
 658 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 659 {
 660         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 661         struct dwc3     *dwc = dep->dwc;
 662
 663         u32             param = 0;
 664         u32             reg;
 665
 666         struct timing {
 667                 u8      u1sel;
 668                 u8      u1pel;
 669                 __le16  u2sel;
 670                 __le16  u2pel;
 671         } __packed timing;
 672
 673         int             ret;
 674
 675         memcpy(&timing, req->buf, sizeof(timing));
 676
 677         dwc->u1sel = timing.u1sel;
 678         dwc->u1pel = timing.u1pel;
 679         dwc->u2sel = le16_to_cpu(timing.u2sel);
 680         dwc->u2pel = le16_to_cpu(timing.u2pel);
 681
 682         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 683         if (reg & DWC3_DCTL_INITU2ENA)
 684                 param = dwc->u2pel;
 685         if (reg & DWC3_DCTL_INITU1ENA)
 686                 param = dwc->u1pel;
 687
 688         /*
 689          * According to Synopsys Databook, if parameter is
 690          * greater than 125, a value of zero should be
 691          * programmed in the register.
 692          */
 693         if (param > 125)
 694                 param = 0;
 695
 696         /* now that we have the time, issue DGCMD Set Sel */
 697         ret = dwc3_send_gadget_generic_command(dwc,
 698                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 699         WARN_ON(ret < 0);
 700 }
 701
 702 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 703 {
 704         struct dwc3_ep  *dep;
 705         enum usb_device_state state = dwc->gadget->state;
 706         u16             wLength;
 707
 708         if (state == USB_STATE_DEFAULT)
 709                 return -EINVAL;
 710
 711         wLength = le16_to_cpu(ctrl->wLength);
 712
 713         if (wLength != 6) {
 714                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 715                                 wLength);
 716                 return -EINVAL;
 717         }
 718
 719         /*
 720          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 721          * queue a usb_request for 6 bytes.
 722          *
 723          * Remember, though, this controller can't handle non-wMaxPacketSize
 724          * aligned transfers on the OUT direction, so we queue a request for
 725          * wMaxPacketSize instead.
 726          */
 727         dep = dwc->eps[0];
 728         dwc->ep0_usb_req.dep = dep;
 729         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 730         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 731         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 732
 733         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 734 }
 735
 736 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 737 {
 738         u16             wLength;
 739         u16             wValue;
 740         u16             wIndex;
 741
 742         wValue = le16_to_cpu(ctrl->wValue);
 743         wLength = le16_to_cpu(ctrl->wLength);
 744         wIndex = le16_to_cpu(ctrl->wIndex);
 745
 746         if (wIndex || wLength)
 747                 return -EINVAL;
 748
 749         dwc->gadget->isoch_delay = wValue;
 750
 751         return 0;
 752 }
 753
 754 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 755 {
 756         int ret;
 757
 758         switch (ctrl->bRequest) {
 759         case USB_REQ_GET_STATUS:
 760                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 761                 break;
 762         case USB_REQ_CLEAR_FEATURE:
 763                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 764                 break;
 765         case USB_REQ_SET_FEATURE:
 766                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 767                 break;
 768         case USB_REQ_SET_ADDRESS:
 769                 ret = dwc3_ep0_set_address(dwc, ctrl);
 770                 break;
 771         case USB_REQ_SET_CONFIGURATION:
 772                 ret = dwc3_ep0_set_config(dwc, ctrl);
 773                 break;
 774         case USB_REQ_SET_SEL:
 775                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 776                 break;
 777         case USB_REQ_SET_ISOCH_DELAY:
 778                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 779                 break;
 780         default:
 781                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 782                 break;
 783         }
 784
 785         return ret;
 786 }
 787
 788 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 789                 const struct dwc3_event_depevt *event)
 790 {
 791         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 792         int ret = -EINVAL;
 793         u32 len;
 794
 795         if (!dwc->gadget_driver)
 796                 goto out;
 797
 798         trace_dwc3_ctrl_req(ctrl);
 799
 800         len = le16_to_cpu(ctrl->wLength);
 801         if (!len) {
 802                 dwc->three_stage_setup = false;
 803                 dwc->ep0_expect_in = false;
 804                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 805         } else {
 806                 dwc->three_stage_setup = true;
 807                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 808                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 809         }
 810
 811         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 812                 ret = dwc3_ep0_std_request(dwc, ctrl);
 813         else
 814                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 815
 816         if (ret == USB_GADGET_DELAYED_STATUS)
 817                 dwc->delayed_status = true;
 818
 819 out:
 820         if (ret < 0)
 821                 dwc3_ep0_stall_and_restart(dwc);
 822 }
 823
 824 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 825                 const struct dwc3_event_depevt *event)
 826 {
 827         struct dwc3_request     *r;
 828         struct usb_request      *ur;
 829         struct dwc3_trb         *trb;
 830         struct dwc3_ep          *ep0;
 831         u32                     transferred = 0;
 832         u32                     status;
 833         u32                     length;
 834         u8                      epnum;
 835
 836         epnum = event->endpoint_number;
 837         ep0 = dwc->eps[0];
 838
 839         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 840         trb = dwc->ep0_trb;
 841         trace_dwc3_complete_trb(ep0, trb);
 842
 843         r = next_request(&ep0->pending_list);
 844         if (!r)
 845                 return;
 846
 847         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 848         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 849                 dwc->setup_packet_pending = true;
 850                 if (r)
 851                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 852
 853                 return;
 854         }
 855
 856         ur = &r->request;
 857
 858         length = trb->size & DWC3_TRB_SIZE_MASK;
 859         transferred = ur->length - length;
 860         ur->actual += transferred;
 861
 862         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 863              ur->length && ur->zero) || dwc->ep0_bounced) {
 864                 trb++;
 865                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 866                 trace_dwc3_complete_trb(ep0, trb);
 867
 868                 if (r->direction)
 869                         dwc->eps[1]->trb_enqueue = 0;
 870                 else
 871                         dwc->eps[0]->trb_enqueue = 0;
 872
 873                 dwc->ep0_bounced = false;
 874         }
 875
 876         if ((epnum & 1) && ur->actual < ur->length)
 877                 dwc3_ep0_stall_and_restart(dwc);
 878         else
 879                 dwc3_gadget_giveback(ep0, r, 0);
 880 }
 881
 882 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 883                 const struct dwc3_event_depevt *event)
 884 {
 885         struct dwc3_request     *r;
 886         struct dwc3_ep          *dep;
 887         struct dwc3_trb         *trb;
 888         u32                     status;
 889
 890         dep = dwc->eps[0];
 891         trb = dwc->ep0_trb;
 892
 893         trace_dwc3_complete_trb(dep, trb);
 894
 895         if (!list_empty(&dep->pending_list)) {
 896                 r = next_request(&dep->pending_list);
 897
 898                 dwc3_gadget_giveback(dep, r, 0);
 899         }
 900
 901         if (dwc->test_mode) {
 902                 int ret;
 903
 904                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 905                 if (ret < 0) {
 906                         dev_err(dwc->dev, "invalid test #%d\n",
 907                                         dwc->test_mode_nr);
 908                         dwc3_ep0_stall_and_restart(dwc);
 909                         return;
 910                 }
 911         }
 912
 913         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 914         if (status == DWC3_TRBSTS_SETUP_PENDING)
 915                 dwc->setup_packet_pending = true;
 916
 917         dwc->ep0state = EP0_SETUP_PHASE;
 918         dwc3_ep0_out_start(dwc);
 919 }
 920
 921 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 922                         const struct dwc3_event_depevt *event)
 923 {
 924         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 925
 926         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 927         dep->resource_index = 0;
 928         dwc->setup_packet_pending = false;
 929
 930         switch (dwc->ep0state) {
 931         case EP0_SETUP_PHASE:
 932                 dwc3_ep0_inspect_setup(dwc, event);
 933                 break;
 934
 935         case EP0_DATA_PHASE:
 936                 dwc3_ep0_complete_data(dwc, event);
 937                 break;
 938
 939         case EP0_STATUS_PHASE:
 940                 dwc3_ep0_complete_status(dwc, event);
 941                 break;
 942         default:
 943                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 944         }
 945 }
 946
 947 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 948                 struct dwc3_ep *dep, struct dwc3_request *req)
 949 {
 950         unsigned int            trb_length = 0;
 951         int                     ret;
 952
 953         req->direction = !!dep->number;
 954
 955         if (req->request.length == 0) {
 956                 if (!req->direction)
 957                         trb_length = dep->endpoint.maxpacket;
 958
 959                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 960                                 DWC3_TRBCTL_CONTROL_DATA, false);
 961                 ret = dwc3_ep0_start_trans(dep);
 962         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 963                         && (dep->number == 0)) {
 964                 u32     maxpacket;
 965                 u32     rem;
 966
 967                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 968                                 &req->request, dep->number);
 969                 if (ret)
 970                         return;
 971
 972                 maxpacket = dep->endpoint.maxpacket;
 973                 rem = req->request.length % maxpacket;
 974                 dwc->ep0_bounced = true;
 975
 976                 /* prepare normal TRB */
 977                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
 978                                          req->request.length,
 979                                          DWC3_TRBCTL_CONTROL_DATA,
 980                                          true);
 981
 982                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
 983
 984                 /* Now prepare one extra TRB to align transfer size */
 985                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
 986                                          maxpacket - rem,
 987                                          DWC3_TRBCTL_CONTROL_DATA,
 988                                          false);
 989                 ret = dwc3_ep0_start_trans(dep);
 990         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
 991                    req->request.length && req->request.zero) {
 992
 993                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 994                                 &req->request, dep->number);
 995                 if (ret)
 996                         return;
 997
 998                 /* prepare normal TRB */
 999                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1000                                          req->request.length,
1001                                          DWC3_TRBCTL_CONTROL_DATA,
1002                                          true);
1003
1004                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1005
1006                 if (!req->direction)
1007                         trb_length = dep->endpoint.maxpacket;
1008
1009                 /* Now prepare one extra TRB to align transfer size */
1010                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1011                                          trb_length, DWC3_TRBCTL_CONTROL_DATA,
1012                                          false);
1013                 ret = dwc3_ep0_start_trans(dep);
1014         } else {
1015                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1016                                 &req->request, dep->number);
1017                 if (ret)
1018                         return;
1019
1020                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1021                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1022                                 false);
1023
1024                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1025
1026                 ret = dwc3_ep0_start_trans(dep);
1027         }
1028
1029         WARN_ON(ret < 0);
1030 }
1031
1032 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1033 {
1034         struct dwc3             *dwc = dep->dwc;
1035         u32                     type;
1036
1037         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1038                 : DWC3_TRBCTL_CONTROL_STATUS2;
1039
1040         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1041         return dwc3_ep0_start_trans(dep);
1042 }
1043
1044 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1045 {
1046         WARN_ON(dwc3_ep0_start_control_status(dep));
1047 }
1048
1049 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1050                 const struct dwc3_event_depevt *event)
1051 {
1052         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1053
1054         __dwc3_ep0_do_control_status(dwc, dep);
1055 }
1056
1057 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1058 {
1059         unsigned int direction = !dwc->ep0_expect_in;
1060
1061         if (dwc->ep0state != EP0_STATUS_PHASE)
1062                 return;
1063
1064         dwc->delayed_status = false;
1065         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1066 }
1067
1068 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1069 {
1070         struct dwc3_gadget_ep_cmd_params params;
1071         u32                     cmd;
1072         int                     ret;
1073
1074         if (!dep->resource_index)
1075                 return;
1076
1077         cmd = DWC3_DEPCMD_ENDTRANSFER;
1078         cmd |= DWC3_DEPCMD_CMDIOC;
1079         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1080         memset(&params, 0, sizeof(params));
1081         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1082         WARN_ON_ONCE(ret);
1083         dep->resource_index = 0;
1084 }
1085
1086 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1087                 const struct dwc3_event_depevt *event)
1088 {
1089         switch (event->status) {
1090         case DEPEVT_STATUS_CONTROL_DATA:
1091                 /*
1092                  * We already have a DATA transfer in the controller's cache,
1093                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1094                  * it's for the wrong direction.
1095                  *
1096                  * In that case, we must issue END_TRANSFER command to the Data
1097                  * Phase we already have started and issue SetStall on the
1098                  * control endpoint.
1099                  */
1100                 if (dwc->ep0_expect_in != event->endpoint_number) {
1101                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1102
1103                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1104                         dwc3_ep0_end_control_data(dwc, dep);
1105                         dwc3_ep0_stall_and_restart(dwc);
1106                         return;
1107                 }
1108
1109                 break;
1110
1111         case DEPEVT_STATUS_CONTROL_STATUS:
1112                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1113                         return;
1114
1115                 dwc->ep0state = EP0_STATUS_PHASE;
1116
1117                 if (dwc->delayed_status) {
1118                         struct dwc3_ep *dep = dwc->eps[0];
1119
1120                         WARN_ON_ONCE(event->endpoint_number != 1);
1121                         /*
1122                          * We should handle the delay STATUS phase here if the
1123                          * request for handling delay STATUS has been queued
1124                          * into the list.
1125                          */
1126                         if (!list_empty(&dep->pending_list)) {
1127                                 dwc->delayed_status = false;
1128                                 usb_gadget_set_state(dwc->gadget,
1129                                                      USB_STATE_CONFIGURED);
1130                                 dwc3_ep0_do_control_status(dwc, event);
1131                         }
1132
1133                         return;
1134                 }
1135
1136                 dwc3_ep0_do_control_status(dwc, event);
1137         }
1138 }
1139
1140 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1141                 const struct dwc3_event_depevt *event)
1142 {
1143         struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1144         u8              cmd;
1145
1146         switch (event->endpoint_event) {
1147         case DWC3_DEPEVT_XFERCOMPLETE:
1148                 dwc3_ep0_xfer_complete(dwc, event);
1149                 break;
1150
1151         case DWC3_DEPEVT_XFERNOTREADY:
1152                 dwc3_ep0_xfernotready(dwc, event);
1153                 break;
1154
1155         case DWC3_DEPEVT_XFERINPROGRESS:
1156         case DWC3_DEPEVT_RXTXFIFOEVT:
1157         case DWC3_DEPEVT_STREAMEVT:
1158                 break;
1159         case DWC3_DEPEVT_EPCMDCMPLT:
1160                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1161
1162                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1163                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1164                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1165                 }
1166                 break;
1167         }
1168 }