1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
9 * Inspired by st-asc.c from STMicroelectronics (c)
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/dma-direction.h>
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
19 #include <linux/iopoll.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
23 #include <linux/of_platform.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pm_wakeirq.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/spinlock.h>
31 #include <linux/sysrq.h>
32 #include <linux/tty_flip.h>
33 #include <linux/tty.h>
35 #include "serial_mctrl_gpio.h"
36 #include "stm32-usart.h"
39 /* Register offsets */
40 static struct stm32_usart_info __maybe_unused stm32f4_info = {
55 .uart_enable_bit = 13,
56 .has_7bits_data = false,
61 static struct stm32_usart_info __maybe_unused stm32f7_info = {
77 .has_7bits_data = true,
83 static struct stm32_usart_info __maybe_unused stm32h7_info = {
99 .has_7bits_data = true,
107 static void stm32_usart_stop_tx(struct uart_port *port);
108 static void stm32_usart_transmit_chars(struct uart_port *port);
109 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch);
111 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
113 return container_of(port, struct stm32_port, port);
116 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
120 val = readl_relaxed(port->membase + reg);
122 writel_relaxed(val, port->membase + reg);
125 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
129 val = readl_relaxed(port->membase + reg);
131 writel_relaxed(val, port->membase + reg);
134 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
136 struct stm32_port *stm32_port = to_stm32_port(port);
137 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
139 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
145 static void stm32_usart_rs485_rts_enable(struct uart_port *port)
147 struct stm32_port *stm32_port = to_stm32_port(port);
148 struct serial_rs485 *rs485conf = &port->rs485;
150 if (stm32_port->hw_flow_control ||
151 !(rs485conf->flags & SER_RS485_ENABLED))
154 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
155 mctrl_gpio_set(stm32_port->gpios,
156 stm32_port->port.mctrl | TIOCM_RTS);
158 mctrl_gpio_set(stm32_port->gpios,
159 stm32_port->port.mctrl & ~TIOCM_RTS);
163 static void stm32_usart_rs485_rts_disable(struct uart_port *port)
165 struct stm32_port *stm32_port = to_stm32_port(port);
166 struct serial_rs485 *rs485conf = &port->rs485;
168 if (stm32_port->hw_flow_control ||
169 !(rs485conf->flags & SER_RS485_ENABLED))
172 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
173 mctrl_gpio_set(stm32_port->gpios,
174 stm32_port->port.mctrl & ~TIOCM_RTS);
176 mctrl_gpio_set(stm32_port->gpios,
177 stm32_port->port.mctrl | TIOCM_RTS);
181 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
182 u32 delay_DDE, u32 baud)
185 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
188 *cr3 |= USART_CR3_DEM;
189 over8 = *cr1 & USART_CR1_OVER8;
191 *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
194 rs485_deat_dedt = delay_ADE * baud * 8;
196 rs485_deat_dedt = delay_ADE * baud * 16;
198 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
199 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
200 rs485_deat_dedt_max : rs485_deat_dedt;
201 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
203 *cr1 |= rs485_deat_dedt;
206 rs485_deat_dedt = delay_DDE * baud * 8;
208 rs485_deat_dedt = delay_DDE * baud * 16;
210 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
211 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
212 rs485_deat_dedt_max : rs485_deat_dedt;
213 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
215 *cr1 |= rs485_deat_dedt;
218 static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios,
219 struct serial_rs485 *rs485conf)
221 struct stm32_port *stm32_port = to_stm32_port(port);
222 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
223 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
224 u32 usartdiv, baud, cr1, cr3;
227 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
229 if (rs485conf->flags & SER_RS485_ENABLED) {
230 cr1 = readl_relaxed(port->membase + ofs->cr1);
231 cr3 = readl_relaxed(port->membase + ofs->cr3);
232 usartdiv = readl_relaxed(port->membase + ofs->brr);
233 usartdiv = usartdiv & GENMASK(15, 0);
234 over8 = cr1 & USART_CR1_OVER8;
237 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
238 << USART_BRR_04_R_SHIFT;
240 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
241 stm32_usart_config_reg_rs485(&cr1, &cr3,
242 rs485conf->delay_rts_before_send,
243 rs485conf->delay_rts_after_send,
246 if (rs485conf->flags & SER_RS485_RTS_ON_SEND)
247 cr3 &= ~USART_CR3_DEP;
249 cr3 |= USART_CR3_DEP;
251 writel_relaxed(cr3, port->membase + ofs->cr3);
252 writel_relaxed(cr1, port->membase + ofs->cr1);
254 rs485conf->flags |= SER_RS485_RX_DURING_TX;
256 stm32_usart_clr_bits(port, ofs->cr3,
257 USART_CR3_DEM | USART_CR3_DEP);
258 stm32_usart_clr_bits(port, ofs->cr1,
259 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
262 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
264 /* Adjust RTS polarity in case it's driven in software */
265 if (stm32_usart_tx_empty(port))
266 stm32_usart_rs485_rts_disable(port);
268 stm32_usart_rs485_rts_enable(port);
273 static int stm32_usart_init_rs485(struct uart_port *port,
274 struct platform_device *pdev)
276 struct serial_rs485 *rs485conf = &port->rs485;
278 rs485conf->flags = 0;
279 rs485conf->delay_rts_before_send = 0;
280 rs485conf->delay_rts_after_send = 0;
282 if (!pdev->dev.of_node)
285 return uart_get_rs485_mode(port);
288 static bool stm32_usart_rx_dma_started(struct stm32_port *stm32_port)
290 return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false;
293 static void stm32_usart_rx_dma_terminate(struct stm32_port *stm32_port)
295 dmaengine_terminate_async(stm32_port->rx_ch);
296 stm32_port->rx_dma_busy = false;
299 static int stm32_usart_dma_pause_resume(struct stm32_port *stm32_port,
300 struct dma_chan *chan,
301 enum dma_status expected_status,
302 int dmaengine_pause_or_resume(struct dma_chan *),
303 bool stm32_usart_xx_dma_started(struct stm32_port *),
304 void stm32_usart_xx_dma_terminate(struct stm32_port *))
306 struct uart_port *port = &stm32_port->port;
307 enum dma_status dma_status;
310 if (!stm32_usart_xx_dma_started(stm32_port))
313 dma_status = dmaengine_tx_status(chan, chan->cookie, NULL);
314 if (dma_status != expected_status)
317 ret = dmaengine_pause_or_resume(chan);
319 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
320 stm32_usart_xx_dma_terminate(stm32_port);
325 static int stm32_usart_rx_dma_pause(struct stm32_port *stm32_port)
327 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
328 DMA_IN_PROGRESS, dmaengine_pause,
329 stm32_usart_rx_dma_started,
330 stm32_usart_rx_dma_terminate);
333 static int stm32_usart_rx_dma_resume(struct stm32_port *stm32_port)
335 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
336 DMA_PAUSED, dmaengine_resume,
337 stm32_usart_rx_dma_started,
338 stm32_usart_rx_dma_terminate);
341 /* Return true when data is pending (in pio mode), and false when no data is pending. */
342 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr)
344 struct stm32_port *stm32_port = to_stm32_port(port);
345 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
347 *sr = readl_relaxed(port->membase + ofs->isr);
348 /* Get pending characters in RDR or FIFO */
349 if (*sr & USART_SR_RXNE) {
350 /* Get all pending characters from the RDR or the FIFO when using interrupts */
351 if (!stm32_usart_rx_dma_started(stm32_port))
354 /* Handle only RX data errors when using DMA */
355 if (*sr & USART_SR_ERR_MASK)
362 static u8 stm32_usart_get_char_pio(struct uart_port *port)
364 struct stm32_port *stm32_port = to_stm32_port(port);
365 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
368 c = readl_relaxed(port->membase + ofs->rdr);
369 /* Apply RDR data mask */
370 c &= stm32_port->rdr_mask;
375 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port)
377 struct stm32_port *stm32_port = to_stm32_port(port);
378 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
379 unsigned int size = 0;
383 while (stm32_usart_pending_rx_pio(port, &sr)) {
384 sr |= USART_SR_DUMMY_RX;
388 * Status bits has to be cleared before reading the RDR:
389 * In FIFO mode, reading the RDR will pop the next data
390 * (if any) along with its status bits into the SR.
391 * Not doing so leads to misalignement between RDR and SR,
392 * and clear status bits of the next rx data.
394 * Clear errors flags for stm32f7 and stm32h7 compatible
395 * devices. On stm32f4 compatible devices, the error bit is
396 * cleared by the sequence [read SR - read DR].
398 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
399 writel_relaxed(sr & USART_SR_ERR_MASK,
400 port->membase + ofs->icr);
402 c = stm32_usart_get_char_pio(port);
405 if (sr & USART_SR_ERR_MASK) {
406 if (sr & USART_SR_ORE) {
407 port->icount.overrun++;
408 } else if (sr & USART_SR_PE) {
409 port->icount.parity++;
410 } else if (sr & USART_SR_FE) {
411 /* Break detection if character is null */
414 if (uart_handle_break(port))
417 port->icount.frame++;
421 sr &= port->read_status_mask;
423 if (sr & USART_SR_PE) {
425 } else if (sr & USART_SR_FE) {
433 if (uart_prepare_sysrq_char(port, c))
435 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
441 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size)
443 struct stm32_port *stm32_port = to_stm32_port(port);
444 struct tty_port *ttyport = &stm32_port->port.state->port;
445 unsigned char *dma_start;
448 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res);
451 * Apply rdr_mask on buffer in order to mask parity bit.
452 * This loop is useless in cs8 mode because DMA copies only
453 * 8 bits and already ignores parity bit.
455 if (!(stm32_port->rdr_mask == (BIT(8) - 1)))
456 for (i = 0; i < dma_size; i++)
457 *(dma_start + i) &= stm32_port->rdr_mask;
459 dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size);
460 port->icount.rx += dma_count;
461 if (dma_count != dma_size)
462 port->icount.buf_overrun++;
463 stm32_port->last_res -= dma_count;
464 if (stm32_port->last_res == 0)
465 stm32_port->last_res = RX_BUF_L;
468 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port)
470 struct stm32_port *stm32_port = to_stm32_port(port);
471 unsigned int dma_size, size = 0;
473 /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */
474 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) {
475 /* Conditional first part: from last_res to end of DMA buffer */
476 dma_size = stm32_port->last_res;
477 stm32_usart_push_buffer_dma(port, dma_size);
481 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue;
482 stm32_usart_push_buffer_dma(port, dma_size);
488 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush)
490 struct stm32_port *stm32_port = to_stm32_port(port);
491 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
492 enum dma_status rx_dma_status;
494 unsigned int size = 0;
496 if (stm32_usart_rx_dma_started(stm32_port) || force_dma_flush) {
497 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
498 stm32_port->rx_ch->cookie,
499 &stm32_port->rx_dma_state);
500 if (rx_dma_status == DMA_IN_PROGRESS ||
501 rx_dma_status == DMA_PAUSED) {
502 /* Empty DMA buffer */
503 size = stm32_usart_receive_chars_dma(port);
504 sr = readl_relaxed(port->membase + ofs->isr);
505 if (sr & USART_SR_ERR_MASK) {
506 /* Disable DMA request line */
507 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
509 /* Switch to PIO mode to handle the errors */
510 size += stm32_usart_receive_chars_pio(port);
512 /* Switch back to DMA mode */
513 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
517 stm32_usart_rx_dma_terminate(stm32_port);
518 /* Fall back to interrupt mode */
519 dev_dbg(port->dev, "DMA error, fallback to irq mode\n");
520 size = stm32_usart_receive_chars_pio(port);
523 size = stm32_usart_receive_chars_pio(port);
529 static void stm32_usart_rx_dma_complete(void *arg)
531 struct uart_port *port = arg;
532 struct tty_port *tport = &port->state->port;
536 uart_port_lock_irqsave(port, &flags);
537 size = stm32_usart_receive_chars(port, false);
538 uart_unlock_and_check_sysrq_irqrestore(port, flags);
540 tty_flip_buffer_push(tport);
543 static int stm32_usart_rx_dma_start_or_resume(struct uart_port *port)
545 struct stm32_port *stm32_port = to_stm32_port(port);
546 struct dma_async_tx_descriptor *desc;
547 enum dma_status rx_dma_status;
550 if (stm32_port->throttled)
553 if (stm32_port->rx_dma_busy) {
554 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
555 stm32_port->rx_ch->cookie,
557 if (rx_dma_status == DMA_IN_PROGRESS)
560 if (rx_dma_status == DMA_PAUSED && !stm32_usart_rx_dma_resume(stm32_port))
563 dev_err(port->dev, "DMA failed : status error.\n");
564 stm32_usart_rx_dma_terminate(stm32_port);
567 stm32_port->rx_dma_busy = true;
569 stm32_port->last_res = RX_BUF_L;
570 /* Prepare a DMA cyclic transaction */
571 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
572 stm32_port->rx_dma_buf,
577 dev_err(port->dev, "rx dma prep cyclic failed\n");
578 stm32_port->rx_dma_busy = false;
582 desc->callback = stm32_usart_rx_dma_complete;
583 desc->callback_param = port;
585 /* Push current DMA transaction in the pending queue */
586 ret = dma_submit_error(dmaengine_submit(desc));
588 dmaengine_terminate_sync(stm32_port->rx_ch);
589 stm32_port->rx_dma_busy = false;
593 /* Issue pending DMA requests */
594 dma_async_issue_pending(stm32_port->rx_ch);
599 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
601 dmaengine_terminate_async(stm32_port->tx_ch);
602 stm32_port->tx_dma_busy = false;
605 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
608 * We cannot use the function "dmaengine_tx_status" to know the
609 * status of DMA. This function does not show if the "dma complete"
610 * callback of the DMA transaction has been called. So we prefer
611 * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
614 return stm32_port->tx_dma_busy;
617 static int stm32_usart_tx_dma_pause(struct stm32_port *stm32_port)
619 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
620 DMA_IN_PROGRESS, dmaengine_pause,
621 stm32_usart_tx_dma_started,
622 stm32_usart_tx_dma_terminate);
625 static int stm32_usart_tx_dma_resume(struct stm32_port *stm32_port)
627 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
628 DMA_PAUSED, dmaengine_resume,
629 stm32_usart_tx_dma_started,
630 stm32_usart_tx_dma_terminate);
633 static void stm32_usart_tx_dma_complete(void *arg)
635 struct uart_port *port = arg;
636 struct stm32_port *stm32port = to_stm32_port(port);
639 stm32_usart_tx_dma_terminate(stm32port);
641 /* Let's see if we have pending data to send */
642 uart_port_lock_irqsave(port, &flags);
643 stm32_usart_transmit_chars(port);
644 uart_port_unlock_irqrestore(port, flags);
647 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
649 struct stm32_port *stm32_port = to_stm32_port(port);
650 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
653 * Enables TX FIFO threashold irq when FIFO is enabled,
654 * or TX empty irq when FIFO is disabled
656 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
657 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
659 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
662 static void stm32_usart_tc_interrupt_enable(struct uart_port *port)
664 struct stm32_port *stm32_port = to_stm32_port(port);
665 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
667 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
670 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
672 struct stm32_port *stm32_port = to_stm32_port(port);
673 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
675 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
676 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
678 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
681 static void stm32_usart_tc_interrupt_disable(struct uart_port *port)
683 struct stm32_port *stm32_port = to_stm32_port(port);
684 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
686 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);
689 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
691 struct stm32_port *stm32_port = to_stm32_port(port);
692 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
693 struct circ_buf *xmit = &port->state->xmit;
695 while (!uart_circ_empty(xmit)) {
696 /* Check that TDR is empty before filling FIFO */
697 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
699 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
700 uart_xmit_advance(port, 1);
703 /* rely on TXE irq (mask or unmask) for sending remaining data */
704 if (uart_circ_empty(xmit))
705 stm32_usart_tx_interrupt_disable(port);
707 stm32_usart_tx_interrupt_enable(port);
710 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
712 struct stm32_port *stm32port = to_stm32_port(port);
713 struct circ_buf *xmit = &port->state->xmit;
714 struct dma_async_tx_descriptor *desc = NULL;
718 if (stm32_usart_tx_dma_started(stm32port)) {
719 ret = stm32_usart_tx_dma_resume(stm32port);
720 if (ret < 0 && ret != -EAGAIN)
725 count = uart_circ_chars_pending(xmit);
727 if (count > TX_BUF_L)
730 if (xmit->tail < xmit->head) {
731 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
733 size_t one = UART_XMIT_SIZE - xmit->tail;
740 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
742 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
745 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
746 stm32port->tx_dma_buf,
755 * Set "tx_dma_busy" flag. This flag will be released when
756 * dmaengine_terminate_async will be called. This flag helps
757 * transmit_chars_dma not to start another DMA transaction
758 * if the callback of the previous is not yet called.
760 stm32port->tx_dma_busy = true;
762 desc->callback = stm32_usart_tx_dma_complete;
763 desc->callback_param = port;
765 /* Push current DMA TX transaction in the pending queue */
766 /* DMA no yet started, safe to free resources */
767 ret = dma_submit_error(dmaengine_submit(desc));
769 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
770 stm32_usart_tx_dma_terminate(stm32port);
774 /* Issue pending DMA TX requests */
775 dma_async_issue_pending(stm32port->tx_ch);
777 uart_xmit_advance(port, count);
782 stm32_usart_transmit_chars_pio(port);
785 static void stm32_usart_transmit_chars(struct uart_port *port)
787 struct stm32_port *stm32_port = to_stm32_port(port);
788 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
789 struct circ_buf *xmit = &port->state->xmit;
793 if (!stm32_port->hw_flow_control &&
794 port->rs485.flags & SER_RS485_ENABLED &&
796 !(uart_circ_empty(xmit) || uart_tx_stopped(port)))) {
797 stm32_usart_tc_interrupt_disable(port);
798 stm32_usart_rs485_rts_enable(port);
802 /* dma terminate may have been called in case of dma pause failure */
803 stm32_usart_tx_dma_pause(stm32_port);
805 /* Check that TDR is empty before filling FIFO */
807 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
809 (isr & USART_SR_TXE),
812 dev_warn(port->dev, "1 character may be erased\n");
814 writel_relaxed(port->x_char, port->membase + ofs->tdr);
818 /* dma terminate may have been called in case of dma resume failure */
819 stm32_usart_tx_dma_resume(stm32_port);
823 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
824 stm32_usart_tx_interrupt_disable(port);
828 if (ofs->icr == UNDEF_REG)
829 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
831 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
833 if (stm32_port->tx_ch)
834 stm32_usart_transmit_chars_dma(port);
836 stm32_usart_transmit_chars_pio(port);
838 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
839 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit)) {
842 stm32_usart_tx_interrupt_disable(port);
843 if (!stm32_port->hw_flow_control &&
844 port->rs485.flags & SER_RS485_ENABLED) {
845 stm32_usart_tc_interrupt_enable(port);
850 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
852 struct uart_port *port = ptr;
853 struct tty_port *tport = &port->state->port;
854 struct stm32_port *stm32_port = to_stm32_port(port);
855 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
859 sr = readl_relaxed(port->membase + ofs->isr);
861 if (!stm32_port->hw_flow_control &&
862 port->rs485.flags & SER_RS485_ENABLED &&
863 (sr & USART_SR_TC)) {
864 stm32_usart_tc_interrupt_disable(port);
865 stm32_usart_rs485_rts_disable(port);
868 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
869 writel_relaxed(USART_ICR_RTOCF,
870 port->membase + ofs->icr);
872 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
873 /* Clear wake up flag and disable wake up interrupt */
874 writel_relaxed(USART_ICR_WUCF,
875 port->membase + ofs->icr);
876 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
877 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
878 pm_wakeup_event(tport->tty->dev, 0);
882 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request
883 * line has been masked by HW and rx data are stacking in FIFO.
885 if (!stm32_port->throttled) {
886 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) ||
887 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) {
888 uart_port_lock(port);
889 size = stm32_usart_receive_chars(port, false);
890 uart_unlock_and_check_sysrq(port);
892 tty_flip_buffer_push(tport);
896 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
897 uart_port_lock(port);
898 stm32_usart_transmit_chars(port);
899 uart_port_unlock(port);
902 /* Receiver timeout irq for DMA RX */
903 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) {
904 uart_port_lock(port);
905 size = stm32_usart_receive_chars(port, false);
906 uart_unlock_and_check_sysrq(port);
908 tty_flip_buffer_push(tport);
914 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
916 struct stm32_port *stm32_port = to_stm32_port(port);
917 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
919 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
920 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
922 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
924 mctrl_gpio_set(stm32_port->gpios, mctrl);
927 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
929 struct stm32_port *stm32_port = to_stm32_port(port);
932 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
933 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
935 return mctrl_gpio_get(stm32_port->gpios, &ret);
938 static void stm32_usart_enable_ms(struct uart_port *port)
940 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
943 static void stm32_usart_disable_ms(struct uart_port *port)
945 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
949 static void stm32_usart_stop_tx(struct uart_port *port)
951 struct stm32_port *stm32_port = to_stm32_port(port);
953 stm32_usart_tx_interrupt_disable(port);
955 /* dma terminate may have been called in case of dma pause failure */
956 stm32_usart_tx_dma_pause(stm32_port);
958 stm32_usart_rs485_rts_disable(port);
961 /* There are probably characters waiting to be transmitted. */
962 static void stm32_usart_start_tx(struct uart_port *port)
964 struct circ_buf *xmit = &port->state->xmit;
966 if (uart_circ_empty(xmit) && !port->x_char) {
967 stm32_usart_rs485_rts_disable(port);
971 stm32_usart_rs485_rts_enable(port);
973 stm32_usart_transmit_chars(port);
976 /* Flush the transmit buffer. */
977 static void stm32_usart_flush_buffer(struct uart_port *port)
979 struct stm32_port *stm32_port = to_stm32_port(port);
981 if (stm32_port->tx_ch)
982 stm32_usart_tx_dma_terminate(stm32_port);
985 /* Throttle the remote when input buffer is about to overflow. */
986 static void stm32_usart_throttle(struct uart_port *port)
988 struct stm32_port *stm32_port = to_stm32_port(port);
989 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
992 uart_port_lock_irqsave(port, &flags);
995 * Pause DMA transfer, so the RX data gets queued into the FIFO.
996 * Hardware flow control is triggered when RX FIFO is full.
998 stm32_usart_rx_dma_pause(stm32_port);
1000 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1001 if (stm32_port->cr3_irq)
1002 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1004 stm32_port->throttled = true;
1005 uart_port_unlock_irqrestore(port, flags);
1008 /* Unthrottle the remote, the input buffer can now accept data. */
1009 static void stm32_usart_unthrottle(struct uart_port *port)
1011 struct stm32_port *stm32_port = to_stm32_port(port);
1012 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1013 unsigned long flags;
1015 uart_port_lock_irqsave(port, &flags);
1016 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
1017 if (stm32_port->cr3_irq)
1018 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
1020 stm32_port->throttled = false;
1023 * Switch back to DMA mode (resume DMA).
1024 * Hardware flow control is stopped when FIFO is not full any more.
1026 if (stm32_port->rx_ch)
1027 stm32_usart_rx_dma_start_or_resume(port);
1029 uart_port_unlock_irqrestore(port, flags);
1033 static void stm32_usart_stop_rx(struct uart_port *port)
1035 struct stm32_port *stm32_port = to_stm32_port(port);
1036 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1038 /* Disable DMA request line. */
1039 stm32_usart_rx_dma_pause(stm32_port);
1041 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1042 if (stm32_port->cr3_irq)
1043 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1046 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
1048 struct stm32_port *stm32_port = to_stm32_port(port);
1049 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1050 unsigned long flags;
1052 spin_lock_irqsave(&port->lock, flags);
1055 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_SBKRQ);
1057 stm32_usart_clr_bits(port, ofs->rqr, USART_RQR_SBKRQ);
1059 spin_unlock_irqrestore(&port->lock, flags);
1062 static int stm32_usart_startup(struct uart_port *port)
1064 struct stm32_port *stm32_port = to_stm32_port(port);
1065 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1066 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1067 const char *name = to_platform_device(port->dev)->name;
1071 ret = request_irq(port->irq, stm32_usart_interrupt,
1072 IRQF_NO_SUSPEND, name, port);
1076 if (stm32_port->swap) {
1077 val = readl_relaxed(port->membase + ofs->cr2);
1078 val |= USART_CR2_SWAP;
1079 writel_relaxed(val, port->membase + ofs->cr2);
1083 if (ofs->rqr != UNDEF_REG)
1084 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
1086 if (stm32_port->rx_ch) {
1087 ret = stm32_usart_rx_dma_start_or_resume(port);
1089 free_irq(port->irq, port);
1095 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
1096 stm32_usart_set_bits(port, ofs->cr1, val);
1101 static void stm32_usart_shutdown(struct uart_port *port)
1103 struct stm32_port *stm32_port = to_stm32_port(port);
1104 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1105 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1109 if (stm32_usart_tx_dma_started(stm32_port))
1110 stm32_usart_tx_dma_terminate(stm32_port);
1112 if (stm32_port->tx_ch)
1113 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1115 /* Disable modem control interrupts */
1116 stm32_usart_disable_ms(port);
1118 val = USART_CR1_TXEIE | USART_CR1_TE;
1119 val |= stm32_port->cr1_irq | USART_CR1_RE;
1120 val |= BIT(cfg->uart_enable_bit);
1121 if (stm32_port->fifoen)
1122 val |= USART_CR1_FIFOEN;
1124 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
1125 isr, (isr & USART_SR_TC),
1128 /* Send the TC error message only when ISR_TC is not set */
1130 dev_err(port->dev, "Transmission is not complete\n");
1132 /* Disable RX DMA. */
1133 if (stm32_port->rx_ch) {
1134 stm32_usart_rx_dma_terminate(stm32_port);
1135 dmaengine_synchronize(stm32_port->rx_ch);
1138 /* flush RX & TX FIFO */
1139 if (ofs->rqr != UNDEF_REG)
1140 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1141 port->membase + ofs->rqr);
1143 stm32_usart_clr_bits(port, ofs->cr1, val);
1145 free_irq(port->irq, port);
1148 static void stm32_usart_set_termios(struct uart_port *port,
1149 struct ktermios *termios,
1150 const struct ktermios *old)
1152 struct stm32_port *stm32_port = to_stm32_port(port);
1153 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1154 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1155 struct serial_rs485 *rs485conf = &port->rs485;
1156 unsigned int baud, bits;
1157 u32 usartdiv, mantissa, fraction, oversampling;
1158 tcflag_t cflag = termios->c_cflag;
1159 u32 cr1, cr2, cr3, isr;
1160 unsigned long flags;
1163 if (!stm32_port->hw_flow_control)
1166 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
1168 uart_port_lock_irqsave(port, &flags);
1170 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
1172 (isr & USART_SR_TC),
1175 /* Send the TC error message only when ISR_TC is not set. */
1177 dev_err(port->dev, "Transmission is not complete\n");
1179 /* Stop serial port and reset value */
1180 writel_relaxed(0, port->membase + ofs->cr1);
1182 /* flush RX & TX FIFO */
1183 if (ofs->rqr != UNDEF_REG)
1184 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1185 port->membase + ofs->rqr);
1187 cr1 = USART_CR1_TE | USART_CR1_RE;
1188 if (stm32_port->fifoen)
1189 cr1 |= USART_CR1_FIFOEN;
1190 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
1192 /* Tx and RX FIFO configuration */
1193 cr3 = readl_relaxed(port->membase + ofs->cr3);
1194 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
1195 if (stm32_port->fifoen) {
1196 if (stm32_port->txftcfg >= 0)
1197 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
1198 if (stm32_port->rxftcfg >= 0)
1199 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
1203 cr2 |= USART_CR2_STOP_2B;
1205 bits = tty_get_char_size(cflag);
1206 stm32_port->rdr_mask = (BIT(bits) - 1);
1208 if (cflag & PARENB) {
1210 cr1 |= USART_CR1_PCE;
1214 * Word length configuration:
1215 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
1216 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
1217 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
1218 * M0 and M1 already cleared by cr1 initialization.
1221 cr1 |= USART_CR1_M0;
1222 } else if ((bits == 7) && cfg->has_7bits_data) {
1223 cr1 |= USART_CR1_M1;
1224 } else if (bits != 8) {
1225 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
1229 termios->c_cflag = cflag;
1231 if (cflag & PARENB) {
1233 cr1 |= USART_CR1_M0;
1237 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
1238 (stm32_port->fifoen &&
1239 stm32_port->rxftcfg >= 0))) {
1241 bits = bits + 3; /* 1 start bit + 2 stop bits */
1243 bits = bits + 2; /* 1 start bit + 1 stop bit */
1245 /* RX timeout irq to occur after last stop bit + bits */
1246 stm32_port->cr1_irq = USART_CR1_RTOIE;
1247 writel_relaxed(bits, port->membase + ofs->rtor);
1248 cr2 |= USART_CR2_RTOEN;
1250 * Enable fifo threshold irq in two cases, either when there is no DMA, or when
1251 * wake up over usart, from low power until the DMA gets re-enabled by resume.
1253 stm32_port->cr3_irq = USART_CR3_RXFTIE;
1256 cr1 |= stm32_port->cr1_irq;
1257 cr3 |= stm32_port->cr3_irq;
1260 cr1 |= USART_CR1_PS;
1262 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1263 if (cflag & CRTSCTS) {
1264 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1265 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
1268 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
1271 * The USART supports 16 or 8 times oversampling.
1272 * By default we prefer 16 times oversampling, so that the receiver
1273 * has a better tolerance to clock deviations.
1274 * 8 times oversampling is only used to achieve higher speeds.
1276 if (usartdiv < 16) {
1278 cr1 |= USART_CR1_OVER8;
1279 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
1282 cr1 &= ~USART_CR1_OVER8;
1283 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
1286 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
1287 fraction = usartdiv % oversampling;
1288 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
1290 uart_update_timeout(port, cflag, baud);
1292 port->read_status_mask = USART_SR_ORE;
1293 if (termios->c_iflag & INPCK)
1294 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
1295 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1296 port->read_status_mask |= USART_SR_FE;
1298 /* Characters to ignore */
1299 port->ignore_status_mask = 0;
1300 if (termios->c_iflag & IGNPAR)
1301 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
1302 if (termios->c_iflag & IGNBRK) {
1303 port->ignore_status_mask |= USART_SR_FE;
1305 * If we're ignoring parity and break indicators,
1306 * ignore overruns too (for real raw support).
1308 if (termios->c_iflag & IGNPAR)
1309 port->ignore_status_mask |= USART_SR_ORE;
1312 /* Ignore all characters if CREAD is not set */
1313 if ((termios->c_cflag & CREAD) == 0)
1314 port->ignore_status_mask |= USART_SR_DUMMY_RX;
1316 if (stm32_port->rx_ch) {
1318 * Setup DMA to collect only valid data and enable error irqs.
1319 * This also enables break reception when using DMA.
1321 cr1 |= USART_CR1_PEIE;
1322 cr3 |= USART_CR3_EIE;
1323 cr3 |= USART_CR3_DMAR;
1324 cr3 |= USART_CR3_DDRE;
1327 if (stm32_port->tx_ch)
1328 cr3 |= USART_CR3_DMAT;
1330 if (rs485conf->flags & SER_RS485_ENABLED) {
1331 stm32_usart_config_reg_rs485(&cr1, &cr3,
1332 rs485conf->delay_rts_before_send,
1333 rs485conf->delay_rts_after_send,
1335 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
1336 cr3 &= ~USART_CR3_DEP;
1337 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1339 cr3 |= USART_CR3_DEP;
1340 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1344 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
1345 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
1348 /* Configure wake up from low power on start bit detection */
1349 if (stm32_port->wakeup_src) {
1350 cr3 &= ~USART_CR3_WUS_MASK;
1351 cr3 |= USART_CR3_WUS_START_BIT;
1354 writel_relaxed(cr3, port->membase + ofs->cr3);
1355 writel_relaxed(cr2, port->membase + ofs->cr2);
1356 writel_relaxed(cr1, port->membase + ofs->cr1);
1358 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1359 uart_port_unlock_irqrestore(port, flags);
1361 /* Handle modem control interrupts */
1362 if (UART_ENABLE_MS(port, termios->c_cflag))
1363 stm32_usart_enable_ms(port);
1365 stm32_usart_disable_ms(port);
1368 static const char *stm32_usart_type(struct uart_port *port)
1370 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
1373 static void stm32_usart_release_port(struct uart_port *port)
1377 static int stm32_usart_request_port(struct uart_port *port)
1382 static void stm32_usart_config_port(struct uart_port *port, int flags)
1384 if (flags & UART_CONFIG_TYPE)
1385 port->type = PORT_STM32;
1389 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
1391 /* No user changeable parameters */
1395 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
1396 unsigned int oldstate)
1398 struct stm32_port *stm32port = container_of(port,
1399 struct stm32_port, port);
1400 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1401 const struct stm32_usart_config *cfg = &stm32port->info->cfg;
1402 unsigned long flags;
1405 case UART_PM_STATE_ON:
1406 pm_runtime_get_sync(port->dev);
1408 case UART_PM_STATE_OFF:
1409 uart_port_lock_irqsave(port, &flags);
1410 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1411 uart_port_unlock_irqrestore(port, flags);
1412 pm_runtime_put_sync(port->dev);
1417 #if defined(CONFIG_CONSOLE_POLL)
1419 /* Callbacks for characters polling in debug context (i.e. KGDB). */
1420 static int stm32_usart_poll_init(struct uart_port *port)
1422 struct stm32_port *stm32_port = to_stm32_port(port);
1424 return clk_prepare_enable(stm32_port->clk);
1427 static int stm32_usart_poll_get_char(struct uart_port *port)
1429 struct stm32_port *stm32_port = to_stm32_port(port);
1430 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1432 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE))
1433 return NO_POLL_CHAR;
1435 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
1438 static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch)
1440 stm32_usart_console_putchar(port, ch);
1442 #endif /* CONFIG_CONSOLE_POLL */
1444 static const struct uart_ops stm32_uart_ops = {
1445 .tx_empty = stm32_usart_tx_empty,
1446 .set_mctrl = stm32_usart_set_mctrl,
1447 .get_mctrl = stm32_usart_get_mctrl,
1448 .stop_tx = stm32_usart_stop_tx,
1449 .start_tx = stm32_usart_start_tx,
1450 .throttle = stm32_usart_throttle,
1451 .unthrottle = stm32_usart_unthrottle,
1452 .stop_rx = stm32_usart_stop_rx,
1453 .enable_ms = stm32_usart_enable_ms,
1454 .break_ctl = stm32_usart_break_ctl,
1455 .startup = stm32_usart_startup,
1456 .shutdown = stm32_usart_shutdown,
1457 .flush_buffer = stm32_usart_flush_buffer,
1458 .set_termios = stm32_usart_set_termios,
1459 .pm = stm32_usart_pm,
1460 .type = stm32_usart_type,
1461 .release_port = stm32_usart_release_port,
1462 .request_port = stm32_usart_request_port,
1463 .config_port = stm32_usart_config_port,
1464 .verify_port = stm32_usart_verify_port,
1465 #if defined(CONFIG_CONSOLE_POLL)
1466 .poll_init = stm32_usart_poll_init,
1467 .poll_get_char = stm32_usart_poll_get_char,
1468 .poll_put_char = stm32_usart_poll_put_char,
1469 #endif /* CONFIG_CONSOLE_POLL */
1473 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1474 * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case,
1475 * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE.
1476 * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1.
1478 static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 };
1480 static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p,
1485 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */
1486 if (of_property_read_u32(pdev->dev.of_node, p, &bytes))
1489 for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++)
1490 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes)
1492 if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg))
1493 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1;
1495 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p,
1496 stm32h7_usart_fifo_thresh_cfg[i]);
1498 /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */
1505 static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1507 clk_disable_unprepare(stm32port->clk);
1510 static const struct serial_rs485 stm32_rs485_supported = {
1511 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
1512 SER_RS485_RX_DURING_TX,
1513 .delay_rts_before_send = 1,
1514 .delay_rts_after_send = 1,
1517 static int stm32_usart_init_port(struct stm32_port *stm32port,
1518 struct platform_device *pdev)
1520 struct uart_port *port = &stm32port->port;
1521 struct resource *res;
1524 irq = platform_get_irq(pdev, 0);
1528 port->iotype = UPIO_MEM;
1529 port->flags = UPF_BOOT_AUTOCONF;
1530 port->ops = &stm32_uart_ops;
1531 port->dev = &pdev->dev;
1532 port->fifosize = stm32port->info->cfg.fifosize;
1533 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1535 port->rs485_config = stm32_usart_config_rs485;
1536 port->rs485_supported = stm32_rs485_supported;
1538 ret = stm32_usart_init_rs485(port, pdev);
1542 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1543 of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1545 stm32port->swap = stm32port->info->cfg.has_swap &&
1546 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
1548 stm32port->fifoen = stm32port->info->cfg.has_fifo;
1549 if (stm32port->fifoen) {
1550 stm32_usart_get_ftcfg(pdev, "rx-threshold",
1551 &stm32port->rxftcfg);
1552 stm32_usart_get_ftcfg(pdev, "tx-threshold",
1553 &stm32port->txftcfg);
1556 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1557 if (IS_ERR(port->membase))
1558 return PTR_ERR(port->membase);
1559 port->mapbase = res->start;
1561 spin_lock_init(&port->lock);
1563 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1564 if (IS_ERR(stm32port->clk))
1565 return PTR_ERR(stm32port->clk);
1567 /* Ensure that clk rate is correct by enabling the clk */
1568 ret = clk_prepare_enable(stm32port->clk);
1572 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1573 if (!stm32port->port.uartclk) {
1578 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1579 if (IS_ERR(stm32port->gpios)) {
1580 ret = PTR_ERR(stm32port->gpios);
1585 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1586 * properties should not be specified.
1588 if (stm32port->hw_flow_control) {
1589 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1590 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1591 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1600 clk_disable_unprepare(stm32port->clk);
1605 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1607 struct device_node *np = pdev->dev.of_node;
1613 id = of_alias_get_id(np, "serial");
1615 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1619 if (WARN_ON(id >= STM32_MAX_PORTS))
1622 stm32_ports[id].hw_flow_control =
1623 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1624 of_property_read_bool (np, "uart-has-rtscts");
1625 stm32_ports[id].port.line = id;
1626 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1627 stm32_ports[id].cr3_irq = 0;
1628 stm32_ports[id].last_res = RX_BUF_L;
1629 return &stm32_ports[id];
1633 static const struct of_device_id stm32_match[] = {
1634 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1635 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1636 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1640 MODULE_DEVICE_TABLE(of, stm32_match);
1643 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1644 struct platform_device *pdev)
1646 if (stm32port->rx_buf)
1647 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf,
1648 stm32port->rx_dma_buf);
1651 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1652 struct platform_device *pdev)
1654 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1655 struct uart_port *port = &stm32port->port;
1656 struct device *dev = &pdev->dev;
1657 struct dma_slave_config config;
1660 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L,
1661 &stm32port->rx_dma_buf,
1663 if (!stm32port->rx_buf)
1666 /* Configure DMA channel */
1667 memset(&config, 0, sizeof(config));
1668 config.src_addr = port->mapbase + ofs->rdr;
1669 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1671 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1673 dev_err(dev, "rx dma channel config failed\n");
1674 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1681 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1682 struct platform_device *pdev)
1684 if (stm32port->tx_buf)
1685 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf,
1686 stm32port->tx_dma_buf);
1689 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1690 struct platform_device *pdev)
1692 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1693 struct uart_port *port = &stm32port->port;
1694 struct device *dev = &pdev->dev;
1695 struct dma_slave_config config;
1698 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1699 &stm32port->tx_dma_buf,
1701 if (!stm32port->tx_buf)
1704 /* Configure DMA channel */
1705 memset(&config, 0, sizeof(config));
1706 config.dst_addr = port->mapbase + ofs->tdr;
1707 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1709 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1711 dev_err(dev, "tx dma channel config failed\n");
1712 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1719 static int stm32_usart_serial_probe(struct platform_device *pdev)
1721 struct stm32_port *stm32port;
1724 stm32port = stm32_usart_of_get_port(pdev);
1728 stm32port->info = of_device_get_match_data(&pdev->dev);
1729 if (!stm32port->info)
1732 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx");
1733 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER)
1734 return -EPROBE_DEFER;
1736 /* Fall back in interrupt mode for any non-deferral error */
1737 if (IS_ERR(stm32port->rx_ch))
1738 stm32port->rx_ch = NULL;
1740 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx");
1741 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) {
1742 ret = -EPROBE_DEFER;
1745 /* Fall back in interrupt mode for any non-deferral error */
1746 if (IS_ERR(stm32port->tx_ch))
1747 stm32port->tx_ch = NULL;
1749 ret = stm32_usart_init_port(stm32port, pdev);
1753 if (stm32port->wakeup_src) {
1754 device_set_wakeup_capable(&pdev->dev, true);
1755 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1757 goto err_deinit_port;
1760 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) {
1761 /* Fall back in interrupt mode */
1762 dma_release_channel(stm32port->rx_ch);
1763 stm32port->rx_ch = NULL;
1766 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) {
1767 /* Fall back in interrupt mode */
1768 dma_release_channel(stm32port->tx_ch);
1769 stm32port->tx_ch = NULL;
1772 if (!stm32port->rx_ch)
1773 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n");
1774 if (!stm32port->tx_ch)
1775 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n");
1777 platform_set_drvdata(pdev, &stm32port->port);
1779 pm_runtime_get_noresume(&pdev->dev);
1780 pm_runtime_set_active(&pdev->dev);
1781 pm_runtime_enable(&pdev->dev);
1783 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1787 pm_runtime_put_sync(&pdev->dev);
1792 pm_runtime_disable(&pdev->dev);
1793 pm_runtime_set_suspended(&pdev->dev);
1794 pm_runtime_put_noidle(&pdev->dev);
1796 if (stm32port->tx_ch)
1797 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1798 if (stm32port->rx_ch)
1799 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1801 if (stm32port->wakeup_src)
1802 dev_pm_clear_wake_irq(&pdev->dev);
1805 if (stm32port->wakeup_src)
1806 device_set_wakeup_capable(&pdev->dev, false);
1808 stm32_usart_deinit_port(stm32port);
1811 if (stm32port->tx_ch)
1812 dma_release_channel(stm32port->tx_ch);
1815 if (stm32port->rx_ch)
1816 dma_release_channel(stm32port->rx_ch);
1821 static void stm32_usart_serial_remove(struct platform_device *pdev)
1823 struct uart_port *port = platform_get_drvdata(pdev);
1824 struct stm32_port *stm32_port = to_stm32_port(port);
1825 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1828 pm_runtime_get_sync(&pdev->dev);
1829 uart_remove_one_port(&stm32_usart_driver, port);
1831 pm_runtime_disable(&pdev->dev);
1832 pm_runtime_set_suspended(&pdev->dev);
1833 pm_runtime_put_noidle(&pdev->dev);
1835 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);
1837 if (stm32_port->tx_ch) {
1838 stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1839 dma_release_channel(stm32_port->tx_ch);
1842 if (stm32_port->rx_ch) {
1843 stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1844 dma_release_channel(stm32_port->rx_ch);
1847 cr3 = readl_relaxed(port->membase + ofs->cr3);
1848 cr3 &= ~USART_CR3_EIE;
1849 cr3 &= ~USART_CR3_DMAR;
1850 cr3 &= ~USART_CR3_DMAT;
1851 cr3 &= ~USART_CR3_DDRE;
1852 writel_relaxed(cr3, port->membase + ofs->cr3);
1854 if (stm32_port->wakeup_src) {
1855 dev_pm_clear_wake_irq(&pdev->dev);
1856 device_init_wakeup(&pdev->dev, false);
1859 stm32_usart_deinit_port(stm32_port);
1862 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1864 struct stm32_port *stm32_port = to_stm32_port(port);
1865 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1869 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr,
1870 (isr & USART_SR_TXE), 100,
1871 STM32_USART_TIMEOUT_USEC);
1873 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret);
1876 writel_relaxed(ch, port->membase + ofs->tdr);
1879 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1880 static void stm32_usart_console_write(struct console *co, const char *s,
1883 struct uart_port *port = &stm32_ports[co->index].port;
1884 struct stm32_port *stm32_port = to_stm32_port(port);
1885 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1886 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1887 unsigned long flags;
1888 u32 old_cr1, new_cr1;
1891 if (oops_in_progress)
1892 locked = uart_port_trylock_irqsave(port, &flags);
1894 uart_port_lock_irqsave(port, &flags);
1896 /* Save and disable interrupts, enable the transmitter */
1897 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1898 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1899 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1900 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1902 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1904 /* Restore interrupt state */
1905 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1908 uart_port_unlock_irqrestore(port, flags);
1911 static int stm32_usart_console_setup(struct console *co, char *options)
1913 struct stm32_port *stm32port;
1919 if (co->index >= STM32_MAX_PORTS)
1922 stm32port = &stm32_ports[co->index];
1925 * This driver does not support early console initialization
1926 * (use ARM early printk support instead), so we only expect
1927 * this to be called during the uart port registration when the
1928 * driver gets probed and the port should be mapped at that point.
1930 if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1934 uart_parse_options(options, &baud, &parity, &bits, &flow);
1936 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1939 static struct console stm32_console = {
1940 .name = STM32_SERIAL_NAME,
1941 .device = uart_console_device,
1942 .write = stm32_usart_console_write,
1943 .setup = stm32_usart_console_setup,
1944 .flags = CON_PRINTBUFFER,
1946 .data = &stm32_usart_driver,
1949 #define STM32_SERIAL_CONSOLE (&stm32_console)
1952 #define STM32_SERIAL_CONSOLE NULL
1953 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1955 #ifdef CONFIG_SERIAL_EARLYCON
1956 static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1958 struct stm32_usart_info *info = port->private_data;
1960 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE))
1963 writel_relaxed(ch, port->membase + info->ofs.tdr);
1966 static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count)
1968 struct earlycon_device *device = console->data;
1969 struct uart_port *port = &device->port;
1971 uart_console_write(port, s, count, early_stm32_usart_console_putchar);
1974 static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options)
1976 if (!(device->port.membase || device->port.iobase))
1978 device->port.private_data = &stm32h7_info;
1979 device->con->write = early_stm32_serial_write;
1983 static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options)
1985 if (!(device->port.membase || device->port.iobase))
1987 device->port.private_data = &stm32f7_info;
1988 device->con->write = early_stm32_serial_write;
1992 static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options)
1994 if (!(device->port.membase || device->port.iobase))
1996 device->port.private_data = &stm32f4_info;
1997 device->con->write = early_stm32_serial_write;
2001 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
2002 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
2003 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
2004 #endif /* CONFIG_SERIAL_EARLYCON */
2006 static struct uart_driver stm32_usart_driver = {
2007 .driver_name = DRIVER_NAME,
2008 .dev_name = STM32_SERIAL_NAME,
2011 .nr = STM32_MAX_PORTS,
2012 .cons = STM32_SERIAL_CONSOLE,
2015 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
2018 struct stm32_port *stm32_port = to_stm32_port(port);
2019 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
2020 struct tty_port *tport = &port->state->port;
2022 unsigned int size = 0;
2023 unsigned long flags;
2025 if (!stm32_port->wakeup_src || !tty_port_initialized(tport))
2029 * Enable low-power wake-up and wake-up irq if argument is set to
2030 * "enable", disable low-power wake-up and wake-up irq otherwise
2033 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
2034 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
2035 mctrl_gpio_enable_irq_wake(stm32_port->gpios);
2038 * When DMA is used for reception, it must be disabled before
2039 * entering low-power mode and re-enabled when exiting from
2042 if (stm32_port->rx_ch) {
2043 uart_port_lock_irqsave(port, &flags);
2044 /* Poll data from DMA RX buffer if any */
2045 if (!stm32_usart_rx_dma_pause(stm32_port))
2046 size += stm32_usart_receive_chars(port, true);
2047 stm32_usart_rx_dma_terminate(stm32_port);
2048 uart_unlock_and_check_sysrq_irqrestore(port, flags);
2050 tty_flip_buffer_push(tport);
2053 /* Poll data from RX FIFO if any */
2054 stm32_usart_receive_chars(port, false);
2056 if (stm32_port->rx_ch) {
2057 ret = stm32_usart_rx_dma_start_or_resume(port);
2061 mctrl_gpio_disable_irq_wake(stm32_port->gpios);
2062 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
2063 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
2069 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
2071 struct uart_port *port = dev_get_drvdata(dev);
2074 uart_suspend_port(&stm32_usart_driver, port);
2076 if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2077 ret = stm32_usart_serial_en_wakeup(port, true);
2083 * When "no_console_suspend" is enabled, keep the pinctrl default state
2084 * and rely on bootloader stage to restore this state upon resume.
2085 * Otherwise, apply the idle or sleep states depending on wakeup
2088 if (console_suspend_enabled || !uart_console(port)) {
2089 if (device_may_wakeup(dev) || device_wakeup_path(dev))
2090 pinctrl_pm_select_idle_state(dev);
2092 pinctrl_pm_select_sleep_state(dev);
2098 static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
2100 struct uart_port *port = dev_get_drvdata(dev);
2103 pinctrl_pm_select_default_state(dev);
2105 if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2106 ret = stm32_usart_serial_en_wakeup(port, false);
2111 return uart_resume_port(&stm32_usart_driver, port);
2114 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
2116 struct uart_port *port = dev_get_drvdata(dev);
2117 struct stm32_port *stm32port = container_of(port,
2118 struct stm32_port, port);
2120 clk_disable_unprepare(stm32port->clk);
2125 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
2127 struct uart_port *port = dev_get_drvdata(dev);
2128 struct stm32_port *stm32port = container_of(port,
2129 struct stm32_port, port);
2131 return clk_prepare_enable(stm32port->clk);
2134 static const struct dev_pm_ops stm32_serial_pm_ops = {
2135 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
2136 stm32_usart_runtime_resume, NULL)
2137 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
2138 stm32_usart_serial_resume)
2141 static struct platform_driver stm32_serial_driver = {
2142 .probe = stm32_usart_serial_probe,
2143 .remove_new = stm32_usart_serial_remove,
2145 .name = DRIVER_NAME,
2146 .pm = &stm32_serial_pm_ops,
2147 .of_match_table = of_match_ptr(stm32_match),
2151 static int __init stm32_usart_init(void)
2153 static char banner[] __initdata = "STM32 USART driver initialized";
2156 pr_info("%s\n", banner);
2158 ret = uart_register_driver(&stm32_usart_driver);
2162 ret = platform_driver_register(&stm32_serial_driver);
2164 uart_unregister_driver(&stm32_usart_driver);
2169 static void __exit stm32_usart_exit(void)
2171 platform_driver_unregister(&stm32_serial_driver);
2172 uart_unregister_driver(&stm32_usart_driver);
2175 module_init(stm32_usart_init);
2176 module_exit(stm32_usart_exit);
2178 MODULE_ALIAS("platform:" DRIVER_NAME);
2179 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
2180 MODULE_LICENSE("GPL v2");