drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/math.h>
  28 #include <linux/module.h>
  29 #include <linux/ioport.h>
  30 #include <linux/io.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/init.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/console.h>
  35 #include <linux/tty.h>
  36 #include <linux/tty_flip.h>
  37 #include <linux/serial_core.h>
  38 #include <linux/serial.h>
  39 #include <linux/serial_s3c.h>
  40 #include <linux/delay.h>
  41 #include <linux/clk.h>
  42 #include <linux/cpufreq.h>
  43 #include <linux/of.h>
  44 #include <asm/irq.h>
  45
  46 /* UART name and device definitions */
  47
  48 #define S3C24XX_SERIAL_NAME     "ttySAC"
  49 #define S3C24XX_SERIAL_MAJOR    204
  50 #define S3C24XX_SERIAL_MINOR    64
  51
  52 #ifdef CONFIG_ARM64
  53 #define UART_NR                 12
  54 #else
  55 #define UART_NR                 CONFIG_SERIAL_SAMSUNG_UARTS
  56 #endif
  57
  58 #define S3C24XX_TX_PIO                  1
  59 #define S3C24XX_TX_DMA                  2
  60 #define S3C24XX_RX_PIO                  1
  61 #define S3C24XX_RX_DMA                  2
  62
  63 /* flag to ignore all characters coming in */
  64 #define RXSTAT_DUMMY_READ (0x10000000)
  65
  66 enum s3c24xx_port_type {
  67         TYPE_S3C24XX,
  68         TYPE_S3C6400,
  69         TYPE_APPLE_S5L,
  70 };
  71
  72 struct s3c24xx_uart_info {
  73         const char              *name;
  74         enum s3c24xx_port_type  type;
  75         unsigned int            port_type;
  76         unsigned int            fifosize;
  77         unsigned long           rx_fifomask;
  78         unsigned long           rx_fifoshift;
  79         unsigned long           rx_fifofull;
  80         unsigned long           tx_fifomask;
  81         unsigned long           tx_fifoshift;
  82         unsigned long           tx_fifofull;
  83         unsigned int            def_clk_sel;
  84         unsigned long           num_clks;
  85         unsigned long           clksel_mask;
  86         unsigned long           clksel_shift;
  87         unsigned long           ucon_mask;
  88
  89         /* uart port features */
  90
  91         unsigned int            has_divslot:1;
  92 };
  93
  94 struct s3c24xx_serial_drv_data {
  95         const struct s3c24xx_uart_info  info;
  96         const struct s3c2410_uartcfg    def_cfg;
  97         const unsigned int              fifosize[UART_NR];
  98 };
  99
 100 struct s3c24xx_uart_dma {
 101         unsigned int                    rx_chan_id;
 102         unsigned int                    tx_chan_id;
 103
 104         struct dma_slave_config         rx_conf;
 105         struct dma_slave_config         tx_conf;
 106
 107         struct dma_chan                 *rx_chan;
 108         struct dma_chan                 *tx_chan;
 109
 110         dma_addr_t                      rx_addr;
 111         dma_addr_t                      tx_addr;
 112
 113         dma_cookie_t                    rx_cookie;
 114         dma_cookie_t                    tx_cookie;
 115
 116         char                            *rx_buf;
 117
 118         dma_addr_t                      tx_transfer_addr;
 119
 120         size_t                          rx_size;
 121         size_t                          tx_size;
 122
 123         struct dma_async_tx_descriptor  *tx_desc;
 124         struct dma_async_tx_descriptor  *rx_desc;
 125
 126         int                             tx_bytes_requested;
 127         int                             rx_bytes_requested;
 128 };
 129
 130 struct s3c24xx_uart_port {
 131         unsigned char                   rx_claimed;
 132         unsigned char                   tx_claimed;
 133         unsigned char                   rx_enabled;
 134         unsigned char                   tx_enabled;
 135         unsigned int                    pm_level;
 136         unsigned long                   baudclk_rate;
 137         unsigned int                    min_dma_size;
 138
 139         unsigned int                    rx_irq;
 140         unsigned int                    tx_irq;
 141
 142         unsigned int                    tx_in_progress;
 143         unsigned int                    tx_mode;
 144         unsigned int                    rx_mode;
 145
 146         const struct s3c24xx_uart_info  *info;
 147         struct clk                      *clk;
 148         struct clk                      *baudclk;
 149         struct uart_port                port;
 150         const struct s3c24xx_serial_drv_data    *drv_data;
 151
 152         /* reference to platform data */
 153         const struct s3c2410_uartcfg    *cfg;
 154
 155         struct s3c24xx_uart_dma         *dma;
 156 };
 157
 158 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 159
 160 /* conversion functions */
 161
 162 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 163
 164 /* register access controls */
 165
 166 #define portaddr(port, reg) ((port)->membase + (reg))
 167 #define portaddrl(port, reg) \
 168         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 169
 170 static u32 rd_reg(const struct uart_port *port, u32 reg)
 171 {
 172         switch (port->iotype) {
 173         case UPIO_MEM:
 174                 return readb_relaxed(portaddr(port, reg));
 175         case UPIO_MEM32:
 176                 return readl_relaxed(portaddr(port, reg));
 177         default:
 178                 return 0;
 179         }
 180         return 0;
 181 }
 182
 183 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 184
 185 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
 186 {
 187         switch (port->iotype) {
 188         case UPIO_MEM:
 189                 writeb_relaxed(val, portaddr(port, reg));
 190                 break;
 191         case UPIO_MEM32:
 192                 writel_relaxed(val, portaddr(port, reg));
 193                 break;
 194         }
 195 }
 196
 197 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 198
 199 /* Byte-order aware bit setting/clearing functions. */
 200
 201 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
 202                                    unsigned int reg)
 203 {
 204         unsigned long flags;
 205         u32 val;
 206
 207         local_irq_save(flags);
 208         val = rd_regl(port, reg);
 209         val |= (1 << idx);
 210         wr_regl(port, reg, val);
 211         local_irq_restore(flags);
 212 }
 213
 214 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
 215                                      unsigned int reg)
 216 {
 217         unsigned long flags;
 218         u32 val;
 219
 220         local_irq_save(flags);
 221         val = rd_regl(port, reg);
 222         val &= ~(1 << idx);
 223         wr_regl(port, reg, val);
 224         local_irq_restore(flags);
 225 }
 226
 227 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 228 {
 229         return container_of(port, struct s3c24xx_uart_port, port);
 230 }
 231
 232 /* translate a port to the device name */
 233
 234 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
 235 {
 236         return to_platform_device(port->dev)->name;
 237 }
 238
 239 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
 240 {
 241         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 242 }
 243
 244 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 245 {
 246         struct s3c24xx_uart_port *ourport = to_ourport(port);
 247         unsigned long flags;
 248         unsigned int ucon, ufcon;
 249         int count = 10000;
 250
 251         spin_lock_irqsave(&port->lock, flags);
 252
 253         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 254                 udelay(100);
 255
 256         ufcon = rd_regl(port, S3C2410_UFCON);
 257         ufcon |= S3C2410_UFCON_RESETRX;
 258         wr_regl(port, S3C2410_UFCON, ufcon);
 259
 260         ucon = rd_regl(port, S3C2410_UCON);
 261         ucon |= S3C2410_UCON_RXIRQMODE;
 262         wr_regl(port, S3C2410_UCON, ucon);
 263
 264         ourport->rx_enabled = 1;
 265         spin_unlock_irqrestore(&port->lock, flags);
 266 }
 267
 268 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 269 {
 270         struct s3c24xx_uart_port *ourport = to_ourport(port);
 271         unsigned long flags;
 272         unsigned int ucon;
 273
 274         spin_lock_irqsave(&port->lock, flags);
 275
 276         ucon = rd_regl(port, S3C2410_UCON);
 277         ucon &= ~S3C2410_UCON_RXIRQMODE;
 278         wr_regl(port, S3C2410_UCON, ucon);
 279
 280         ourport->rx_enabled = 0;
 281         spin_unlock_irqrestore(&port->lock, flags);
 282 }
 283
 284 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 285 {
 286         struct s3c24xx_uart_port *ourport = to_ourport(port);
 287         struct s3c24xx_uart_dma *dma = ourport->dma;
 288         struct dma_tx_state state;
 289         int count;
 290
 291         if (!ourport->tx_enabled)
 292                 return;
 293
 294         switch (ourport->info->type) {
 295         case TYPE_S3C6400:
 296                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 297                 break;
 298         case TYPE_APPLE_S5L:
 299                 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 300                 break;
 301         default:
 302                 disable_irq_nosync(ourport->tx_irq);
 303                 break;
 304         }
 305
 306         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 307                 dmaengine_pause(dma->tx_chan);
 308                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 309                 dmaengine_terminate_all(dma->tx_chan);
 310                 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 311                                         dma->tx_transfer_addr, dma->tx_size,
 312                                         DMA_TO_DEVICE);
 313                 async_tx_ack(dma->tx_desc);
 314                 count = dma->tx_bytes_requested - state.residue;
 315                 uart_xmit_advance(port, count);
 316         }
 317
 318         ourport->tx_enabled = 0;
 319         ourport->tx_in_progress = 0;
 320
 321         if (port->flags & UPF_CONS_FLOW)
 322                 s3c24xx_serial_rx_enable(port);
 323
 324         ourport->tx_mode = 0;
 325 }
 326
 327 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 328
 329 static void s3c24xx_serial_tx_dma_complete(void *args)
 330 {
 331         struct s3c24xx_uart_port *ourport = args;
 332         struct uart_port *port = &ourport->port;
 333         struct circ_buf *xmit = &port->state->xmit;
 334         struct s3c24xx_uart_dma *dma = ourport->dma;
 335         struct dma_tx_state state;
 336         unsigned long flags;
 337         int count;
 338
 339         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 340         count = dma->tx_bytes_requested - state.residue;
 341         async_tx_ack(dma->tx_desc);
 342
 343         dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 344                                 dma->tx_transfer_addr, dma->tx_size,
 345                                 DMA_TO_DEVICE);
 346
 347         spin_lock_irqsave(&port->lock, flags);
 348
 349         uart_xmit_advance(port, count);
 350         ourport->tx_in_progress = 0;
 351
 352         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 353                 uart_write_wakeup(port);
 354
 355         s3c24xx_serial_start_next_tx(ourport);
 356         spin_unlock_irqrestore(&port->lock, flags);
 357 }
 358
 359 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 360 {
 361         const struct uart_port *port = &ourport->port;
 362         u32 ucon;
 363
 364         /* Mask Tx interrupt */
 365         switch (ourport->info->type) {
 366         case TYPE_S3C6400:
 367                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 368                 break;
 369         case TYPE_APPLE_S5L:
 370                 WARN_ON(1); // No DMA
 371                 break;
 372         default:
 373                 disable_irq_nosync(ourport->tx_irq);
 374                 break;
 375         }
 376
 377         /* Enable tx dma mode */
 378         ucon = rd_regl(port, S3C2410_UCON);
 379         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 380         ucon |= S3C64XX_UCON_TXBURST_1;
 381         ucon |= S3C64XX_UCON_TXMODE_DMA;
 382         wr_regl(port,  S3C2410_UCON, ucon);
 383
 384         ourport->tx_mode = S3C24XX_TX_DMA;
 385 }
 386
 387 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 388 {
 389         const struct uart_port *port = &ourport->port;
 390         u32 ucon, ufcon;
 391
 392         /* Set ufcon txtrig */
 393         ourport->tx_in_progress = S3C24XX_TX_PIO;
 394         ufcon = rd_regl(port, S3C2410_UFCON);
 395         wr_regl(port,  S3C2410_UFCON, ufcon);
 396
 397         /* Enable tx pio mode */
 398         ucon = rd_regl(port, S3C2410_UCON);
 399         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 400         ucon |= S3C64XX_UCON_TXMODE_CPU;
 401         wr_regl(port,  S3C2410_UCON, ucon);
 402
 403         /* Unmask Tx interrupt */
 404         switch (ourport->info->type) {
 405         case TYPE_S3C6400:
 406                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 407                                   S3C64XX_UINTM);
 408                 break;
 409         case TYPE_APPLE_S5L:
 410                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 411                 wr_regl(port, S3C2410_UCON, ucon);
 412                 break;
 413         default:
 414                 enable_irq(ourport->tx_irq);
 415                 break;
 416         }
 417
 418         ourport->tx_mode = S3C24XX_TX_PIO;
 419
 420         /*
 421          * The Apple version only has edge triggered TX IRQs, so we need
 422          * to kick off the process by sending some characters here.
 423          */
 424         if (ourport->info->type == TYPE_APPLE_S5L)
 425                 s3c24xx_serial_tx_chars(ourport);
 426 }
 427
 428 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 429 {
 430         if (ourport->tx_mode != S3C24XX_TX_PIO)
 431                 enable_tx_pio(ourport);
 432 }
 433
 434 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 435                                       unsigned int count)
 436 {
 437         struct uart_port *port = &ourport->port;
 438         struct circ_buf *xmit = &port->state->xmit;
 439         struct s3c24xx_uart_dma *dma = ourport->dma;
 440
 441         if (ourport->tx_mode != S3C24XX_TX_DMA)
 442                 enable_tx_dma(ourport);
 443
 444         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 445         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 446
 447         dma_sync_single_for_device(dma->tx_chan->device->dev,
 448                                    dma->tx_transfer_addr, dma->tx_size,
 449                                    DMA_TO_DEVICE);
 450
 451         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 452                                 dma->tx_transfer_addr, dma->tx_size,
 453                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 454         if (!dma->tx_desc) {
 455                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 456                 return -EIO;
 457         }
 458
 459         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 460         dma->tx_desc->callback_param = ourport;
 461         dma->tx_bytes_requested = dma->tx_size;
 462
 463         ourport->tx_in_progress = S3C24XX_TX_DMA;
 464         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 465         dma_async_issue_pending(dma->tx_chan);
 466         return 0;
 467 }
 468
 469 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 470 {
 471         struct uart_port *port = &ourport->port;
 472         struct circ_buf *xmit = &port->state->xmit;
 473         unsigned long count;
 474
 475         /* Get data size up to the end of buffer */
 476         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 477
 478         if (!count) {
 479                 s3c24xx_serial_stop_tx(port);
 480                 return;
 481         }
 482
 483         if (!ourport->dma || !ourport->dma->tx_chan ||
 484             count < ourport->min_dma_size ||
 485             xmit->tail & (dma_get_cache_alignment() - 1))
 486                 s3c24xx_serial_start_tx_pio(ourport);
 487         else
 488                 s3c24xx_serial_start_tx_dma(ourport, count);
 489 }
 490
 491 static void s3c24xx_serial_start_tx(struct uart_port *port)
 492 {
 493         struct s3c24xx_uart_port *ourport = to_ourport(port);
 494         struct circ_buf *xmit = &port->state->xmit;
 495
 496         if (!ourport->tx_enabled) {
 497                 if (port->flags & UPF_CONS_FLOW)
 498                         s3c24xx_serial_rx_disable(port);
 499
 500                 ourport->tx_enabled = 1;
 501                 if (!ourport->dma || !ourport->dma->tx_chan)
 502                         s3c24xx_serial_start_tx_pio(ourport);
 503         }
 504
 505         if (ourport->dma && ourport->dma->tx_chan) {
 506                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 507                         s3c24xx_serial_start_next_tx(ourport);
 508         }
 509 }
 510
 511 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 512                 struct tty_port *tty, int count)
 513 {
 514         struct s3c24xx_uart_dma *dma = ourport->dma;
 515         int copied;
 516
 517         if (!count)
 518                 return;
 519
 520         dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
 521                                 dma->rx_size, DMA_FROM_DEVICE);
 522
 523         ourport->port.icount.rx += count;
 524         if (!tty) {
 525                 dev_err(ourport->port.dev, "No tty port\n");
 526                 return;
 527         }
 528         copied = tty_insert_flip_string(tty,
 529                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 530         if (copied != count) {
 531                 WARN_ON(1);
 532                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 533         }
 534 }
 535
 536 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 537 {
 538         struct s3c24xx_uart_port *ourport = to_ourport(port);
 539         struct s3c24xx_uart_dma *dma = ourport->dma;
 540         struct tty_port *t = &port->state->port;
 541         struct dma_tx_state state;
 542         enum dma_status dma_status;
 543         unsigned int received;
 544
 545         if (ourport->rx_enabled) {
 546                 dev_dbg(port->dev, "stopping rx\n");
 547                 switch (ourport->info->type) {
 548                 case TYPE_S3C6400:
 549                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 550                                         S3C64XX_UINTM);
 551                         break;
 552                 case TYPE_APPLE_S5L:
 553                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 554                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 555                         break;
 556                 default:
 557                         disable_irq_nosync(ourport->rx_irq);
 558                         break;
 559                 }
 560                 ourport->rx_enabled = 0;
 561         }
 562         if (dma && dma->rx_chan) {
 563                 dmaengine_pause(dma->tx_chan);
 564                 dma_status = dmaengine_tx_status(dma->rx_chan,
 565                                 dma->rx_cookie, &state);
 566                 if (dma_status == DMA_IN_PROGRESS ||
 567                         dma_status == DMA_PAUSED) {
 568                         received = dma->rx_bytes_requested - state.residue;
 569                         dmaengine_terminate_all(dma->rx_chan);
 570                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 571                 }
 572         }
 573 }
 574
 575 static inline const struct s3c24xx_uart_info
 576         *s3c24xx_port_to_info(struct uart_port *port)
 577 {
 578         return to_ourport(port)->info;
 579 }
 580
 581 static inline const struct s3c2410_uartcfg
 582         *s3c24xx_port_to_cfg(const struct uart_port *port)
 583 {
 584         const struct s3c24xx_uart_port *ourport;
 585
 586         if (port->dev == NULL)
 587                 return NULL;
 588
 589         ourport = container_of(port, struct s3c24xx_uart_port, port);
 590         return ourport->cfg;
 591 }
 592
 593 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
 594                                      unsigned long ufstat)
 595 {
 596         const struct s3c24xx_uart_info *info = ourport->info;
 597
 598         if (ufstat & info->rx_fifofull)
 599                 return ourport->port.fifosize;
 600
 601         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 602 }
 603
 604 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 605 static void s3c24xx_serial_rx_dma_complete(void *args)
 606 {
 607         struct s3c24xx_uart_port *ourport = args;
 608         struct uart_port *port = &ourport->port;
 609
 610         struct s3c24xx_uart_dma *dma = ourport->dma;
 611         struct tty_port *t = &port->state->port;
 612         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 613
 614         struct dma_tx_state state;
 615         unsigned long flags;
 616         int received;
 617
 618         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 619         received  = dma->rx_bytes_requested - state.residue;
 620         async_tx_ack(dma->rx_desc);
 621
 622         spin_lock_irqsave(&port->lock, flags);
 623
 624         if (received)
 625                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 626
 627         if (tty) {
 628                 tty_flip_buffer_push(t);
 629                 tty_kref_put(tty);
 630         }
 631
 632         s3c64xx_start_rx_dma(ourport);
 633
 634         spin_unlock_irqrestore(&port->lock, flags);
 635 }
 636
 637 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 638 {
 639         struct s3c24xx_uart_dma *dma = ourport->dma;
 640
 641         dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
 642                                    dma->rx_size, DMA_FROM_DEVICE);
 643
 644         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 645                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 646                                 DMA_PREP_INTERRUPT);
 647         if (!dma->rx_desc) {
 648                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 649                 return;
 650         }
 651
 652         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 653         dma->rx_desc->callback_param = ourport;
 654         dma->rx_bytes_requested = dma->rx_size;
 655
 656         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 657         dma_async_issue_pending(dma->rx_chan);
 658 }
 659
 660 /* ? - where has parity gone?? */
 661 #define S3C2410_UERSTAT_PARITY (0x1000)
 662
 663 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 664 {
 665         struct uart_port *port = &ourport->port;
 666         unsigned int ucon;
 667
 668         /* set Rx mode to DMA mode */
 669         ucon = rd_regl(port, S3C2410_UCON);
 670         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 671                         S3C64XX_UCON_TIMEOUT_MASK |
 672                         S3C64XX_UCON_EMPTYINT_EN |
 673                         S3C64XX_UCON_DMASUS_EN |
 674                         S3C64XX_UCON_TIMEOUT_EN |
 675                         S3C64XX_UCON_RXMODE_MASK);
 676         ucon |= S3C64XX_UCON_RXBURST_1 |
 677                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 678                         S3C64XX_UCON_EMPTYINT_EN |
 679                         S3C64XX_UCON_TIMEOUT_EN |
 680                         S3C64XX_UCON_RXMODE_DMA;
 681         wr_regl(port, S3C2410_UCON, ucon);
 682
 683         ourport->rx_mode = S3C24XX_RX_DMA;
 684 }
 685
 686 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 687 {
 688         struct uart_port *port = &ourport->port;
 689         unsigned int ucon;
 690
 691         /* set Rx mode to DMA mode */
 692         ucon = rd_regl(port, S3C2410_UCON);
 693         ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 694         ucon |= S3C64XX_UCON_RXMODE_CPU;
 695
 696         /* Apple types use these bits for IRQ masks */
 697         if (ourport->info->type != TYPE_APPLE_S5L) {
 698                 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 699                                 S3C64XX_UCON_EMPTYINT_EN |
 700                                 S3C64XX_UCON_DMASUS_EN |
 701                                 S3C64XX_UCON_TIMEOUT_EN);
 702                 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 703                                 S3C64XX_UCON_TIMEOUT_EN;
 704         }
 705         wr_regl(port, S3C2410_UCON, ucon);
 706
 707         ourport->rx_mode = S3C24XX_RX_PIO;
 708 }
 709
 710 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 711
 712 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 713 {
 714         unsigned int utrstat, received;
 715         struct s3c24xx_uart_port *ourport = dev_id;
 716         struct uart_port *port = &ourport->port;
 717         struct s3c24xx_uart_dma *dma = ourport->dma;
 718         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 719         struct tty_port *t = &port->state->port;
 720         struct dma_tx_state state;
 721
 722         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 723         rd_regl(port, S3C2410_UFSTAT);
 724
 725         spin_lock(&port->lock);
 726
 727         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 728                 s3c64xx_start_rx_dma(ourport);
 729                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 730                         enable_rx_dma(ourport);
 731                 goto finish;
 732         }
 733
 734         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 735                 dmaengine_pause(dma->rx_chan);
 736                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 737                 dmaengine_terminate_all(dma->rx_chan);
 738                 received = dma->rx_bytes_requested - state.residue;
 739                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 740
 741                 enable_rx_pio(ourport);
 742         }
 743
 744         s3c24xx_serial_rx_drain_fifo(ourport);
 745
 746         if (tty) {
 747                 tty_flip_buffer_push(t);
 748                 tty_kref_put(tty);
 749         }
 750
 751         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 752
 753 finish:
 754         spin_unlock(&port->lock);
 755
 756         return IRQ_HANDLED;
 757 }
 758
 759 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 760 {
 761         struct uart_port *port = &ourport->port;
 762         unsigned int ufcon, ufstat, uerstat;
 763         unsigned int fifocnt = 0;
 764         int max_count = port->fifosize;
 765         u8 ch, flag;
 766
 767         while (max_count-- > 0) {
 768                 /*
 769                  * Receive all characters known to be in FIFO
 770                  * before reading FIFO level again
 771                  */
 772                 if (fifocnt == 0) {
 773                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 774                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 775                         if (fifocnt == 0)
 776                                 break;
 777                 }
 778                 fifocnt--;
 779
 780                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 781                 ch = rd_reg(port, S3C2410_URXH);
 782
 783                 if (port->flags & UPF_CONS_FLOW) {
 784                         int txe = s3c24xx_serial_txempty_nofifo(port);
 785
 786                         if (ourport->rx_enabled) {
 787                                 if (!txe) {
 788                                         ourport->rx_enabled = 0;
 789                                         continue;
 790                                 }
 791                         } else {
 792                                 if (txe) {
 793                                         ufcon = rd_regl(port, S3C2410_UFCON);
 794                                         ufcon |= S3C2410_UFCON_RESETRX;
 795                                         wr_regl(port, S3C2410_UFCON, ufcon);
 796                                         ourport->rx_enabled = 1;
 797                                         return;
 798                                 }
 799                                 continue;
 800                         }
 801                 }
 802
 803                 /* insert the character into the buffer */
 804
 805                 flag = TTY_NORMAL;
 806                 port->icount.rx++;
 807
 808                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 809                         dev_dbg(port->dev,
 810                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 811                                 ch, uerstat);
 812
 813                         /* check for break */
 814                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 815                                 dev_dbg(port->dev, "break!\n");
 816                                 port->icount.brk++;
 817                                 if (uart_handle_break(port))
 818                                         continue; /* Ignore character */
 819                         }
 820
 821                         if (uerstat & S3C2410_UERSTAT_FRAME)
 822                                 port->icount.frame++;
 823                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 824                                 port->icount.overrun++;
 825
 826                         uerstat &= port->read_status_mask;
 827
 828                         if (uerstat & S3C2410_UERSTAT_BREAK)
 829                                 flag = TTY_BREAK;
 830                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 831                                 flag = TTY_PARITY;
 832                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 833                                             S3C2410_UERSTAT_OVERRUN))
 834                                 flag = TTY_FRAME;
 835                 }
 836
 837                 if (uart_handle_sysrq_char(port, ch))
 838                         continue; /* Ignore character */
 839
 840                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 841                                  ch, flag);
 842         }
 843
 844         tty_flip_buffer_push(&port->state->port);
 845 }
 846
 847 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 848 {
 849         struct s3c24xx_uart_port *ourport = dev_id;
 850         struct uart_port *port = &ourport->port;
 851
 852         spin_lock(&port->lock);
 853         s3c24xx_serial_rx_drain_fifo(ourport);
 854         spin_unlock(&port->lock);
 855
 856         return IRQ_HANDLED;
 857 }
 858
 859 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
 860 {
 861         struct s3c24xx_uart_port *ourport = dev_id;
 862
 863         if (ourport->dma && ourport->dma->rx_chan)
 864                 return s3c24xx_serial_rx_chars_dma(dev_id);
 865         return s3c24xx_serial_rx_chars_pio(dev_id);
 866 }
 867
 868 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 869 {
 870         struct uart_port *port = &ourport->port;
 871         struct circ_buf *xmit = &port->state->xmit;
 872         int count, dma_count = 0;
 873
 874         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 875
 876         if (ourport->dma && ourport->dma->tx_chan &&
 877             count >= ourport->min_dma_size) {
 878                 int align = dma_get_cache_alignment() -
 879                         (xmit->tail & (dma_get_cache_alignment() - 1));
 880                 if (count - align >= ourport->min_dma_size) {
 881                         dma_count = count - align;
 882                         count = align;
 883                 }
 884         }
 885
 886         if (port->x_char) {
 887                 wr_reg(port, S3C2410_UTXH, port->x_char);
 888                 port->icount.tx++;
 889                 port->x_char = 0;
 890                 return;
 891         }
 892
 893         /* if there isn't anything more to transmit, or the uart is now
 894          * stopped, disable the uart and exit
 895          */
 896
 897         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 898                 s3c24xx_serial_stop_tx(port);
 899                 return;
 900         }
 901
 902         /* try and drain the buffer... */
 903
 904         if (count > port->fifosize) {
 905                 count = port->fifosize;
 906                 dma_count = 0;
 907         }
 908
 909         while (!uart_circ_empty(xmit) && count > 0) {
 910                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 911                         break;
 912
 913                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 914                 uart_xmit_advance(port, 1);
 915                 count--;
 916         }
 917
 918         if (!count && dma_count) {
 919                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 920                 return;
 921         }
 922
 923         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 924                 uart_write_wakeup(port);
 925
 926         if (uart_circ_empty(xmit))
 927                 s3c24xx_serial_stop_tx(port);
 928 }
 929
 930 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
 931 {
 932         struct s3c24xx_uart_port *ourport = id;
 933         struct uart_port *port = &ourport->port;
 934
 935         spin_lock(&port->lock);
 936
 937         s3c24xx_serial_tx_chars(ourport);
 938
 939         spin_unlock(&port->lock);
 940         return IRQ_HANDLED;
 941 }
 942
 943 /* interrupt handler for s3c64xx and later SoC's.*/
 944 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 945 {
 946         const struct s3c24xx_uart_port *ourport = id;
 947         const struct uart_port *port = &ourport->port;
 948         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 949         irqreturn_t ret = IRQ_HANDLED;
 950
 951         if (pend & S3C64XX_UINTM_RXD_MSK) {
 952                 ret = s3c24xx_serial_rx_irq(irq, id);
 953                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 954         }
 955         if (pend & S3C64XX_UINTM_TXD_MSK) {
 956                 ret = s3c24xx_serial_tx_irq(irq, id);
 957                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 958         }
 959         return ret;
 960 }
 961
 962 /* interrupt handler for Apple SoC's.*/
 963 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 964 {
 965         const struct s3c24xx_uart_port *ourport = id;
 966         const struct uart_port *port = &ourport->port;
 967         unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
 968         irqreturn_t ret = IRQ_NONE;
 969
 970         if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
 971                 wr_regl(port, S3C2410_UTRSTAT,
 972                         APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
 973                 ret = s3c24xx_serial_rx_irq(irq, id);
 974         }
 975         if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 976                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 977                 ret = s3c24xx_serial_tx_irq(irq, id);
 978         }
 979
 980         return ret;
 981 }
 982
 983 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 984 {
 985         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 986         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 987         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 988
 989         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 990                 if ((ufstat & info->tx_fifomask) != 0 ||
 991                     (ufstat & info->tx_fifofull))
 992                         return 0;
 993
 994                 return 1;
 995         }
 996
 997         return s3c24xx_serial_txempty_nofifo(port);
 998 }
 999
1000 /* no modem control lines */
1001 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1002 {
1003         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1004
1005         if (umstat & S3C2410_UMSTAT_CTS)
1006                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1007         else
1008                 return TIOCM_CAR | TIOCM_DSR;
1009 }
1010
1011 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1012 {
1013         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1014         unsigned int ucon = rd_regl(port, S3C2410_UCON);
1015
1016         if (mctrl & TIOCM_RTS)
1017                 umcon |= S3C2410_UMCOM_RTS_LOW;
1018         else
1019                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1020
1021         wr_regl(port, S3C2410_UMCON, umcon);
1022
1023         if (mctrl & TIOCM_LOOP)
1024                 ucon |= S3C2410_UCON_LOOPBACK;
1025         else
1026                 ucon &= ~S3C2410_UCON_LOOPBACK;
1027
1028         wr_regl(port, S3C2410_UCON, ucon);
1029 }
1030
1031 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1032 {
1033         unsigned long flags;
1034         unsigned int ucon;
1035
1036         spin_lock_irqsave(&port->lock, flags);
1037
1038         ucon = rd_regl(port, S3C2410_UCON);
1039
1040         if (break_state)
1041                 ucon |= S3C2410_UCON_SBREAK;
1042         else
1043                 ucon &= ~S3C2410_UCON_SBREAK;
1044
1045         wr_regl(port, S3C2410_UCON, ucon);
1046
1047         spin_unlock_irqrestore(&port->lock, flags);
1048 }
1049
1050 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1051 {
1052         struct s3c24xx_uart_dma *dma = p->dma;
1053         struct dma_slave_caps dma_caps;
1054         const char *reason = NULL;
1055         int ret;
1056
1057         /* Default slave configuration parameters */
1058         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
1059         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1060         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
1061         dma->rx_conf.src_maxburst       = 1;
1062
1063         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
1064         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1065         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
1066         dma->tx_conf.dst_maxburst       = 1;
1067
1068         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1069
1070         if (IS_ERR(dma->rx_chan)) {
1071                 reason = "DMA RX channel request failed";
1072                 ret = PTR_ERR(dma->rx_chan);
1073                 goto err_warn;
1074         }
1075
1076         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1077         if (ret < 0 ||
1078             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1079                 reason = "insufficient DMA RX engine capabilities";
1080                 ret = -EOPNOTSUPP;
1081                 goto err_release_rx;
1082         }
1083
1084         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1085
1086         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1087         if (IS_ERR(dma->tx_chan)) {
1088                 reason = "DMA TX channel request failed";
1089                 ret = PTR_ERR(dma->tx_chan);
1090                 goto err_release_rx;
1091         }
1092
1093         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1094         if (ret < 0 ||
1095             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1096                 reason = "insufficient DMA TX engine capabilities";
1097                 ret = -EOPNOTSUPP;
1098                 goto err_release_tx;
1099         }
1100
1101         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1102
1103         /* RX buffer */
1104         dma->rx_size = PAGE_SIZE;
1105
1106         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1107         if (!dma->rx_buf) {
1108                 ret = -ENOMEM;
1109                 goto err_release_tx;
1110         }
1111
1112         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1113                                       dma->rx_size, DMA_FROM_DEVICE);
1114         if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1115                 reason = "DMA mapping error for RX buffer";
1116                 ret = -EIO;
1117                 goto err_free_rx;
1118         }
1119
1120         /* TX buffer */
1121         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1122                                       p->port.state->xmit.buf, UART_XMIT_SIZE,
1123                                       DMA_TO_DEVICE);
1124         if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1125                 reason = "DMA mapping error for TX buffer";
1126                 ret = -EIO;
1127                 goto err_unmap_rx;
1128         }
1129
1130         return 0;
1131
1132 err_unmap_rx:
1133         dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1134                          dma->rx_size, DMA_FROM_DEVICE);
1135 err_free_rx:
1136         kfree(dma->rx_buf);
1137 err_release_tx:
1138         dma_release_channel(dma->tx_chan);
1139 err_release_rx:
1140         dma_release_channel(dma->rx_chan);
1141 err_warn:
1142         if (reason)
1143                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1144         return ret;
1145 }
1146
1147 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1148 {
1149         struct s3c24xx_uart_dma *dma = p->dma;
1150
1151         if (dma->rx_chan) {
1152                 dmaengine_terminate_all(dma->rx_chan);
1153                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1154                                  dma->rx_size, DMA_FROM_DEVICE);
1155                 kfree(dma->rx_buf);
1156                 dma_release_channel(dma->rx_chan);
1157                 dma->rx_chan = NULL;
1158         }
1159
1160         if (dma->tx_chan) {
1161                 dmaengine_terminate_all(dma->tx_chan);
1162                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1163                                  UART_XMIT_SIZE, DMA_TO_DEVICE);
1164                 dma_release_channel(dma->tx_chan);
1165                 dma->tx_chan = NULL;
1166         }
1167 }
1168
1169 static void s3c24xx_serial_shutdown(struct uart_port *port)
1170 {
1171         struct s3c24xx_uart_port *ourport = to_ourport(port);
1172
1173         if (ourport->tx_claimed) {
1174                 free_irq(ourport->tx_irq, ourport);
1175                 ourport->tx_enabled = 0;
1176                 ourport->tx_claimed = 0;
1177                 ourport->tx_mode = 0;
1178         }
1179
1180         if (ourport->rx_claimed) {
1181                 free_irq(ourport->rx_irq, ourport);
1182                 ourport->rx_claimed = 0;
1183                 ourport->rx_enabled = 0;
1184         }
1185
1186         if (ourport->dma)
1187                 s3c24xx_serial_release_dma(ourport);
1188
1189         ourport->tx_in_progress = 0;
1190 }
1191
1192 static void s3c64xx_serial_shutdown(struct uart_port *port)
1193 {
1194         struct s3c24xx_uart_port *ourport = to_ourport(port);
1195
1196         ourport->tx_enabled = 0;
1197         ourport->tx_mode = 0;
1198         ourport->rx_enabled = 0;
1199
1200         free_irq(port->irq, ourport);
1201
1202         wr_regl(port, S3C64XX_UINTP, 0xf);
1203         wr_regl(port, S3C64XX_UINTM, 0xf);
1204
1205         if (ourport->dma)
1206                 s3c24xx_serial_release_dma(ourport);
1207
1208         ourport->tx_in_progress = 0;
1209 }
1210
1211 static void apple_s5l_serial_shutdown(struct uart_port *port)
1212 {
1213         struct s3c24xx_uart_port *ourport = to_ourport(port);
1214
1215         unsigned int ucon;
1216
1217         ucon = rd_regl(port, S3C2410_UCON);
1218         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1219                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1220                   APPLE_S5L_UCON_RXTO_ENA_MSK);
1221         wr_regl(port, S3C2410_UCON, ucon);
1222
1223         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1224
1225         free_irq(port->irq, ourport);
1226
1227         ourport->tx_enabled = 0;
1228         ourport->tx_mode = 0;
1229         ourport->rx_enabled = 0;
1230
1231         if (ourport->dma)
1232                 s3c24xx_serial_release_dma(ourport);
1233
1234         ourport->tx_in_progress = 0;
1235 }
1236
1237 static int s3c24xx_serial_startup(struct uart_port *port)
1238 {
1239         struct s3c24xx_uart_port *ourport = to_ourport(port);
1240         int ret;
1241
1242         ourport->rx_enabled = 1;
1243
1244         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1245                           s3c24xx_serial_portname(port), ourport);
1246
1247         if (ret != 0) {
1248                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1249                 return ret;
1250         }
1251
1252         ourport->rx_claimed = 1;
1253
1254         dev_dbg(port->dev, "requesting tx irq...\n");
1255
1256         ourport->tx_enabled = 1;
1257
1258         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1259                           s3c24xx_serial_portname(port), ourport);
1260
1261         if (ret) {
1262                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1263                 goto err;
1264         }
1265
1266         ourport->tx_claimed = 1;
1267
1268         /* the port reset code should have done the correct
1269          * register setup for the port controls
1270          */
1271
1272         return ret;
1273
1274 err:
1275         s3c24xx_serial_shutdown(port);
1276         return ret;
1277 }
1278
1279 static int s3c64xx_serial_startup(struct uart_port *port)
1280 {
1281         struct s3c24xx_uart_port *ourport = to_ourport(port);
1282         unsigned long flags;
1283         unsigned int ufcon;
1284         int ret;
1285
1286         wr_regl(port, S3C64XX_UINTM, 0xf);
1287         if (ourport->dma) {
1288                 ret = s3c24xx_serial_request_dma(ourport);
1289                 if (ret < 0) {
1290                         devm_kfree(port->dev, ourport->dma);
1291                         ourport->dma = NULL;
1292                 }
1293         }
1294
1295         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1296                           s3c24xx_serial_portname(port), ourport);
1297         if (ret) {
1298                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1299                 return ret;
1300         }
1301
1302         /* For compatibility with s3c24xx Soc's */
1303         ourport->rx_enabled = 1;
1304         ourport->tx_enabled = 0;
1305
1306         spin_lock_irqsave(&port->lock, flags);
1307
1308         ufcon = rd_regl(port, S3C2410_UFCON);
1309         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1310         if (!uart_console(port))
1311                 ufcon |= S3C2410_UFCON_RESETTX;
1312         wr_regl(port, S3C2410_UFCON, ufcon);
1313
1314         enable_rx_pio(ourport);
1315
1316         spin_unlock_irqrestore(&port->lock, flags);
1317
1318         /* Enable Rx Interrupt */
1319         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1320
1321         return ret;
1322 }
1323
1324 static int apple_s5l_serial_startup(struct uart_port *port)
1325 {
1326         struct s3c24xx_uart_port *ourport = to_ourport(port);
1327         unsigned long flags;
1328         unsigned int ufcon;
1329         int ret;
1330
1331         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1332
1333         ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1334                           s3c24xx_serial_portname(port), ourport);
1335         if (ret) {
1336                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1337                 return ret;
1338         }
1339
1340         /* For compatibility with s3c24xx Soc's */
1341         ourport->rx_enabled = 1;
1342         ourport->tx_enabled = 0;
1343
1344         spin_lock_irqsave(&port->lock, flags);
1345
1346         ufcon = rd_regl(port, S3C2410_UFCON);
1347         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1348         if (!uart_console(port))
1349                 ufcon |= S3C2410_UFCON_RESETTX;
1350         wr_regl(port, S3C2410_UFCON, ufcon);
1351
1352         enable_rx_pio(ourport);
1353
1354         spin_unlock_irqrestore(&port->lock, flags);
1355
1356         /* Enable Rx Interrupt */
1357         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1358         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1359
1360         return ret;
1361 }
1362
1363 /* power power management control */
1364
1365 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1366                               unsigned int old)
1367 {
1368         struct s3c24xx_uart_port *ourport = to_ourport(port);
1369         int timeout = 10000;
1370
1371         ourport->pm_level = level;
1372
1373         switch (level) {
1374         case 3:
1375                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1376                         udelay(100);
1377
1378                 if (!IS_ERR(ourport->baudclk))
1379                         clk_disable_unprepare(ourport->baudclk);
1380
1381                 clk_disable_unprepare(ourport->clk);
1382                 break;
1383
1384         case 0:
1385                 clk_prepare_enable(ourport->clk);
1386
1387                 if (!IS_ERR(ourport->baudclk))
1388                         clk_prepare_enable(ourport->baudclk);
1389                 break;
1390         default:
1391                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1392         }
1393 }
1394
1395 /* baud rate calculation
1396  *
1397  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1398  * of different sources, including the peripheral clock ("pclk") and an
1399  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1400  * with a programmable extra divisor.
1401  *
1402  * The following code goes through the clock sources, and calculates the
1403  * baud clocks (and the resultant actual baud rates) and then tries to
1404  * pick the closest one and select that.
1405  *
1406  */
1407
1408 #define MAX_CLK_NAME_LENGTH 15
1409
1410 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1411 {
1412         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1413         unsigned int ucon;
1414
1415         if (info->num_clks == 1)
1416                 return 0;
1417
1418         ucon = rd_regl(port, S3C2410_UCON);
1419         ucon &= info->clksel_mask;
1420         return ucon >> info->clksel_shift;
1421 }
1422
1423 static void s3c24xx_serial_setsource(struct uart_port *port,
1424                         unsigned int clk_sel)
1425 {
1426         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1427         unsigned int ucon;
1428
1429         if (info->num_clks == 1)
1430                 return;
1431
1432         ucon = rd_regl(port, S3C2410_UCON);
1433         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1434                 return;
1435
1436         ucon &= ~info->clksel_mask;
1437         ucon |= clk_sel << info->clksel_shift;
1438         wr_regl(port, S3C2410_UCON, ucon);
1439 }
1440
1441 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1442                         unsigned int req_baud, struct clk **best_clk,
1443                         unsigned int *clk_num)
1444 {
1445         const struct s3c24xx_uart_info *info = ourport->info;
1446         struct clk *clk;
1447         unsigned long rate;
1448         unsigned int cnt, baud, quot, best_quot = 0;
1449         char clkname[MAX_CLK_NAME_LENGTH];
1450         int calc_deviation, deviation = (1 << 30) - 1;
1451
1452         for (cnt = 0; cnt < info->num_clks; cnt++) {
1453                 /* Keep selected clock if provided */
1454                 if (ourport->cfg->clk_sel &&
1455                         !(ourport->cfg->clk_sel & (1 << cnt)))
1456                         continue;
1457
1458                 sprintf(clkname, "clk_uart_baud%d", cnt);
1459                 clk = clk_get(ourport->port.dev, clkname);
1460                 if (IS_ERR(clk))
1461                         continue;
1462
1463                 rate = clk_get_rate(clk);
1464                 if (!rate) {
1465                         dev_err(ourport->port.dev,
1466                                 "Failed to get clock rate for %s.\n", clkname);
1467                         clk_put(clk);
1468                         continue;
1469                 }
1470
1471                 if (ourport->info->has_divslot) {
1472                         unsigned long div = rate / req_baud;
1473
1474                         /* The UDIVSLOT register on the newer UARTs allows us to
1475                          * get a divisor adjustment of 1/16th on the baud clock.
1476                          *
1477                          * We don't keep the UDIVSLOT value (the 16ths we
1478                          * calculated by not multiplying the baud by 16) as it
1479                          * is easy enough to recalculate.
1480                          */
1481
1482                         quot = div / 16;
1483                         baud = rate / div;
1484                 } else {
1485                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1486                         baud = rate / (quot * 16);
1487                 }
1488                 quot--;
1489
1490                 calc_deviation = abs(req_baud - baud);
1491
1492                 if (calc_deviation < deviation) {
1493                         /*
1494                          * If we find a better clk, release the previous one, if
1495                          * any.
1496                          */
1497                         if (!IS_ERR(*best_clk))
1498                                 clk_put(*best_clk);
1499                         *best_clk = clk;
1500                         best_quot = quot;
1501                         *clk_num = cnt;
1502                         deviation = calc_deviation;
1503                 } else {
1504                         clk_put(clk);
1505                 }
1506         }
1507
1508         return best_quot;
1509 }
1510
1511 /* udivslot_table[]
1512  *
1513  * This table takes the fractional value of the baud divisor and gives
1514  * the recommended setting for the UDIVSLOT register.
1515  */
1516 static const u16 udivslot_table[16] = {
1517         [0] = 0x0000,
1518         [1] = 0x0080,
1519         [2] = 0x0808,
1520         [3] = 0x0888,
1521         [4] = 0x2222,
1522         [5] = 0x4924,
1523         [6] = 0x4A52,
1524         [7] = 0x54AA,
1525         [8] = 0x5555,
1526         [9] = 0xD555,
1527         [10] = 0xD5D5,
1528         [11] = 0xDDD5,
1529         [12] = 0xDDDD,
1530         [13] = 0xDFDD,
1531         [14] = 0xDFDF,
1532         [15] = 0xFFDF,
1533 };
1534
1535 static void s3c24xx_serial_set_termios(struct uart_port *port,
1536                                        struct ktermios *termios,
1537                                        const struct ktermios *old)
1538 {
1539         const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1540         struct s3c24xx_uart_port *ourport = to_ourport(port);
1541         struct clk *clk = ERR_PTR(-EINVAL);
1542         unsigned long flags;
1543         unsigned int baud, quot, clk_sel = 0;
1544         unsigned int ulcon;
1545         unsigned int umcon;
1546         unsigned int udivslot = 0;
1547
1548         /*
1549          * We don't support modem control lines.
1550          */
1551         termios->c_cflag &= ~(HUPCL | CMSPAR);
1552         termios->c_cflag |= CLOCAL;
1553
1554         /*
1555          * Ask the core to calculate the divisor for us.
1556          */
1557
1558         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1559         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1560         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1561                 quot = port->custom_divisor;
1562         if (IS_ERR(clk))
1563                 return;
1564
1565         /* check to see if we need  to change clock source */
1566
1567         if (ourport->baudclk != clk) {
1568                 clk_prepare_enable(clk);
1569
1570                 s3c24xx_serial_setsource(port, clk_sel);
1571
1572                 if (!IS_ERR(ourport->baudclk)) {
1573                         clk_disable_unprepare(ourport->baudclk);
1574                         ourport->baudclk = ERR_PTR(-EINVAL);
1575                 }
1576
1577                 ourport->baudclk = clk;
1578                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1579         }
1580
1581         if (ourport->info->has_divslot) {
1582                 unsigned int div = ourport->baudclk_rate / baud;
1583
1584                 if (cfg->has_fracval) {
1585                         udivslot = (div & 15);
1586                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1587                 } else {
1588                         udivslot = udivslot_table[div & 15];
1589                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1590                                 udivslot, div & 15);
1591                 }
1592         }
1593
1594         switch (termios->c_cflag & CSIZE) {
1595         case CS5:
1596                 dev_dbg(port->dev, "config: 5bits/char\n");
1597                 ulcon = S3C2410_LCON_CS5;
1598                 break;
1599         case CS6:
1600                 dev_dbg(port->dev, "config: 6bits/char\n");
1601                 ulcon = S3C2410_LCON_CS6;
1602                 break;
1603         case CS7:
1604                 dev_dbg(port->dev, "config: 7bits/char\n");
1605                 ulcon = S3C2410_LCON_CS7;
1606                 break;
1607         case CS8:
1608         default:
1609                 dev_dbg(port->dev, "config: 8bits/char\n");
1610                 ulcon = S3C2410_LCON_CS8;
1611                 break;
1612         }
1613
1614         /* preserve original lcon IR settings */
1615         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1616
1617         if (termios->c_cflag & CSTOPB)
1618                 ulcon |= S3C2410_LCON_STOPB;
1619
1620         if (termios->c_cflag & PARENB) {
1621                 if (termios->c_cflag & PARODD)
1622                         ulcon |= S3C2410_LCON_PODD;
1623                 else
1624                         ulcon |= S3C2410_LCON_PEVEN;
1625         } else {
1626                 ulcon |= S3C2410_LCON_PNONE;
1627         }
1628
1629         spin_lock_irqsave(&port->lock, flags);
1630
1631         dev_dbg(port->dev,
1632                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1633                 ulcon, quot, udivslot);
1634
1635         wr_regl(port, S3C2410_ULCON, ulcon);
1636         wr_regl(port, S3C2410_UBRDIV, quot);
1637
1638         port->status &= ~UPSTAT_AUTOCTS;
1639
1640         umcon = rd_regl(port, S3C2410_UMCON);
1641         if (termios->c_cflag & CRTSCTS) {
1642                 umcon |= S3C2410_UMCOM_AFC;
1643                 /* Disable RTS when RX FIFO contains 63 bytes */
1644                 umcon &= ~S3C2412_UMCON_AFC_8;
1645                 port->status = UPSTAT_AUTOCTS;
1646         } else {
1647                 umcon &= ~S3C2410_UMCOM_AFC;
1648         }
1649         wr_regl(port, S3C2410_UMCON, umcon);
1650
1651         if (ourport->info->has_divslot)
1652                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1653
1654         dev_dbg(port->dev,
1655                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1656                 rd_regl(port, S3C2410_ULCON),
1657                 rd_regl(port, S3C2410_UCON),
1658                 rd_regl(port, S3C2410_UFCON));
1659
1660         /*
1661          * Update the per-port timeout.
1662          */
1663         uart_update_timeout(port, termios->c_cflag, baud);
1664
1665         /*
1666          * Which character status flags are we interested in?
1667          */
1668         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1669         if (termios->c_iflag & INPCK)
1670                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1671                         S3C2410_UERSTAT_PARITY;
1672         /*
1673          * Which character status flags should we ignore?
1674          */
1675         port->ignore_status_mask = 0;
1676         if (termios->c_iflag & IGNPAR)
1677                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1678         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1679                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1680
1681         /*
1682          * Ignore all characters if CREAD is not set.
1683          */
1684         if ((termios->c_cflag & CREAD) == 0)
1685                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1686
1687         spin_unlock_irqrestore(&port->lock, flags);
1688 }
1689
1690 static const char *s3c24xx_serial_type(struct uart_port *port)
1691 {
1692         const struct s3c24xx_uart_port *ourport = to_ourport(port);
1693
1694         switch (ourport->info->type) {
1695         case TYPE_S3C24XX:
1696                 return "S3C24XX";
1697         case TYPE_S3C6400:
1698                 return "S3C6400/10";
1699         case TYPE_APPLE_S5L:
1700                 return "APPLE S5L";
1701         default:
1702                 return NULL;
1703         }
1704 }
1705
1706 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1707 {
1708         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1709
1710         if (flags & UART_CONFIG_TYPE)
1711                 port->type = info->port_type;
1712 }
1713
1714 /*
1715  * verify the new serial_struct (for TIOCSSERIAL).
1716  */
1717 static int
1718 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1719 {
1720         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1721
1722         if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1723                 return -EINVAL;
1724
1725         return 0;
1726 }
1727
1728 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1729
1730 static struct console s3c24xx_serial_console;
1731
1732 static void __init s3c24xx_serial_register_console(void)
1733 {
1734         register_console(&s3c24xx_serial_console);
1735 }
1736
1737 static void s3c24xx_serial_unregister_console(void)
1738 {
1739         if (console_is_registered(&s3c24xx_serial_console))
1740                 unregister_console(&s3c24xx_serial_console);
1741 }
1742
1743 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1744 #else
1745 static inline void s3c24xx_serial_register_console(void) { }
1746 static inline void s3c24xx_serial_unregister_console(void) { }
1747 #define S3C24XX_SERIAL_CONSOLE NULL
1748 #endif
1749
1750 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1751 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1752 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1753                          unsigned char c);
1754 #endif
1755
1756 static const struct uart_ops s3c24xx_serial_ops = {
1757         .pm             = s3c24xx_serial_pm,
1758         .tx_empty       = s3c24xx_serial_tx_empty,
1759         .get_mctrl      = s3c24xx_serial_get_mctrl,
1760         .set_mctrl      = s3c24xx_serial_set_mctrl,
1761         .stop_tx        = s3c24xx_serial_stop_tx,
1762         .start_tx       = s3c24xx_serial_start_tx,
1763         .stop_rx        = s3c24xx_serial_stop_rx,
1764         .break_ctl      = s3c24xx_serial_break_ctl,
1765         .startup        = s3c24xx_serial_startup,
1766         .shutdown       = s3c24xx_serial_shutdown,
1767         .set_termios    = s3c24xx_serial_set_termios,
1768         .type           = s3c24xx_serial_type,
1769         .config_port    = s3c24xx_serial_config_port,
1770         .verify_port    = s3c24xx_serial_verify_port,
1771 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1772         .poll_get_char = s3c24xx_serial_get_poll_char,
1773         .poll_put_char = s3c24xx_serial_put_poll_char,
1774 #endif
1775 };
1776
1777 static const struct uart_ops s3c64xx_serial_ops = {
1778         .pm             = s3c24xx_serial_pm,
1779         .tx_empty       = s3c24xx_serial_tx_empty,
1780         .get_mctrl      = s3c24xx_serial_get_mctrl,
1781         .set_mctrl      = s3c24xx_serial_set_mctrl,
1782         .stop_tx        = s3c24xx_serial_stop_tx,
1783         .start_tx       = s3c24xx_serial_start_tx,
1784         .stop_rx        = s3c24xx_serial_stop_rx,
1785         .break_ctl      = s3c24xx_serial_break_ctl,
1786         .startup        = s3c64xx_serial_startup,
1787         .shutdown       = s3c64xx_serial_shutdown,
1788         .set_termios    = s3c24xx_serial_set_termios,
1789         .type           = s3c24xx_serial_type,
1790         .config_port    = s3c24xx_serial_config_port,
1791         .verify_port    = s3c24xx_serial_verify_port,
1792 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1793         .poll_get_char = s3c24xx_serial_get_poll_char,
1794         .poll_put_char = s3c24xx_serial_put_poll_char,
1795 #endif
1796 };
1797
1798 static const struct uart_ops apple_s5l_serial_ops = {
1799         .pm             = s3c24xx_serial_pm,
1800         .tx_empty       = s3c24xx_serial_tx_empty,
1801         .get_mctrl      = s3c24xx_serial_get_mctrl,
1802         .set_mctrl      = s3c24xx_serial_set_mctrl,
1803         .stop_tx        = s3c24xx_serial_stop_tx,
1804         .start_tx       = s3c24xx_serial_start_tx,
1805         .stop_rx        = s3c24xx_serial_stop_rx,
1806         .break_ctl      = s3c24xx_serial_break_ctl,
1807         .startup        = apple_s5l_serial_startup,
1808         .shutdown       = apple_s5l_serial_shutdown,
1809         .set_termios    = s3c24xx_serial_set_termios,
1810         .type           = s3c24xx_serial_type,
1811         .config_port    = s3c24xx_serial_config_port,
1812         .verify_port    = s3c24xx_serial_verify_port,
1813 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1814         .poll_get_char = s3c24xx_serial_get_poll_char,
1815         .poll_put_char = s3c24xx_serial_put_poll_char,
1816 #endif
1817 };
1818
1819 static struct uart_driver s3c24xx_uart_drv = {
1820         .owner          = THIS_MODULE,
1821         .driver_name    = "s3c2410_serial",
1822         .nr             = UART_NR,
1823         .cons           = S3C24XX_SERIAL_CONSOLE,
1824         .dev_name       = S3C24XX_SERIAL_NAME,
1825         .major          = S3C24XX_SERIAL_MAJOR,
1826         .minor          = S3C24XX_SERIAL_MINOR,
1827 };
1828
1829 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1830
1831 static void s3c24xx_serial_init_port_default(int index) {
1832         struct uart_port *port = &s3c24xx_serial_ports[index].port;
1833
1834         spin_lock_init(&port->lock);
1835
1836         port->iotype = UPIO_MEM;
1837         port->uartclk = 0;
1838         port->fifosize = 16;
1839         port->ops = &s3c24xx_serial_ops;
1840         port->flags = UPF_BOOT_AUTOCONF;
1841         port->line = index;
1842 }
1843
1844 /* s3c24xx_serial_resetport
1845  *
1846  * reset the fifos and other the settings.
1847  */
1848
1849 static void s3c24xx_serial_resetport(struct uart_port *port,
1850                                      const struct s3c2410_uartcfg *cfg)
1851 {
1852         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1853         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1854
1855         ucon &= (info->clksel_mask | info->ucon_mask);
1856         wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1857
1858         /* reset both fifos */
1859         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1860         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1861
1862         /* some delay is required after fifo reset */
1863         udelay(1);
1864 }
1865
1866 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1867 {
1868         struct device *dev = ourport->port.dev;
1869         const struct s3c24xx_uart_info *info = ourport->info;
1870         char clk_name[MAX_CLK_NAME_LENGTH];
1871         unsigned int clk_sel;
1872         struct clk *clk;
1873         int clk_num;
1874         int ret;
1875
1876         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1877         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1878                 if (!(clk_sel & (1 << clk_num)))
1879                         continue;
1880
1881                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1882                 clk = clk_get(dev, clk_name);
1883                 if (IS_ERR(clk))
1884                         continue;
1885
1886                 ret = clk_prepare_enable(clk);
1887                 if (ret) {
1888                         clk_put(clk);
1889                         continue;
1890                 }
1891
1892                 ourport->baudclk = clk;
1893                 ourport->baudclk_rate = clk_get_rate(clk);
1894                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1895
1896                 return 0;
1897         }
1898
1899         return -EINVAL;
1900 }
1901
1902 /* s3c24xx_serial_init_port
1903  *
1904  * initialise a single serial port from the platform device given
1905  */
1906
1907 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1908                                     struct platform_device *platdev)
1909 {
1910         struct uart_port *port = &ourport->port;
1911         const struct s3c2410_uartcfg *cfg = ourport->cfg;
1912         struct resource *res;
1913         int ret;
1914
1915         if (platdev == NULL)
1916                 return -ENODEV;
1917
1918         if (port->mapbase != 0)
1919                 return -EINVAL;
1920
1921         /* setup info for port */
1922         port->dev       = &platdev->dev;
1923
1924         port->uartclk = 1;
1925
1926         if (cfg->uart_flags & UPF_CONS_FLOW) {
1927                 dev_dbg(port->dev, "enabling flow control\n");
1928                 port->flags |= UPF_CONS_FLOW;
1929         }
1930
1931         /* sort our the physical and virtual addresses for each UART */
1932
1933         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1934         if (res == NULL) {
1935                 dev_err(port->dev, "failed to find memory resource for uart\n");
1936                 return -EINVAL;
1937         }
1938
1939         dev_dbg(port->dev, "resource %pR)\n", res);
1940
1941         port->membase = devm_ioremap_resource(port->dev, res);
1942         if (IS_ERR(port->membase)) {
1943                 dev_err(port->dev, "failed to remap controller address\n");
1944                 return -EBUSY;
1945         }
1946
1947         port->mapbase = res->start;
1948         ret = platform_get_irq(platdev, 0);
1949         if (ret < 0) {
1950                 port->irq = 0;
1951         } else {
1952                 port->irq = ret;
1953                 ourport->rx_irq = ret;
1954                 ourport->tx_irq = ret + 1;
1955         }
1956
1957         switch (ourport->info->type) {
1958         case TYPE_S3C24XX:
1959                 ret = platform_get_irq(platdev, 1);
1960                 if (ret > 0)
1961                         ourport->tx_irq = ret;
1962                 break;
1963         default:
1964                 break;
1965         }
1966
1967         /*
1968          * DMA is currently supported only on DT platforms, if DMA properties
1969          * are specified.
1970          */
1971         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1972                                                      "dmas", NULL)) {
1973                 ourport->dma = devm_kzalloc(port->dev,
1974                                             sizeof(*ourport->dma),
1975                                             GFP_KERNEL);
1976                 if (!ourport->dma) {
1977                         ret = -ENOMEM;
1978                         goto err;
1979                 }
1980         }
1981
1982         ourport->clk    = clk_get(&platdev->dev, "uart");
1983         if (IS_ERR(ourport->clk)) {
1984                 pr_err("%s: Controller clock not found\n",
1985                                 dev_name(&platdev->dev));
1986                 ret = PTR_ERR(ourport->clk);
1987                 goto err;
1988         }
1989
1990         ret = clk_prepare_enable(ourport->clk);
1991         if (ret) {
1992                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1993                 clk_put(ourport->clk);
1994                 goto err;
1995         }
1996
1997         ret = s3c24xx_serial_enable_baudclk(ourport);
1998         if (ret)
1999                 pr_warn("uart: failed to enable baudclk\n");
2000
2001         /* Keep all interrupts masked and cleared */
2002         switch (ourport->info->type) {
2003         case TYPE_S3C6400:
2004                 wr_regl(port, S3C64XX_UINTM, 0xf);
2005                 wr_regl(port, S3C64XX_UINTP, 0xf);
2006                 wr_regl(port, S3C64XX_UINTSP, 0xf);
2007                 break;
2008         case TYPE_APPLE_S5L: {
2009                 unsigned int ucon;
2010
2011                 ucon = rd_regl(port, S3C2410_UCON);
2012                 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2013                         APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2014                         APPLE_S5L_UCON_RXTO_ENA_MSK);
2015                 wr_regl(port, S3C2410_UCON, ucon);
2016
2017                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2018                 break;
2019         }
2020         default:
2021                 break;
2022         }
2023
2024         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2025                 &port->mapbase, port->membase, port->irq,
2026                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2027
2028         /* reset the fifos (and setup the uart) */
2029         s3c24xx_serial_resetport(port, cfg);
2030
2031         return 0;
2032
2033 err:
2034         port->mapbase = 0;
2035         return ret;
2036 }
2037
2038 /* Device driver serial port probe */
2039
2040 static int probe_index;
2041
2042 static inline const struct s3c24xx_serial_drv_data *
2043 s3c24xx_get_driver_data(struct platform_device *pdev)
2044 {
2045         if (dev_of_node(&pdev->dev))
2046                 return of_device_get_match_data(&pdev->dev);
2047
2048         return (struct s3c24xx_serial_drv_data *)
2049                         platform_get_device_id(pdev)->driver_data;
2050 }
2051
2052 static int s3c24xx_serial_probe(struct platform_device *pdev)
2053 {
2054         struct device_node *np = pdev->dev.of_node;
2055         struct s3c24xx_uart_port *ourport;
2056         int index = probe_index;
2057         int ret, prop = 0;
2058
2059         if (np) {
2060                 ret = of_alias_get_id(np, "serial");
2061                 if (ret >= 0)
2062                         index = ret;
2063         }
2064
2065         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2066                 dev_err(&pdev->dev, "serial%d out of range\n", index);
2067                 return -EINVAL;
2068         }
2069         ourport = &s3c24xx_serial_ports[index];
2070
2071         s3c24xx_serial_init_port_default(index);
2072
2073         ourport->drv_data = s3c24xx_get_driver_data(pdev);
2074         if (!ourport->drv_data) {
2075                 dev_err(&pdev->dev, "could not find driver data\n");
2076                 return -ENODEV;
2077         }
2078
2079         ourport->baudclk = ERR_PTR(-EINVAL);
2080         ourport->info = &ourport->drv_data->info;
2081         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2082                         dev_get_platdata(&pdev->dev) :
2083                         &ourport->drv_data->def_cfg;
2084
2085         switch (ourport->info->type) {
2086         case TYPE_S3C24XX:
2087                 ourport->port.ops = &s3c24xx_serial_ops;
2088                 break;
2089         case TYPE_S3C6400:
2090                 ourport->port.ops = &s3c64xx_serial_ops;
2091                 break;
2092         case TYPE_APPLE_S5L:
2093                 ourport->port.ops = &apple_s5l_serial_ops;
2094                 break;
2095         }
2096
2097         if (np) {
2098                 of_property_read_u32(np,
2099                         "samsung,uart-fifosize", &ourport->port.fifosize);
2100
2101                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2102                         switch (prop) {
2103                         case 1:
2104                                 ourport->port.iotype = UPIO_MEM;
2105                                 break;
2106                         case 4:
2107                                 ourport->port.iotype = UPIO_MEM32;
2108                                 break;
2109                         default:
2110                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2111                                                 prop);
2112                                 return -EINVAL;
2113                         }
2114                 }
2115         }
2116
2117         if (ourport->drv_data->fifosize[index])
2118                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2119         else if (ourport->info->fifosize)
2120                 ourport->port.fifosize = ourport->info->fifosize;
2121         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2122
2123         /*
2124          * DMA transfers must be aligned at least to cache line size,
2125          * so find minimal transfer size suitable for DMA mode
2126          */
2127         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2128                                     dma_get_cache_alignment());
2129
2130         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2131
2132         ret = s3c24xx_serial_init_port(ourport, pdev);
2133         if (ret < 0)
2134                 return ret;
2135
2136         if (!s3c24xx_uart_drv.state) {
2137                 ret = uart_register_driver(&s3c24xx_uart_drv);
2138                 if (ret < 0) {
2139                         pr_err("Failed to register Samsung UART driver\n");
2140                         return ret;
2141                 }
2142         }
2143
2144         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2145         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2146         platform_set_drvdata(pdev, &ourport->port);
2147
2148         /*
2149          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2150          * so that a potential re-enablement through the pm-callback overlaps
2151          * and keeps the clock enabled in this case.
2152          */
2153         clk_disable_unprepare(ourport->clk);
2154         if (!IS_ERR(ourport->baudclk))
2155                 clk_disable_unprepare(ourport->baudclk);
2156
2157         probe_index++;
2158
2159         return 0;
2160 }
2161
2162 static int s3c24xx_serial_remove(struct platform_device *dev)
2163 {
2164         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2165
2166         if (port) {
2167                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2168         }
2169
2170         uart_unregister_driver(&s3c24xx_uart_drv);
2171
2172         return 0;
2173 }
2174
2175 /* UART power management code */
2176 #ifdef CONFIG_PM_SLEEP
2177 static int s3c24xx_serial_suspend(struct device *dev)
2178 {
2179         struct uart_port *port = s3c24xx_dev_to_port(dev);
2180
2181         if (port)
2182                 uart_suspend_port(&s3c24xx_uart_drv, port);
2183
2184         return 0;
2185 }
2186
2187 static int s3c24xx_serial_resume(struct device *dev)
2188 {
2189         struct uart_port *port = s3c24xx_dev_to_port(dev);
2190         struct s3c24xx_uart_port *ourport = to_ourport(port);
2191
2192         if (port) {
2193                 clk_prepare_enable(ourport->clk);
2194                 if (!IS_ERR(ourport->baudclk))
2195                         clk_prepare_enable(ourport->baudclk);
2196                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2197                 if (!IS_ERR(ourport->baudclk))
2198                         clk_disable_unprepare(ourport->baudclk);
2199                 clk_disable_unprepare(ourport->clk);
2200
2201                 uart_resume_port(&s3c24xx_uart_drv, port);
2202         }
2203
2204         return 0;
2205 }
2206
2207 static int s3c24xx_serial_resume_noirq(struct device *dev)
2208 {
2209         struct uart_port *port = s3c24xx_dev_to_port(dev);
2210         struct s3c24xx_uart_port *ourport = to_ourport(port);
2211
2212         if (port) {
2213                 /* restore IRQ mask */
2214                 switch (ourport->info->type) {
2215                 case TYPE_S3C6400: {
2216                         unsigned int uintm = 0xf;
2217
2218                         if (ourport->tx_enabled)
2219                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2220                         if (ourport->rx_enabled)
2221                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2222                         clk_prepare_enable(ourport->clk);
2223                         if (!IS_ERR(ourport->baudclk))
2224                                 clk_prepare_enable(ourport->baudclk);
2225                         wr_regl(port, S3C64XX_UINTM, uintm);
2226                         if (!IS_ERR(ourport->baudclk))
2227                                 clk_disable_unprepare(ourport->baudclk);
2228                         clk_disable_unprepare(ourport->clk);
2229                         break;
2230                 }
2231                 case TYPE_APPLE_S5L: {
2232                         unsigned int ucon;
2233                         int ret;
2234
2235                         ret = clk_prepare_enable(ourport->clk);
2236                         if (ret) {
2237                                 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2238                                 return ret;
2239                         }
2240                         if (!IS_ERR(ourport->baudclk)) {
2241                                 ret = clk_prepare_enable(ourport->baudclk);
2242                                 if (ret) {
2243                                         dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2244                                         clk_disable_unprepare(ourport->clk);
2245                                         return ret;
2246                                 }
2247                         }
2248
2249                         ucon = rd_regl(port, S3C2410_UCON);
2250
2251                         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2252                                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2253                                   APPLE_S5L_UCON_RXTO_ENA_MSK);
2254
2255                         if (ourport->tx_enabled)
2256                                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2257                         if (ourport->rx_enabled)
2258                                 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2259                                         APPLE_S5L_UCON_RXTO_ENA_MSK;
2260
2261                         wr_regl(port, S3C2410_UCON, ucon);
2262
2263                         if (!IS_ERR(ourport->baudclk))
2264                                 clk_disable_unprepare(ourport->baudclk);
2265                         clk_disable_unprepare(ourport->clk);
2266                         break;
2267                 }
2268                 default:
2269                         break;
2270                 }
2271         }
2272
2273         return 0;
2274 }
2275
2276 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2277         SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume)
2278         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq)
2279 };
2280 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2281
2282 #else /* !CONFIG_PM_SLEEP */
2283
2284 #define SERIAL_SAMSUNG_PM_OPS   NULL
2285 #endif /* CONFIG_PM_SLEEP */
2286
2287 /* Console code */
2288
2289 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2290
2291 static struct uart_port *cons_uart;
2292
2293 static int
2294 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2295 {
2296         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2297         unsigned long ufstat, utrstat;
2298
2299         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2300                 /* fifo mode - check amount of data in fifo registers... */
2301
2302                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2303                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2304         }
2305
2306         /* in non-fifo mode, we go and use the tx buffer empty */
2307
2308         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2309         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2310 }
2311
2312 static bool
2313 s3c24xx_port_configured(unsigned int ucon)
2314 {
2315         /* consider the serial port configured if the tx/rx mode set */
2316         return (ucon & 0xf) != 0;
2317 }
2318
2319 #ifdef CONFIG_CONSOLE_POLL
2320 /*
2321  * Console polling routines for writing and reading from the uart while
2322  * in an interrupt or debug context.
2323  */
2324
2325 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2326 {
2327         const struct s3c24xx_uart_port *ourport = to_ourport(port);
2328         unsigned int ufstat;
2329
2330         ufstat = rd_regl(port, S3C2410_UFSTAT);
2331         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2332                 return NO_POLL_CHAR;
2333
2334         return rd_reg(port, S3C2410_URXH);
2335 }
2336
2337 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2338                 unsigned char c)
2339 {
2340         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2341         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2342
2343         /* not possible to xmit on unconfigured port */
2344         if (!s3c24xx_port_configured(ucon))
2345                 return;
2346
2347         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2348                 cpu_relax();
2349         wr_reg(port, S3C2410_UTXH, c);
2350 }
2351
2352 #endif /* CONFIG_CONSOLE_POLL */
2353
2354 static void
2355 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2356 {
2357         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2358
2359         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2360                 cpu_relax();
2361         wr_reg(port, S3C2410_UTXH, ch);
2362 }
2363
2364 static void
2365 s3c24xx_serial_console_write(struct console *co, const char *s,
2366                              unsigned int count)
2367 {
2368         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2369         unsigned long flags;
2370         bool locked = true;
2371
2372         /* not possible to xmit on unconfigured port */
2373         if (!s3c24xx_port_configured(ucon))
2374                 return;
2375
2376         if (cons_uart->sysrq)
2377                 locked = false;
2378         else if (oops_in_progress)
2379                 locked = spin_trylock_irqsave(&cons_uart->lock, flags);
2380         else
2381                 spin_lock_irqsave(&cons_uart->lock, flags);
2382
2383         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2384
2385         if (locked)
2386                 spin_unlock_irqrestore(&cons_uart->lock, flags);
2387 }
2388
2389 /* Shouldn't be __init, as it can be instantiated from other module */
2390 static void
2391 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2392                            int *parity, int *bits)
2393 {
2394         struct clk *clk;
2395         unsigned int ulcon;
2396         unsigned int ucon;
2397         unsigned int ubrdiv;
2398         unsigned long rate;
2399         unsigned int clk_sel;
2400         char clk_name[MAX_CLK_NAME_LENGTH];
2401
2402         ulcon  = rd_regl(port, S3C2410_ULCON);
2403         ucon   = rd_regl(port, S3C2410_UCON);
2404         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2405
2406         if (s3c24xx_port_configured(ucon)) {
2407                 switch (ulcon & S3C2410_LCON_CSMASK) {
2408                 case S3C2410_LCON_CS5:
2409                         *bits = 5;
2410                         break;
2411                 case S3C2410_LCON_CS6:
2412                         *bits = 6;
2413                         break;
2414                 case S3C2410_LCON_CS7:
2415                         *bits = 7;
2416                         break;
2417                 case S3C2410_LCON_CS8:
2418                 default:
2419                         *bits = 8;
2420                         break;
2421                 }
2422
2423                 switch (ulcon & S3C2410_LCON_PMASK) {
2424                 case S3C2410_LCON_PEVEN:
2425                         *parity = 'e';
2426                         break;
2427
2428                 case S3C2410_LCON_PODD:
2429                         *parity = 'o';
2430                         break;
2431
2432                 case S3C2410_LCON_PNONE:
2433                 default:
2434                         *parity = 'n';
2435                 }
2436
2437                 /* now calculate the baud rate */
2438
2439                 clk_sel = s3c24xx_serial_getsource(port);
2440                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2441
2442                 clk = clk_get(port->dev, clk_name);
2443                 if (!IS_ERR(clk))
2444                         rate = clk_get_rate(clk);
2445                 else
2446                         rate = 1;
2447
2448                 *baud = rate / (16 * (ubrdiv + 1));
2449                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2450         }
2451 }
2452
2453 /* Shouldn't be __init, as it can be instantiated from other module */
2454 static int
2455 s3c24xx_serial_console_setup(struct console *co, char *options)
2456 {
2457         struct uart_port *port;
2458         int baud = 9600;
2459         int bits = 8;
2460         int parity = 'n';
2461         int flow = 'n';
2462
2463         /* is this a valid port */
2464
2465         if (co->index == -1 || co->index >= UART_NR)
2466                 co->index = 0;
2467
2468         port = &s3c24xx_serial_ports[co->index].port;
2469
2470         /* is the port configured? */
2471
2472         if (port->mapbase == 0x0)
2473                 return -ENODEV;
2474
2475         cons_uart = port;
2476
2477         /*
2478          * Check whether an invalid uart number has been specified, and
2479          * if so, search for the first available port that does have
2480          * console support.
2481          */
2482         if (options)
2483                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2484         else
2485                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2486
2487         dev_dbg(port->dev, "baud %d\n", baud);
2488
2489         return uart_set_options(port, co, baud, parity, bits, flow);
2490 }
2491
2492 static struct console s3c24xx_serial_console = {
2493         .name           = S3C24XX_SERIAL_NAME,
2494         .device         = uart_console_device,
2495         .flags          = CON_PRINTBUFFER,
2496         .index          = -1,
2497         .write          = s3c24xx_serial_console_write,
2498         .setup          = s3c24xx_serial_console_setup,
2499         .data           = &s3c24xx_uart_drv,
2500 };
2501 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2502
2503 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2504 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2505         .info = {
2506                 .name           = "Samsung S3C6400 UART",
2507                 .type           = TYPE_S3C6400,
2508                 .port_type      = PORT_S3C6400,
2509                 .fifosize       = 64,
2510                 .has_divslot    = 1,
2511                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2512                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2513                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2514                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2515                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2516                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2517                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2518                 .num_clks       = 4,
2519                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2520                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2521         },
2522         .def_cfg = {
2523                 .ucon           = S3C2410_UCON_DEFAULT,
2524                 .ufcon          = S3C2410_UFCON_DEFAULT,
2525         },
2526 };
2527 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2528 #else
2529 #define S3C6400_SERIAL_DRV_DATA NULL
2530 #endif
2531
2532 #ifdef CONFIG_CPU_S5PV210
2533 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2534         .info = {
2535                 .name           = "Samsung S5PV210 UART",
2536                 .type           = TYPE_S3C6400,
2537                 .port_type      = PORT_S3C6400,
2538                 .has_divslot    = 1,
2539                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2540                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2541                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2542                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2543                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2544                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2545                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2546                 .num_clks       = 2,
2547                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2548                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2549         },
2550         .def_cfg = {
2551                 .ucon           = S5PV210_UCON_DEFAULT,
2552                 .ufcon          = S5PV210_UFCON_DEFAULT,
2553         },
2554         .fifosize = { 256, 64, 16, 16 },
2555 };
2556 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2557 #else
2558 #define S5PV210_SERIAL_DRV_DATA NULL
2559 #endif
2560
2561 #if defined(CONFIG_ARCH_EXYNOS)
2562 #define EXYNOS_COMMON_SERIAL_DRV_DATA()                         \
2563         .info = {                                               \
2564                 .name           = "Samsung Exynos UART",        \
2565                 .type           = TYPE_S3C6400,                 \
2566                 .port_type      = PORT_S3C6400,                 \
2567                 .has_divslot    = 1,                            \
2568                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2569                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2570                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2571                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2572                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2573                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2574                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2575                 .num_clks       = 1,                            \
2576                 .clksel_mask    = 0,                            \
2577                 .clksel_shift   = 0,                            \
2578         },                                                      \
2579         .def_cfg = {                                            \
2580                 .ucon           = S5PV210_UCON_DEFAULT,         \
2581                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2582                 .has_fracval    = 1,                            \
2583         }                                                       \
2584
2585 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2586         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2587         .fifosize = { 256, 64, 16, 16 },
2588 };
2589
2590 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2591         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2592         .fifosize = { 64, 256, 16, 256 },
2593 };
2594
2595 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2596         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2597         .fifosize = { 256, 64, 64, 64 },
2598 };
2599
2600 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2601 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2602 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2603
2604 #else
2605 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2606 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2607 #define EXYNOS850_SERIAL_DRV_DATA NULL
2608 #endif
2609
2610 #ifdef CONFIG_ARCH_APPLE
2611 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2612         .info = {
2613                 .name           = "Apple S5L UART",
2614                 .type           = TYPE_APPLE_S5L,
2615                 .port_type      = PORT_8250,
2616                 .fifosize       = 16,
2617                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2618                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2619                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2620                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2621                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2622                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2623                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2624                 .num_clks       = 1,
2625                 .clksel_mask    = 0,
2626                 .clksel_shift   = 0,
2627                 .ucon_mask      = APPLE_S5L_UCON_MASK,
2628         },
2629         .def_cfg = {
2630                 .ucon           = APPLE_S5L_UCON_DEFAULT,
2631                 .ufcon          = S3C2410_UFCON_DEFAULT,
2632         },
2633 };
2634 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2635 #else
2636 #define S5L_SERIAL_DRV_DATA NULL
2637 #endif
2638
2639 #if defined(CONFIG_ARCH_ARTPEC)
2640 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2641         .info = {
2642                 .name           = "Axis ARTPEC-8 UART",
2643                 .type           = TYPE_S3C6400,
2644                 .port_type      = PORT_S3C6400,
2645                 .fifosize       = 64,
2646                 .has_divslot    = 1,
2647                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2648                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2649                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2650                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2651                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2652                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2653                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2654                 .num_clks       = 1,
2655                 .clksel_mask    = 0,
2656                 .clksel_shift   = 0,
2657         },
2658         .def_cfg = {
2659                 .ucon           = S5PV210_UCON_DEFAULT,
2660                 .ufcon          = S5PV210_UFCON_DEFAULT,
2661                 .has_fracval    = 1,
2662         }
2663 };
2664 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2665 #else
2666 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2667 #endif
2668
2669 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2670         {
2671                 .name           = "s3c6400-uart",
2672                 .driver_data    = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2673         }, {
2674                 .name           = "s5pv210-uart",
2675                 .driver_data    = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2676         }, {
2677                 .name           = "exynos4210-uart",
2678                 .driver_data    = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2679         }, {
2680                 .name           = "exynos5433-uart",
2681                 .driver_data    = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2682         }, {
2683                 .name           = "s5l-uart",
2684                 .driver_data    = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2685         }, {
2686                 .name           = "exynos850-uart",
2687                 .driver_data    = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2688         }, {
2689                 .name           = "artpec8-uart",
2690                 .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2691         },
2692         { },
2693 };
2694 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2695
2696 #ifdef CONFIG_OF
2697 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2698         { .compatible = "samsung,s3c6400-uart",
2699                 .data = S3C6400_SERIAL_DRV_DATA },
2700         { .compatible = "samsung,s5pv210-uart",
2701                 .data = S5PV210_SERIAL_DRV_DATA },
2702         { .compatible = "samsung,exynos4210-uart",
2703                 .data = EXYNOS4210_SERIAL_DRV_DATA },
2704         { .compatible = "samsung,exynos5433-uart",
2705                 .data = EXYNOS5433_SERIAL_DRV_DATA },
2706         { .compatible = "apple,s5l-uart",
2707                 .data = S5L_SERIAL_DRV_DATA },
2708         { .compatible = "samsung,exynos850-uart",
2709                 .data = EXYNOS850_SERIAL_DRV_DATA },
2710         { .compatible = "axis,artpec8-uart",
2711                 .data = ARTPEC8_SERIAL_DRV_DATA },
2712         {},
2713 };
2714 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2715 #endif
2716
2717 static struct platform_driver samsung_serial_driver = {
2718         .probe          = s3c24xx_serial_probe,
2719         .remove         = s3c24xx_serial_remove,
2720         .id_table       = s3c24xx_serial_driver_ids,
2721         .driver         = {
2722                 .name   = "samsung-uart",
2723                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2724                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2725         },
2726 };
2727
2728 static int __init samsung_serial_init(void)
2729 {
2730         int ret;
2731
2732         s3c24xx_serial_register_console();
2733
2734         ret = platform_driver_register(&samsung_serial_driver);
2735         if (ret) {
2736                 s3c24xx_serial_unregister_console();
2737                 return ret;
2738         }
2739
2740         return 0;
2741 }
2742
2743 static void __exit samsung_serial_exit(void)
2744 {
2745         platform_driver_unregister(&samsung_serial_driver);
2746         s3c24xx_serial_unregister_console();
2747 }
2748
2749 module_init(samsung_serial_init);
2750 module_exit(samsung_serial_exit);
2751
2752 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2753 /*
2754  * Early console.
2755  */
2756
2757 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2758 {
2759         switch (port->iotype) {
2760         case UPIO_MEM:
2761                 writeb(val, portaddr(port, reg));
2762                 break;
2763         case UPIO_MEM32:
2764                 writel(val, portaddr(port, reg));
2765                 break;
2766         }
2767 }
2768
2769 struct samsung_early_console_data {
2770         u32 txfull_mask;
2771         u32 rxfifo_mask;
2772 };
2773
2774 static void samsung_early_busyuart(const struct uart_port *port)
2775 {
2776         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2777                 ;
2778 }
2779
2780 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2781 {
2782         const struct samsung_early_console_data *data = port->private_data;
2783
2784         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2785                 ;
2786 }
2787
2788 static void samsung_early_putc(struct uart_port *port, unsigned char c)
2789 {
2790         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2791                 samsung_early_busyuart_fifo(port);
2792         else
2793                 samsung_early_busyuart(port);
2794
2795         wr_reg_barrier(port, S3C2410_UTXH, c);
2796 }
2797
2798 static void samsung_early_write(struct console *con, const char *s,
2799                                 unsigned int n)
2800 {
2801         struct earlycon_device *dev = con->data;
2802
2803         uart_console_write(&dev->port, s, n, samsung_early_putc);
2804 }
2805
2806 static int samsung_early_read(struct console *con, char *s, unsigned int n)
2807 {
2808         struct earlycon_device *dev = con->data;
2809         const struct samsung_early_console_data *data = dev->port.private_data;
2810         int ch, ufstat, num_read = 0;
2811
2812         while (num_read < n) {
2813                 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2814                 if (!(ufstat & data->rxfifo_mask))
2815                         break;
2816                 ch = rd_reg(&dev->port, S3C2410_URXH);
2817                 if (ch == NO_POLL_CHAR)
2818                         break;
2819
2820                 s[num_read++] = ch;
2821         }
2822
2823         return num_read;
2824 }
2825
2826 static int __init samsung_early_console_setup(struct earlycon_device *device,
2827                                               const char *opt)
2828 {
2829         if (!device->port.membase)
2830                 return -ENODEV;
2831
2832         device->con->write = samsung_early_write;
2833         device->con->read = samsung_early_read;
2834         return 0;
2835 }
2836
2837 /* S3C2410 */
2838 static struct samsung_early_console_data s3c2410_early_console_data = {
2839         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2840         .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2841 };
2842
2843 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2844                                               const char *opt)
2845 {
2846         device->port.private_data = &s3c2410_early_console_data;
2847         return samsung_early_console_setup(device, opt);
2848 }
2849
2850 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2851                         s3c2410_early_console_setup);
2852
2853 /* S3C2412, S3C2440, S3C64xx */
2854 static struct samsung_early_console_data s3c2440_early_console_data = {
2855         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2856         .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2857 };
2858
2859 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2860                                               const char *opt)
2861 {
2862         device->port.private_data = &s3c2440_early_console_data;
2863         return samsung_early_console_setup(device, opt);
2864 }
2865
2866 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2867                         s3c2440_early_console_setup);
2868 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2869                         s3c2440_early_console_setup);
2870 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2871                         s3c2440_early_console_setup);
2872
2873 /* S5PV210, Exynos */
2874 static struct samsung_early_console_data s5pv210_early_console_data = {
2875         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2876         .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2877 };
2878
2879 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2880                                               const char *opt)
2881 {
2882         device->port.private_data = &s5pv210_early_console_data;
2883         return samsung_early_console_setup(device, opt);
2884 }
2885
2886 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2887                         s5pv210_early_console_setup);
2888 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2889                         s5pv210_early_console_setup);
2890 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2891                         s5pv210_early_console_setup);
2892
2893 /* Apple S5L */
2894 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2895                                                 const char *opt)
2896 {
2897         /* Close enough to S3C2410 for earlycon... */
2898         device->port.private_data = &s3c2410_early_console_data;
2899
2900 #ifdef CONFIG_ARM64
2901         /* ... but we need to override the existing fixmap entry as nGnRnE */
2902         __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2903                      __pgprot(PROT_DEVICE_nGnRnE));
2904 #endif
2905         return samsung_early_console_setup(device, opt);
2906 }
2907
2908 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2909 #endif
2910
2911 MODULE_ALIAS("platform:samsung-uart");
2912 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2913 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2914 MODULE_LICENSE("GPL v2");